TargetSelectionDAG.td revision cfe33c46aa50f04adb0431243e7d25f79b719ac6
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand has floating-point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisVec - The specified operand has a vector type. 40class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42// SDTCisSameAs - The two specified operands have identical types. 43class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45} 46 47// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48// smaller than the 'Other' operand. 49class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51} 52 53class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55} 56 57/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58/// type as the element type of OtherOp, which is a vector type. 59class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62} 63 64/// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 65/// with length less that of OtherOp, which is a vector type. 66class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 67 : SDTypeConstraint<ThisOp> { 68 int OtherOpNum = OtherOp; 69} 70 71//===----------------------------------------------------------------------===// 72// Selection DAG Type Profile definitions. 73// 74// These use the constraints defined above to describe the type requirements of 75// the various nodes. These are not hard coded into tblgen, allowing targets to 76// add their own if needed. 77// 78 79// SDTypeProfile - This profile describes the type requirements of a Selection 80// DAG node. 81class SDTypeProfile<int numresults, int numoperands, 82 list<SDTypeConstraint> constraints> { 83 int NumResults = numresults; 84 int NumOperands = numoperands; 85 list<SDTypeConstraint> Constraints = constraints; 86} 87 88// Builtin profiles. 89def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 90def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 91def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 92def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 93def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 94def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 95 96def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 98]>; 99def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 101]>; 102def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 104]>; 105 106def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 108]>; 109def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 111]>; 112def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 114]>; 115def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 116 SDTCisSameAs<0, 1>, SDTCisInt<0> 117]>; 118def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 120]>; 121def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 123]>; 124def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 125 SDTCisSameAs<0, 1>, SDTCisFP<0> 126]>; 127def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 129]>; 130def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 132]>; 133def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 134 SDTCisFP<0>, SDTCisInt<1> 135]>; 136def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 137 SDTCisInt<0>, SDTCisFP<1> 138]>; 139def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 141 SDTCisVTSmallerThanOp<2, 1> 142]>; 143 144def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 146]>; 147 148def SDTSelect : SDTypeProfile<1, 3, [ // select 149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 150]>; 151 152def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 153 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 154 SDTCisVT<5, OtherVT> 155]>; 156 157def SDTBr : SDTypeProfile<0, 1, [ // br 158 SDTCisVT<0, OtherVT> 159]>; 160 161def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 162 SDTCisInt<0>, SDTCisVT<1, OtherVT> 163]>; 164 165def SDTBrind : SDTypeProfile<0, 1, [ // brind 166 SDTCisPtrTy<0> 167]>; 168 169def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 170 171def SDTLoad : SDTypeProfile<1, 1, [ // load 172 SDTCisPtrTy<1> 173]>; 174 175def SDTStore : SDTypeProfile<0, 2, [ // store 176 SDTCisPtrTy<1> 177]>; 178 179def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 180 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 181]>; 182 183def SDTVecShuffle : SDTypeProfile<1, 2, [ 184 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 185]>; 186def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 187 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 188]>; 189def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 190 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 191]>; 192 193def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 194 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 195]>; 196def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 197 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 198]>; 199 200def SDTPrefetch : SDTypeProfile<0, 3, [ // prefetch 201 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1> 202]>; 203 204def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier 205 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 206 SDTCisInt<0> 207]>; 208def SDTAtomic3 : SDTypeProfile<1, 3, [ 209 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 210]>; 211def SDTAtomic2 : SDTypeProfile<1, 2, [ 212 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 213]>; 214 215def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 216 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 217]>; 218 219class SDCallSeqStart<list<SDTypeConstraint> constraints> : 220 SDTypeProfile<0, 1, constraints>; 221class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 222 SDTypeProfile<0, 2, constraints>; 223 224//===----------------------------------------------------------------------===// 225// Selection DAG Node Properties. 226// 227// Note: These are hard coded into tblgen. 228// 229class SDNodeProperty; 230def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 231def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 232def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 233def SDNPOutGlue : SDNodeProperty; // Write a flag result 234def SDNPInGlue : SDNodeProperty; // Read a flag operand 235def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand 236def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 237def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 238def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 239def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 240def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 241def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match 242def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent 243 244//===----------------------------------------------------------------------===// 245// Selection DAG Pattern Operations 246class SDPatternOperator; 247 248//===----------------------------------------------------------------------===// 249// Selection DAG Node definitions. 250// 251class SDNode<string opcode, SDTypeProfile typeprof, 252 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 253 : SDPatternOperator { 254 string Opcode = opcode; 255 string SDClass = sdclass; 256 list<SDNodeProperty> Properties = props; 257 SDTypeProfile TypeProfile = typeprof; 258} 259 260// Special TableGen-recognized dag nodes 261def set; 262def implicit; 263def node; 264def srcvalue; 265 266def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 267def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 268def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 269def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 270def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 271def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 272def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 273def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 274 "GlobalAddressSDNode">; 275def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 276 "GlobalAddressSDNode">; 277def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 278 "GlobalAddressSDNode">; 279def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 280 "GlobalAddressSDNode">; 281def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 282 "ConstantPoolSDNode">; 283def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 284 "ConstantPoolSDNode">; 285def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 286 "JumpTableSDNode">; 287def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 288 "JumpTableSDNode">; 289def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 290 "FrameIndexSDNode">; 291def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 292 "FrameIndexSDNode">; 293def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 294 "ExternalSymbolSDNode">; 295def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 296 "ExternalSymbolSDNode">; 297def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 298 "BlockAddressSDNode">; 299def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 300 "BlockAddressSDNode">; 301 302def add : SDNode<"ISD::ADD" , SDTIntBinOp , 303 [SDNPCommutative, SDNPAssociative]>; 304def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 305def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 306 [SDNPCommutative, SDNPAssociative]>; 307def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 308def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 309def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 310def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 311def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 312def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 313def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 314def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 315def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 316def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 317def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 318def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 319def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 320def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 321def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 322def and : SDNode<"ISD::AND" , SDTIntBinOp, 323 [SDNPCommutative, SDNPAssociative]>; 324def or : SDNode<"ISD::OR" , SDTIntBinOp, 325 [SDNPCommutative, SDNPAssociative]>; 326def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 327 [SDNPCommutative, SDNPAssociative]>; 328def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 329 [SDNPCommutative, SDNPOutGlue]>; 330def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 331 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 332def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 333 [SDNPOutGlue]>; 334def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 335 [SDNPOutGlue, SDNPInGlue]>; 336 337def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 338def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 339def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 340def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 341def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 342def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 343def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 344def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 345def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 346def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 347def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 348def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 349 350 351def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 352def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 353def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 354def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 355def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 356def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 357def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 358def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 359def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 360def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 361def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 362def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 363def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 364def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 365def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 366def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 367def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 368 369def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 370def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 371def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 372 373def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 374def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 375def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 376def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 377def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>; 378def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>; 379 380def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 381def select : SDNode<"ISD::SELECT" , SDTSelect>; 382def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 383def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>; 384 385def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 386def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 387def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 388def trap : SDNode<"ISD::TRAP" , SDTNone, 389 [SDNPHasChain, SDNPSideEffect]>; 390 391def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 392 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 393 SDNPMemOperand]>; 394 395def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, 396 [SDNPHasChain, SDNPSideEffect]>; 397 398def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 399 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 400def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 401 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 402def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 403 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 404def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 405 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 406def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 407 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 408def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 409 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 410def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 411 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 412def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 413 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 414def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 415 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 416def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 417 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 418def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 419 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 420def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 421 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 422 423// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 424// and truncst (see below). 425def ld : SDNode<"ISD::LOAD" , SDTLoad, 426 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 427def st : SDNode<"ISD::STORE" , SDTStore, 428 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 429def ist : SDNode<"ISD::STORE" , SDTIStore, 430 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 431 432def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 433def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 434def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 435 []>; 436def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 437 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 438def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 439 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 440 441// This operator does not do subvector type checking. The ARM 442// backend, at least, needs it. 443def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 444 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 445 []>; 446 447// This operator does subvector type checking. 448def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 449def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 450 451// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 452// these internally. Don't reference these directly. 453def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 454 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 455 [SDNPHasChain]>; 456def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 457 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 458 [SDNPHasChain]>; 459def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 460 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 461 462// Do not use cvt directly. Use cvt forms below 463def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 464 465//===----------------------------------------------------------------------===// 466// Selection DAG Condition Codes 467 468class CondCode; // ISD::CondCode enums 469def SETOEQ : CondCode; def SETOGT : CondCode; 470def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 471def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 472def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 473def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 474 475def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 476def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 477 478 479//===----------------------------------------------------------------------===// 480// Selection DAG Node Transformation Functions. 481// 482// This mechanism allows targets to manipulate nodes in the output DAG once a 483// match has been formed. This is typically used to manipulate immediate 484// values. 485// 486class SDNodeXForm<SDNode opc, code xformFunction> { 487 SDNode Opcode = opc; 488 code XFormFunction = xformFunction; 489} 490 491def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 492 493 494//===----------------------------------------------------------------------===// 495// Selection DAG Pattern Fragments. 496// 497// Pattern fragments are reusable chunks of dags that match specific things. 498// They can take arguments and have C++ predicates that control whether they 499// match. They are intended to make the patterns for common instructions more 500// compact and readable. 501// 502 503/// PatFrag - Represents a pattern fragment. This can match something on the 504/// DAG, from a single node to multiple nested other fragments. 505/// 506class PatFrag<dag ops, dag frag, code pred = [{}], 507 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 508 dag Operands = ops; 509 dag Fragment = frag; 510 code Predicate = pred; 511 SDNodeXForm OperandTransform = xform; 512} 513 514// PatLeaf's are pattern fragments that have no operands. This is just a helper 515// to define immediates and other common things concisely. 516class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 517 : PatFrag<(ops), frag, pred, xform>; 518 519// Leaf fragments. 520 521def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 522def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 523 524def immAllOnesV: PatLeaf<(build_vector), [{ 525 return ISD::isBuildVectorAllOnes(N); 526}]>; 527def immAllZerosV: PatLeaf<(build_vector), [{ 528 return ISD::isBuildVectorAllZeros(N); 529}]>; 530 531 532 533// Other helper fragments. 534def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 535def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 536def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 537 538// load fragments. 539def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 540 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 541}]>; 542def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 543 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 544}]>; 545 546// extending load fragments. 547def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 548 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 549}]>; 550def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 551 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 552}]>; 553def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 554 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 555}]>; 556 557def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 558 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 559}]>; 560def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 561 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 562}]>; 563def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 564 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 565}]>; 566def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 567 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 568}]>; 569def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 570 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 571}]>; 572def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 573 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 574}]>; 575 576def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 577 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 578}]>; 579def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 580 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 581}]>; 582def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 583 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 584}]>; 585def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 586 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 587}]>; 588 589def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 590 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 591}]>; 592def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 593 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 594}]>; 595def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 596 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 597}]>; 598def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 599 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 600}]>; 601 602// store fragments. 603def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 604 (st node:$val, node:$ptr), [{ 605 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 606}]>; 607def store : PatFrag<(ops node:$val, node:$ptr), 608 (unindexedstore node:$val, node:$ptr), [{ 609 return !cast<StoreSDNode>(N)->isTruncatingStore(); 610}]>; 611 612// truncstore fragments. 613def truncstore : PatFrag<(ops node:$val, node:$ptr), 614 (unindexedstore node:$val, node:$ptr), [{ 615 return cast<StoreSDNode>(N)->isTruncatingStore(); 616}]>; 617def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 618 (truncstore node:$val, node:$ptr), [{ 619 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 620}]>; 621def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 622 (truncstore node:$val, node:$ptr), [{ 623 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 624}]>; 625def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 626 (truncstore node:$val, node:$ptr), [{ 627 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 628}]>; 629def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 630 (truncstore node:$val, node:$ptr), [{ 631 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 632}]>; 633def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 634 (truncstore node:$val, node:$ptr), [{ 635 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 636}]>; 637 638// indexed store fragments. 639def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 640 (ist node:$val, node:$base, node:$offset), [{ 641 return !cast<StoreSDNode>(N)->isTruncatingStore(); 642}]>; 643 644def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 645 (istore node:$val, node:$base, node:$offset), [{ 646 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 647 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 648}]>; 649 650def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 651 (ist node:$val, node:$base, node:$offset), [{ 652 return cast<StoreSDNode>(N)->isTruncatingStore(); 653}]>; 654def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 655 (itruncstore node:$val, node:$base, node:$offset), [{ 656 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 657 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 658}]>; 659def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 660 (pre_truncst node:$val, node:$base, node:$offset), [{ 661 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 662}]>; 663def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 664 (pre_truncst node:$val, node:$base, node:$offset), [{ 665 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 666}]>; 667def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 668 (pre_truncst node:$val, node:$base, node:$offset), [{ 669 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 670}]>; 671def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 672 (pre_truncst node:$val, node:$base, node:$offset), [{ 673 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 674}]>; 675def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 676 (pre_truncst node:$val, node:$base, node:$offset), [{ 677 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 678}]>; 679 680def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 681 (istore node:$val, node:$ptr, node:$offset), [{ 682 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 683 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 684}]>; 685 686def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 687 (itruncstore node:$val, node:$base, node:$offset), [{ 688 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 689 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 690}]>; 691def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 692 (post_truncst node:$val, node:$base, node:$offset), [{ 693 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 694}]>; 695def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 696 (post_truncst node:$val, node:$base, node:$offset), [{ 697 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 698}]>; 699def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 700 (post_truncst node:$val, node:$base, node:$offset), [{ 701 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 702}]>; 703def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 704 (post_truncst node:$val, node:$base, node:$offset), [{ 705 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 706}]>; 707def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 708 (post_truncst node:$val, node:$base, node:$offset), [{ 709 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 710}]>; 711 712// setcc convenience fragments. 713def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 714 (setcc node:$lhs, node:$rhs, SETOEQ)>; 715def setogt : PatFrag<(ops node:$lhs, node:$rhs), 716 (setcc node:$lhs, node:$rhs, SETOGT)>; 717def setoge : PatFrag<(ops node:$lhs, node:$rhs), 718 (setcc node:$lhs, node:$rhs, SETOGE)>; 719def setolt : PatFrag<(ops node:$lhs, node:$rhs), 720 (setcc node:$lhs, node:$rhs, SETOLT)>; 721def setole : PatFrag<(ops node:$lhs, node:$rhs), 722 (setcc node:$lhs, node:$rhs, SETOLE)>; 723def setone : PatFrag<(ops node:$lhs, node:$rhs), 724 (setcc node:$lhs, node:$rhs, SETONE)>; 725def seto : PatFrag<(ops node:$lhs, node:$rhs), 726 (setcc node:$lhs, node:$rhs, SETO)>; 727def setuo : PatFrag<(ops node:$lhs, node:$rhs), 728 (setcc node:$lhs, node:$rhs, SETUO)>; 729def setueq : PatFrag<(ops node:$lhs, node:$rhs), 730 (setcc node:$lhs, node:$rhs, SETUEQ)>; 731def setugt : PatFrag<(ops node:$lhs, node:$rhs), 732 (setcc node:$lhs, node:$rhs, SETUGT)>; 733def setuge : PatFrag<(ops node:$lhs, node:$rhs), 734 (setcc node:$lhs, node:$rhs, SETUGE)>; 735def setult : PatFrag<(ops node:$lhs, node:$rhs), 736 (setcc node:$lhs, node:$rhs, SETULT)>; 737def setule : PatFrag<(ops node:$lhs, node:$rhs), 738 (setcc node:$lhs, node:$rhs, SETULE)>; 739def setune : PatFrag<(ops node:$lhs, node:$rhs), 740 (setcc node:$lhs, node:$rhs, SETUNE)>; 741def seteq : PatFrag<(ops node:$lhs, node:$rhs), 742 (setcc node:$lhs, node:$rhs, SETEQ)>; 743def setgt : PatFrag<(ops node:$lhs, node:$rhs), 744 (setcc node:$lhs, node:$rhs, SETGT)>; 745def setge : PatFrag<(ops node:$lhs, node:$rhs), 746 (setcc node:$lhs, node:$rhs, SETGE)>; 747def setlt : PatFrag<(ops node:$lhs, node:$rhs), 748 (setcc node:$lhs, node:$rhs, SETLT)>; 749def setle : PatFrag<(ops node:$lhs, node:$rhs), 750 (setcc node:$lhs, node:$rhs, SETLE)>; 751def setne : PatFrag<(ops node:$lhs, node:$rhs), 752 (setcc node:$lhs, node:$rhs, SETNE)>; 753 754def atomic_cmp_swap_8 : 755 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 756 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 757 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 758}]>; 759def atomic_cmp_swap_16 : 760 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 761 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 762 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 763}]>; 764def atomic_cmp_swap_32 : 765 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 766 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 767 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 768}]>; 769def atomic_cmp_swap_64 : 770 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 771 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 772 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 773}]>; 774 775multiclass binary_atomic_op<SDNode atomic_op> { 776 def _8 : PatFrag<(ops node:$ptr, node:$val), 777 (atomic_op node:$ptr, node:$val), [{ 778 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 779 }]>; 780 def _16 : PatFrag<(ops node:$ptr, node:$val), 781 (atomic_op node:$ptr, node:$val), [{ 782 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 783 }]>; 784 def _32 : PatFrag<(ops node:$ptr, node:$val), 785 (atomic_op node:$ptr, node:$val), [{ 786 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 787 }]>; 788 def _64 : PatFrag<(ops node:$ptr, node:$val), 789 (atomic_op node:$ptr, node:$val), [{ 790 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 791 }]>; 792} 793 794defm atomic_load_add : binary_atomic_op<atomic_load_add>; 795defm atomic_swap : binary_atomic_op<atomic_swap>; 796defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 797defm atomic_load_and : binary_atomic_op<atomic_load_and>; 798defm atomic_load_or : binary_atomic_op<atomic_load_or>; 799defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 800defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 801defm atomic_load_min : binary_atomic_op<atomic_load_min>; 802defm atomic_load_max : binary_atomic_op<atomic_load_max>; 803defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 804defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 805 806//===----------------------------------------------------------------------===// 807// Selection DAG CONVERT_RNDSAT patterns 808 809def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 810 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 811 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 812 }]>; 813 814def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 815 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 816 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 817 }]>; 818 819def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 820 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 821 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 822 }]>; 823 824def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 825 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 826 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 827 }]>; 828 829def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 830 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 831 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 832 }]>; 833 834def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 835 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 836 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 837 }]>; 838 839def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 840 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 841 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 842 }]>; 843 844def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 845 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 846 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 847 }]>; 848 849def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 850 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 851 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 852 }]>; 853 854//===----------------------------------------------------------------------===// 855// Selection DAG Pattern Support. 856// 857// Patterns are what are actually matched against by the target-flavored 858// instruction selection DAG. Instructions defined by the target implicitly 859// define patterns in most cases, but patterns can also be explicitly added when 860// an operation is defined by a sequence of instructions (e.g. loading a large 861// immediate value on RISC targets that do not support immediates as large as 862// their GPRs). 863// 864 865class Pattern<dag patternToMatch, list<dag> resultInstrs> { 866 dag PatternToMatch = patternToMatch; 867 list<dag> ResultInstrs = resultInstrs; 868 list<Predicate> Predicates = []; // See class Instruction in Target.td. 869 int AddedComplexity = 0; // See class Instruction in Target.td. 870} 871 872// Pat - A simple (but common) form of a pattern, which produces a simple result 873// not needing a full list. 874class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 875 876//===----------------------------------------------------------------------===// 877// Complex pattern definitions. 878// 879 880// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 881// in C++. NumOperands is the number of operands returned by the select function; 882// SelectFunc is the name of the function used to pattern match the max. pattern; 883// RootNodes are the list of possible root nodes of the sub-dags to match. 884// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 885// 886class ComplexPattern<ValueType ty, int numops, string fn, 887 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 888 ValueType Ty = ty; 889 int NumOperands = numops; 890 string SelectFunc = fn; 891 list<SDNode> RootNodes = roots; 892 list<SDNodeProperty> Properties = props; 893} 894