TargetSelectionDAG.td revision e8cabf3c2eb835f9189a39c810654d9bd302f7ee
1//===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the target-independent interfaces used by SelectionDAG 11// instruction selection generators. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// Selection DAG Type Constraint definitions. 17// 18// Note that the semantics of these constraints are hard coded into tblgen. To 19// modify or add constraints, you have to hack tblgen. 20// 21 22class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24} 25 26// SDTCisVT - The specified operand has exactly this VT. 27class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29} 30 31class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33// SDTCisInt - The specified operand has integer type. 34class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36// SDTCisFP - The specified operand has floating-point type. 37class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39// SDTCisVec - The specified operand has a vector type. 40class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42// SDTCisSameAs - The two specified operands have identical types. 43class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45} 46 47// SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48// smaller than the 'Other' operand. 49class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51} 52 53class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55} 56 57/// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58/// type as the element type of OtherOp, which is a vector type. 59class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62} 63 64//===----------------------------------------------------------------------===// 65// Selection DAG Type Profile definitions. 66// 67// These use the constraints defined above to describe the type requirements of 68// the various nodes. These are not hard coded into tblgen, allowing targets to 69// add their own if needed. 70// 71 72// SDTypeProfile - This profile describes the type requirements of a Selection 73// DAG node. 74class SDTypeProfile<int numresults, int numoperands, 75 list<SDTypeConstraint> constraints> { 76 int NumResults = numresults; 77 int NumOperands = numoperands; 78 list<SDTypeConstraint> Constraints = constraints; 79} 80 81// Builtin profiles. 82def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 83def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 84def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 85def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 86def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 87def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 88 89def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 90 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 91]>; 92def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 93 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 94]>; 95def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 97]>; 98def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 99 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 100]>; 101def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 103]>; 104def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 105 SDTCisSameAs<0, 1>, SDTCisInt<0> 106]>; 107def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 108 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 109]>; 110def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 111 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 112]>; 113def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 114 SDTCisSameAs<0, 1>, SDTCisFP<0> 115]>; 116def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 117 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 118]>; 119def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 120 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 121]>; 122def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 123 SDTCisFP<0>, SDTCisInt<1> 124]>; 125def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 126 SDTCisInt<0>, SDTCisFP<1> 127]>; 128def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 129 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 130 SDTCisVTSmallerThanOp<2, 1> 131]>; 132 133def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 134 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 135]>; 136 137def SDTSelect : SDTypeProfile<1, 3, [ // select 138 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 139]>; 140 141def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 142 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 143 SDTCisVT<5, OtherVT> 144]>; 145 146def SDTBr : SDTypeProfile<0, 1, [ // br 147 SDTCisVT<0, OtherVT> 148]>; 149 150def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 151 SDTCisInt<0>, SDTCisVT<1, OtherVT> 152]>; 153 154def SDTBrind : SDTypeProfile<0, 1, [ // brind 155 SDTCisPtrTy<0> 156]>; 157 158def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 159 160def SDTLoad : SDTypeProfile<1, 1, [ // load 161 SDTCisPtrTy<1> 162]>; 163 164def SDTStore : SDTypeProfile<0, 2, [ // store 165 SDTCisPtrTy<1> 166]>; 167 168def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 169 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 170]>; 171 172def SDTVecShuffle : SDTypeProfile<1, 2, [ 173 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 174]>; 175def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 176 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 177]>; 178def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 179 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 180]>; 181 182def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch 183 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1> 184]>; 185 186def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier 187 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 188 SDTCisInt<0> 189]>; 190def STDAtomic3 : SDTypeProfile<1, 3, [ 191 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 192]>; 193def STDAtomic2 : SDTypeProfile<1, 2, [ 194 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 195]>; 196 197def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 198 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 199]>; 200 201class SDCallSeqStart<list<SDTypeConstraint> constraints> : 202 SDTypeProfile<0, 1, constraints>; 203class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 204 SDTypeProfile<0, 2, constraints>; 205 206//===----------------------------------------------------------------------===// 207// Selection DAG Node Properties. 208// 209// Note: These are hard coded into tblgen. 210// 211class SDNodeProperty; 212def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 213def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 214def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 215def SDNPOutFlag : SDNodeProperty; // Write a flag result 216def SDNPInFlag : SDNodeProperty; // Read a flag operand 217def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand 218def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 219def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 220def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 221def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 222def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 223 224//===----------------------------------------------------------------------===// 225// Selection DAG Node definitions. 226// 227class SDNode<string opcode, SDTypeProfile typeprof, 228 list<SDNodeProperty> props = [], string sdclass = "SDNode"> { 229 string Opcode = opcode; 230 string SDClass = sdclass; 231 list<SDNodeProperty> Properties = props; 232 SDTypeProfile TypeProfile = typeprof; 233} 234 235// Special TableGen-recognized dag nodes 236def set; 237def implicit; 238def parallel; 239def node; 240def srcvalue; 241 242def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 243def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 244def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 245def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 246def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 247def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 248def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 249def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 250 "GlobalAddressSDNode">; 251def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 252 "GlobalAddressSDNode">; 253def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 254 "GlobalAddressSDNode">; 255def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 256 "GlobalAddressSDNode">; 257def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 258 "ConstantPoolSDNode">; 259def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 260 "ConstantPoolSDNode">; 261def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 262 "JumpTableSDNode">; 263def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 264 "JumpTableSDNode">; 265def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 266 "FrameIndexSDNode">; 267def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 268 "FrameIndexSDNode">; 269def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 270 "ExternalSymbolSDNode">; 271def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 272 "ExternalSymbolSDNode">; 273def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 274 "BlockAddressSDNode">; 275def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 276 "BlockAddressSDNode">; 277 278def add : SDNode<"ISD::ADD" , SDTIntBinOp , 279 [SDNPCommutative, SDNPAssociative]>; 280def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 281def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 282 [SDNPCommutative, SDNPAssociative]>; 283def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 284def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 285def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 286def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 287def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 288def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 289def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 290def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 291def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 292def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 293def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 294def and : SDNode<"ISD::AND" , SDTIntBinOp, 295 [SDNPCommutative, SDNPAssociative]>; 296def or : SDNode<"ISD::OR" , SDTIntBinOp, 297 [SDNPCommutative, SDNPAssociative]>; 298def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 299 [SDNPCommutative, SDNPAssociative]>; 300def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 301 [SDNPCommutative, SDNPOutFlag]>; 302def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 303 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>; 304def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 305 [SDNPOutFlag]>; 306def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 307 [SDNPOutFlag, SDNPInFlag]>; 308 309def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 310def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 311def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 312def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 313def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 314def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 315def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 316def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 317def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 318def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>; 319def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 320def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 321 322 323def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 324def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 325def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 326def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 327def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 328def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 329def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 330def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 331def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 332def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 333def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 334def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 335def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 336def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 337def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 338def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 339def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 340 341def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 342def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 343def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 344 345def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 346def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 347def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 348def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 349def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>; 350def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>; 351 352def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 353def select : SDNode<"ISD::SELECT" , SDTSelect>; 354def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 355def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>; 356 357def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 358def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 359def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 360def trap : SDNode<"ISD::TRAP" , SDTNone, 361 [SDNPHasChain, SDNPSideEffect]>; 362 363def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch, 364 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; 365 366def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier, 367 [SDNPHasChain, SDNPSideEffect]>; 368 369def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3, 370 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 371def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2, 372 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 373def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2, 374 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 375def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2, 376 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 377def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2, 378 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 379def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2, 380 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 381def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2, 382 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 383def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2, 384 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 385def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2, 386 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 387def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2, 388 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 389def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2, 390 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 391def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2, 392 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 393 394// Do not use ld, st directly. Use load, extload, sextload, zextload, store, 395// and truncst (see below). 396def ld : SDNode<"ISD::LOAD" , SDTLoad, 397 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 398def st : SDNode<"ISD::STORE" , SDTStore, 399 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 400def ist : SDNode<"ISD::STORE" , SDTIStore, 401 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 402 403def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 404def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 405def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 406 []>; 407def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 408 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 409def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 410 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 411 412// Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 413// these internally. Don't reference these directly. 414def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 415 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 416 [SDNPHasChain]>; 417def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 418 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 419 [SDNPHasChain]>; 420def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 421 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 422 423// Do not use cvt directly. Use cvt forms below 424def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 425 426//===----------------------------------------------------------------------===// 427// Selection DAG Condition Codes 428 429class CondCode; // ISD::CondCode enums 430def SETOEQ : CondCode; def SETOGT : CondCode; 431def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 432def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 433def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 434def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 435 436def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 437def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 438 439 440//===----------------------------------------------------------------------===// 441// Selection DAG Node Transformation Functions. 442// 443// This mechanism allows targets to manipulate nodes in the output DAG once a 444// match has been formed. This is typically used to manipulate immediate 445// values. 446// 447class SDNodeXForm<SDNode opc, code xformFunction> { 448 SDNode Opcode = opc; 449 code XFormFunction = xformFunction; 450} 451 452def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 453 454 455//===----------------------------------------------------------------------===// 456// Selection DAG Pattern Fragments. 457// 458// Pattern fragments are reusable chunks of dags that match specific things. 459// They can take arguments and have C++ predicates that control whether they 460// match. They are intended to make the patterns for common instructions more 461// compact and readable. 462// 463 464/// PatFrag - Represents a pattern fragment. This can match something on the 465/// DAG, frame a single node to multiply nested other fragments. 466/// 467class PatFrag<dag ops, dag frag, code pred = [{}], 468 SDNodeXForm xform = NOOP_SDNodeXForm> { 469 dag Operands = ops; 470 dag Fragment = frag; 471 code Predicate = pred; 472 SDNodeXForm OperandTransform = xform; 473} 474 475// PatLeaf's are pattern fragments that have no operands. This is just a helper 476// to define immediates and other common things concisely. 477class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 478 : PatFrag<(ops), frag, pred, xform>; 479 480// Leaf fragments. 481 482def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 483def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 484 485def immAllOnesV: PatLeaf<(build_vector), [{ 486 return ISD::isBuildVectorAllOnes(N); 487}]>; 488def immAllOnesV_bc: PatLeaf<(bitconvert), [{ 489 return ISD::isBuildVectorAllOnes(N); 490}]>; 491def immAllZerosV: PatLeaf<(build_vector), [{ 492 return ISD::isBuildVectorAllZeros(N); 493}]>; 494def immAllZerosV_bc: PatLeaf<(bitconvert), [{ 495 return ISD::isBuildVectorAllZeros(N); 496}]>; 497 498 499 500// Other helper fragments. 501def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 502def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 503def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>; 504def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 505 506// load fragments. 507def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 508 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 509}]>; 510def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 511 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 512}]>; 513 514// extending load fragments. 515def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 516 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 517}]>; 518def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 519 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 520}]>; 521def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 522 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 523}]>; 524 525def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 526 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 527}]>; 528def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 529 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 530}]>; 531def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 532 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 533}]>; 534def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 535 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 536}]>; 537def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 538 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 539}]>; 540def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 541 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 542}]>; 543 544def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 545 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 546}]>; 547def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 548 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 549}]>; 550def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 551 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 552}]>; 553def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 554 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 555}]>; 556 557def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 558 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 559}]>; 560def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 561 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 562}]>; 563def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 564 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 565}]>; 566def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 567 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 568}]>; 569 570// store fragments. 571def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 572 (st node:$val, node:$ptr), [{ 573 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 574}]>; 575def store : PatFrag<(ops node:$val, node:$ptr), 576 (unindexedstore node:$val, node:$ptr), [{ 577 return !cast<StoreSDNode>(N)->isTruncatingStore(); 578}]>; 579 580// truncstore fragments. 581def truncstore : PatFrag<(ops node:$val, node:$ptr), 582 (unindexedstore node:$val, node:$ptr), [{ 583 return cast<StoreSDNode>(N)->isTruncatingStore(); 584}]>; 585def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 586 (truncstore node:$val, node:$ptr), [{ 587 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 588}]>; 589def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 590 (truncstore node:$val, node:$ptr), [{ 591 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 592}]>; 593def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 594 (truncstore node:$val, node:$ptr), [{ 595 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 596}]>; 597def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 598 (truncstore node:$val, node:$ptr), [{ 599 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 600}]>; 601def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 602 (truncstore node:$val, node:$ptr), [{ 603 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 604}]>; 605 606// indexed store fragments. 607def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 608 (ist node:$val, node:$base, node:$offset), [{ 609 return !cast<StoreSDNode>(N)->isTruncatingStore(); 610}]>; 611 612def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 613 (istore node:$val, node:$base, node:$offset), [{ 614 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 615 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 616}]>; 617 618def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 619 (ist node:$val, node:$base, node:$offset), [{ 620 return cast<StoreSDNode>(N)->isTruncatingStore(); 621}]>; 622def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 623 (itruncstore node:$val, node:$base, node:$offset), [{ 624 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 625 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 626}]>; 627def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 628 (pre_truncst node:$val, node:$base, node:$offset), [{ 629 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 630}]>; 631def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 632 (pre_truncst node:$val, node:$base, node:$offset), [{ 633 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 634}]>; 635def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 636 (pre_truncst node:$val, node:$base, node:$offset), [{ 637 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 638}]>; 639def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 640 (pre_truncst node:$val, node:$base, node:$offset), [{ 641 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 642}]>; 643def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 644 (pre_truncst node:$val, node:$base, node:$offset), [{ 645 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 646}]>; 647 648def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 649 (istore node:$val, node:$ptr, node:$offset), [{ 650 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 651 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 652}]>; 653 654def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 655 (itruncstore node:$val, node:$base, node:$offset), [{ 656 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 657 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 658}]>; 659def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 660 (post_truncst node:$val, node:$base, node:$offset), [{ 661 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 662}]>; 663def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 664 (post_truncst node:$val, node:$base, node:$offset), [{ 665 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 666}]>; 667def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 668 (post_truncst node:$val, node:$base, node:$offset), [{ 669 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 670}]>; 671def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 672 (post_truncst node:$val, node:$base, node:$offset), [{ 673 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 674}]>; 675def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 676 (post_truncst node:$val, node:$base, node:$offset), [{ 677 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 678}]>; 679 680// setcc convenience fragments. 681def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 682 (setcc node:$lhs, node:$rhs, SETOEQ)>; 683def setogt : PatFrag<(ops node:$lhs, node:$rhs), 684 (setcc node:$lhs, node:$rhs, SETOGT)>; 685def setoge : PatFrag<(ops node:$lhs, node:$rhs), 686 (setcc node:$lhs, node:$rhs, SETOGE)>; 687def setolt : PatFrag<(ops node:$lhs, node:$rhs), 688 (setcc node:$lhs, node:$rhs, SETOLT)>; 689def setole : PatFrag<(ops node:$lhs, node:$rhs), 690 (setcc node:$lhs, node:$rhs, SETOLE)>; 691def setone : PatFrag<(ops node:$lhs, node:$rhs), 692 (setcc node:$lhs, node:$rhs, SETONE)>; 693def seto : PatFrag<(ops node:$lhs, node:$rhs), 694 (setcc node:$lhs, node:$rhs, SETO)>; 695def setuo : PatFrag<(ops node:$lhs, node:$rhs), 696 (setcc node:$lhs, node:$rhs, SETUO)>; 697def setueq : PatFrag<(ops node:$lhs, node:$rhs), 698 (setcc node:$lhs, node:$rhs, SETUEQ)>; 699def setugt : PatFrag<(ops node:$lhs, node:$rhs), 700 (setcc node:$lhs, node:$rhs, SETUGT)>; 701def setuge : PatFrag<(ops node:$lhs, node:$rhs), 702 (setcc node:$lhs, node:$rhs, SETUGE)>; 703def setult : PatFrag<(ops node:$lhs, node:$rhs), 704 (setcc node:$lhs, node:$rhs, SETULT)>; 705def setule : PatFrag<(ops node:$lhs, node:$rhs), 706 (setcc node:$lhs, node:$rhs, SETULE)>; 707def setune : PatFrag<(ops node:$lhs, node:$rhs), 708 (setcc node:$lhs, node:$rhs, SETUNE)>; 709def seteq : PatFrag<(ops node:$lhs, node:$rhs), 710 (setcc node:$lhs, node:$rhs, SETEQ)>; 711def setgt : PatFrag<(ops node:$lhs, node:$rhs), 712 (setcc node:$lhs, node:$rhs, SETGT)>; 713def setge : PatFrag<(ops node:$lhs, node:$rhs), 714 (setcc node:$lhs, node:$rhs, SETGE)>; 715def setlt : PatFrag<(ops node:$lhs, node:$rhs), 716 (setcc node:$lhs, node:$rhs, SETLT)>; 717def setle : PatFrag<(ops node:$lhs, node:$rhs), 718 (setcc node:$lhs, node:$rhs, SETLE)>; 719def setne : PatFrag<(ops node:$lhs, node:$rhs), 720 (setcc node:$lhs, node:$rhs, SETNE)>; 721 722def atomic_cmp_swap_8 : 723 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 724 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 725 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 726}]>; 727def atomic_cmp_swap_16 : 728 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 729 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 730 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 731}]>; 732def atomic_cmp_swap_32 : 733 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 734 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 735 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 736}]>; 737def atomic_cmp_swap_64 : 738 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 739 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 740 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 741}]>; 742 743multiclass binary_atomic_op<SDNode atomic_op> { 744 def _8 : PatFrag<(ops node:$ptr, node:$val), 745 (atomic_op node:$ptr, node:$val), [{ 746 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 747 }]>; 748 def _16 : PatFrag<(ops node:$ptr, node:$val), 749 (atomic_op node:$ptr, node:$val), [{ 750 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 751 }]>; 752 def _32 : PatFrag<(ops node:$ptr, node:$val), 753 (atomic_op node:$ptr, node:$val), [{ 754 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 755 }]>; 756 def _64 : PatFrag<(ops node:$ptr, node:$val), 757 (atomic_op node:$ptr, node:$val), [{ 758 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 759 }]>; 760} 761 762defm atomic_load_add : binary_atomic_op<atomic_load_add>; 763defm atomic_swap : binary_atomic_op<atomic_swap>; 764defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 765defm atomic_load_and : binary_atomic_op<atomic_load_and>; 766defm atomic_load_or : binary_atomic_op<atomic_load_or>; 767defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 768defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 769defm atomic_load_min : binary_atomic_op<atomic_load_min>; 770defm atomic_load_max : binary_atomic_op<atomic_load_max>; 771defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 772defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 773 774//===----------------------------------------------------------------------===// 775// Selection DAG CONVERT_RNDSAT patterns 776 777def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 778 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 779 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 780 }]>; 781 782def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 783 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 784 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 785 }]>; 786 787def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 788 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 789 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 790 }]>; 791 792def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 793 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 794 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 795 }]>; 796 797def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 798 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 799 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 800 }]>; 801 802def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 803 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 804 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 805 }]>; 806 807def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 808 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 809 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 810 }]>; 811 812def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 813 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 814 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 815 }]>; 816 817def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 818 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 819 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 820 }]>; 821 822//===----------------------------------------------------------------------===// 823// Selection DAG Pattern Support. 824// 825// Patterns are what are actually matched against the target-flavored 826// instruction selection DAG. Instructions defined by the target implicitly 827// define patterns in most cases, but patterns can also be explicitly added when 828// an operation is defined by a sequence of instructions (e.g. loading a large 829// immediate value on RISC targets that do not support immediates as large as 830// their GPRs). 831// 832 833class Pattern<dag patternToMatch, list<dag> resultInstrs> { 834 dag PatternToMatch = patternToMatch; 835 list<dag> ResultInstrs = resultInstrs; 836 list<Predicate> Predicates = []; // See class Instruction in Target.td. 837 int AddedComplexity = 0; // See class Instruction in Target.td. 838} 839 840// Pat - A simple (but common) form of a pattern, which produces a simple result 841// not needing a full list. 842class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 843 844//===----------------------------------------------------------------------===// 845// Complex pattern definitions. 846// 847 848// Complex patterns, e.g. X86 addressing mode, requires pattern matching code 849// in C++. NumOperands is the number of operands returned by the select function; 850// SelectFunc is the name of the function used to pattern match the max. pattern; 851// RootNodes are the list of possible root nodes of the sub-dags to match. 852// e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 853// 854class ComplexPattern<ValueType ty, int numops, string fn, 855 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 856 ValueType Ty = ty; 857 int NumOperands = numops; 858 string SelectFunc = fn; 859 list<SDNode> RootNodes = roots; 860 list<SDNodeProperty> Properties = props; 861} 862