1//=- llvm/CodeGen/CriticalAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the CriticalAntiDepBreaker class, which
11// implements register anti-dependence breaking along a blocks
12// critical path during post-RA scheduler.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
17#define LLVM_LIB_CODEGEN_CRITICALANTIDEPBREAKER_H
18
19#include "AntiDepBreaker.h"
20#include "llvm/ADT/BitVector.h"
21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/RegisterClassInfo.h"
24#include "llvm/CodeGen/ScheduleDAG.h"
25
26namespace llvm {
27class RegisterClassInfo;
28class TargetInstrInfo;
29class TargetRegisterInfo;
30class MachineFunction;
31
32class LLVM_LIBRARY_VISIBILITY CriticalAntiDepBreaker : public AntiDepBreaker {
33    MachineFunction& MF;
34    MachineRegisterInfo &MRI;
35    const TargetInstrInfo *TII;
36    const TargetRegisterInfo *TRI;
37    const RegisterClassInfo &RegClassInfo;
38
39    /// The set of allocatable registers.
40    /// We'll be ignoring anti-dependencies on non-allocatable registers,
41    /// because they may not be safe to break.
42    const BitVector AllocatableSet;
43
44    /// For live regs that are only used in one register class in a
45    /// live range, the register class. If the register is not live, the
46    /// corresponding value is null. If the register is live but used in
47    /// multiple register classes, the corresponding value is -1 casted to a
48    /// pointer.
49    std::vector<const TargetRegisterClass*> Classes;
50
51    /// Map registers to all their references within a live range.
52    std::multimap<unsigned, MachineOperand *> RegRefs;
53    typedef std::multimap<unsigned, MachineOperand *>::const_iterator
54      RegRefIter;
55
56    /// The index of the most recent kill (proceeding bottom-up),
57    /// or ~0u if the register is not live.
58    std::vector<unsigned> KillIndices;
59
60    /// The index of the most recent complete def (proceeding
61    /// bottom up), or ~0u if the register is live.
62    std::vector<unsigned> DefIndices;
63
64    /// A set of registers which are live and cannot be changed to
65    /// break anti-dependencies.
66    BitVector KeepRegs;
67
68  public:
69    CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo&);
70    ~CriticalAntiDepBreaker() override;
71
72    /// Initialize anti-dep breaking for a new basic block.
73    void StartBlock(MachineBasicBlock *BB) override;
74
75    /// Identifiy anti-dependencies along the critical path
76    /// of the ScheduleDAG and break them by renaming registers.
77    unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
78                                   MachineBasicBlock::iterator Begin,
79                                   MachineBasicBlock::iterator End,
80                                   unsigned InsertPosIndex,
81                                   DbgValueVector &DbgValues) override;
82
83    /// Update liveness information to account for the current
84    /// instruction, which will not be scheduled.
85    void Observe(MachineInstr &MI, unsigned Count,
86                 unsigned InsertPosIndex) override;
87
88    /// Finish anti-dep breaking for a basic block.
89    void FinishBlock() override;
90
91  private:
92    void PrescanInstruction(MachineInstr &MI);
93    void ScanInstruction(MachineInstr &MI, unsigned Count);
94    bool isNewRegClobberedByRefs(RegRefIter RegRefBegin,
95                                 RegRefIter RegRefEnd,
96                                 unsigned NewReg);
97    unsigned findSuitableFreeRegister(RegRefIter RegRefBegin,
98                                      RegRefIter RegRefEnd,
99                                      unsigned AntiDepReg,
100                                      unsigned LastNewReg,
101                                      const TargetRegisterClass *RC,
102                                      SmallVectorImpl<unsigned> &Forbid);
103  };
104}
105
106#endif
107