1//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief This file provides AMDGPU specific target descriptions.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AMDGPUMCTargetDesc.h"
16#include "AMDGPUELFStreamer.h"
17#include "AMDGPUMCAsmInfo.h"
18#include "AMDGPUTargetStreamer.h"
19#include "InstPrinter/AMDGPUInstPrinter.h"
20#include "SIDefines.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCInstrInfo.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/MC/MCStreamer.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/MC/MachineLocation.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/TargetRegistry.h"
29
30using namespace llvm;
31
32#define GET_INSTRINFO_MC_DESC
33#include "AMDGPUGenInstrInfo.inc"
34
35#define GET_SUBTARGETINFO_MC_DESC
36#include "AMDGPUGenSubtargetInfo.inc"
37
38#define GET_REGINFO_MC_DESC
39#include "AMDGPUGenRegisterInfo.inc"
40
41static MCInstrInfo *createAMDGPUMCInstrInfo() {
42  MCInstrInfo *X = new MCInstrInfo();
43  InitAMDGPUMCInstrInfo(X);
44  return X;
45}
46
47static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
48  MCRegisterInfo *X = new MCRegisterInfo();
49  InitAMDGPUMCRegisterInfo(X, 0);
50  return X;
51}
52
53static MCSubtargetInfo *
54createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
55  return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
56}
57
58static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
59                                                unsigned SyntaxVariant,
60                                                const MCAsmInfo &MAI,
61                                                const MCInstrInfo &MII,
62                                                const MCRegisterInfo &MRI) {
63  return new AMDGPUInstPrinter(MAI, MII, MRI);
64}
65
66static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
67                                                      formatted_raw_ostream &OS,
68                                                      MCInstPrinter *InstPrint,
69                                                      bool isVerboseAsm) {
70  return new AMDGPUTargetAsmStreamer(S, OS);
71}
72
73static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
74                                                   MCStreamer &S,
75                                                   const MCSubtargetInfo &STI) {
76  return new AMDGPUTargetELFStreamer(S);
77}
78
79static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
80                                    MCAsmBackend &MAB, raw_pwrite_stream &OS,
81                                    MCCodeEmitter *Emitter, bool RelaxAll) {
82  if (T.getOS() == Triple::AMDHSA)
83    return createAMDGPUELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
84
85  return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
86}
87
88extern "C" void LLVMInitializeAMDGPUTargetMC() {
89  for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) {
90    RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
91
92    TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
93    TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
94    TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
95    TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
96    TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
97    TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
98  }
99
100  // R600 specific registration
101  TargetRegistry::RegisterMCCodeEmitter(TheAMDGPUTarget,
102                                        createR600MCCodeEmitter);
103
104  // GCN specific registration
105  TargetRegistry::RegisterMCCodeEmitter(TheGCNTarget, createSIMCCodeEmitter);
106
107  TargetRegistry::RegisterAsmTargetStreamer(TheGCNTarget,
108                                            createAMDGPUAsmTargetStreamer);
109  TargetRegistry::RegisterObjectTargetStreamer(TheGCNTarget,
110                                              createAMDGPUObjectTargetStreamer);
111}
112