1//===- R600MCCodeEmitter.cpp - Code Emitter for R600->Cayman GPU families -===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11///
12/// \brief The R600 code emitter produces machine code that can be executed
13/// directly on the GPU device.
14//
15//===----------------------------------------------------------------------===//
16
17#include "R600Defines.h"
18#include "MCTargetDesc/AMDGPUFixupKinds.h"
19#include "MCTargetDesc/AMDGPUMCCodeEmitter.h"
20#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
21#include "llvm/MC/MCCodeEmitter.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCInst.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCRegisterInfo.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/Support/EndianStream.h"
28#include "llvm/Support/raw_ostream.h"
29
30using namespace llvm;
31
32namespace {
33
34class R600MCCodeEmitter : public AMDGPUMCCodeEmitter {
35  R600MCCodeEmitter(const R600MCCodeEmitter &) = delete;
36  void operator=(const R600MCCodeEmitter &) = delete;
37  const MCInstrInfo &MCII;
38  const MCRegisterInfo &MRI;
39
40public:
41  R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
42    : MCII(mcii), MRI(mri) { }
43
44  /// \brief Encode the instruction and write it to the OS.
45  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
46                         SmallVectorImpl<MCFixup> &Fixups,
47                         const MCSubtargetInfo &STI) const override;
48
49  /// \returns the encoding for an MCOperand.
50  uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
51                             SmallVectorImpl<MCFixup> &Fixups,
52                             const MCSubtargetInfo &STI) const override;
53
54private:
55  void Emit(uint32_t value, raw_ostream &OS) const;
56  void Emit(uint64_t value, raw_ostream &OS) const;
57
58  unsigned getHWReg(unsigned regNo) const;
59};
60
61} // End anonymous namespace
62
63enum RegElement {
64  ELEMENT_X = 0,
65  ELEMENT_Y,
66  ELEMENT_Z,
67  ELEMENT_W
68};
69
70enum FCInstr {
71  FC_IF_PREDICATE = 0,
72  FC_ELSE,
73  FC_ENDIF,
74  FC_BGNLOOP,
75  FC_ENDLOOP,
76  FC_BREAK_PREDICATE,
77  FC_CONTINUE
78};
79
80MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
81                                             const MCRegisterInfo &MRI,
82                                             MCContext &Ctx) {
83  return new R600MCCodeEmitter(MCII, MRI);
84}
85
86void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
87                                       SmallVectorImpl<MCFixup> &Fixups,
88                                       const MCSubtargetInfo &STI) const {
89  const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
90  if (MI.getOpcode() == AMDGPU::RETURN ||
91    MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||
92    MI.getOpcode() == AMDGPU::ALU_CLAUSE ||
93    MI.getOpcode() == AMDGPU::BUNDLE ||
94    MI.getOpcode() == AMDGPU::KILL) {
95    return;
96  } else if (IS_VTX(Desc)) {
97    uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI);
98    uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset
99    if (!(STI.getFeatureBits()[AMDGPU::FeatureCaymanISA])) {
100      InstWord2 |= 1 << 19; // Mega-Fetch bit
101    }
102
103    Emit(InstWord01, OS);
104    Emit(InstWord2, OS);
105    Emit((uint32_t) 0, OS);
106  } else if (IS_TEX(Desc)) {
107      int64_t Sampler = MI.getOperand(14).getImm();
108
109      int64_t SrcSelect[4] = {
110        MI.getOperand(2).getImm(),
111        MI.getOperand(3).getImm(),
112        MI.getOperand(4).getImm(),
113        MI.getOperand(5).getImm()
114      };
115      int64_t Offsets[3] = {
116        MI.getOperand(6).getImm() & 0x1F,
117        MI.getOperand(7).getImm() & 0x1F,
118        MI.getOperand(8).getImm() & 0x1F
119      };
120
121      uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI);
122      uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 |
123          SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 |
124          SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 |
125          Offsets[2] << 10;
126
127      Emit(Word01, OS);
128      Emit(Word2, OS);
129      Emit((uint32_t) 0, OS);
130  } else {
131    uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI);
132    if ((STI.getFeatureBits()[AMDGPU::FeatureR600ALUInst]) &&
133       ((Desc.TSFlags & R600_InstFlag::OP1) ||
134         Desc.TSFlags & R600_InstFlag::OP2)) {
135      uint64_t ISAOpCode = Inst & (0x3FFULL << 39);
136      Inst &= ~(0x3FFULL << 39);
137      Inst |= ISAOpCode << 1;
138    }
139    Emit(Inst, OS);
140  }
141}
142
143void R600MCCodeEmitter::Emit(uint32_t Value, raw_ostream &OS) const {
144  support::endian::Writer<support::little>(OS).write(Value);
145}
146
147void R600MCCodeEmitter::Emit(uint64_t Value, raw_ostream &OS) const {
148  support::endian::Writer<support::little>(OS).write(Value);
149}
150
151unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const {
152  return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
153}
154
155uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
156                                              const MCOperand &MO,
157                                        SmallVectorImpl<MCFixup> &Fixups,
158                                        const MCSubtargetInfo &STI) const {
159  if (MO.isReg()) {
160    if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
161      return MRI.getEncodingValue(MO.getReg());
162    return getHWReg(MO.getReg());
163  }
164
165  if (MO.isExpr()) {
166    // We put rodata at the end of code section, then map the entire
167    // code secetion as vtx buf. Thus the section relative address is the
168    // correct one.
169    // Each R600 literal instruction has two operands
170    // We can't easily get the order of the current one, so compare against
171    // the first one and adjust offset.
172    const unsigned offset = (&MO == &MI.getOperand(0)) ? 0 : 4;
173    Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc()));
174    return 0;
175  }
176
177  assert(MO.isImm());
178  return MO.getImm();
179}
180
181#include "AMDGPUGenMCCodeEmitter.inc"
182