1//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides ARM specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
15#define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMMCTARGETDESC_H
16
17#include "llvm/Support/DataTypes.h"
18#include <string>
19
20namespace llvm {
21class formatted_raw_ostream;
22class MCAsmBackend;
23class MCCodeEmitter;
24class MCContext;
25class MCInstrInfo;
26class MCInstPrinter;
27class MCObjectWriter;
28class MCRegisterInfo;
29class MCSubtargetInfo;
30class MCStreamer;
31class MCRelocationInfo;
32class MCTargetStreamer;
33class StringRef;
34class Target;
35class Triple;
36class raw_ostream;
37class raw_pwrite_stream;
38
39extern Target TheARMLETarget, TheThumbLETarget;
40extern Target TheARMBETarget, TheThumbBETarget;
41
42namespace ARM_MC {
43std::string ParseARMTriple(const Triple &TT, StringRef CPU);
44
45/// Create a ARM MCSubtargetInfo instance. This is exposed so Asm parser, etc.
46/// do not need to go through TargetRegistry.
47MCSubtargetInfo *createARMMCSubtargetInfo(const Triple &TT, StringRef CPU,
48                                          StringRef FS);
49}
50
51MCTargetStreamer *createARMNullTargetStreamer(MCStreamer &S);
52MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S,
53                                             formatted_raw_ostream &OS,
54                                             MCInstPrinter *InstPrint,
55                                             bool isVerboseAsm);
56MCTargetStreamer *createARMObjectTargetStreamer(MCStreamer &S,
57                                                const MCSubtargetInfo &STI);
58
59MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
60                                        const MCRegisterInfo &MRI,
61                                        MCContext &Ctx);
62
63MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
64                                        const MCRegisterInfo &MRI,
65                                        MCContext &Ctx);
66
67MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
68                                  const Triple &TT, StringRef CPU,
69                                  bool IsLittleEndian);
70
71MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
72                                    const Triple &TT, StringRef CPU);
73
74MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
75                                    const Triple &TT, StringRef CPU);
76
77MCAsmBackend *createThumbLEAsmBackend(const Target &T,
78                                      const MCRegisterInfo &MRI,
79                                      const Triple &TT, StringRef CPU);
80
81MCAsmBackend *createThumbBEAsmBackend(const Target &T,
82                                      const MCRegisterInfo &MRI,
83                                      const Triple &TT, StringRef CPU);
84
85// Construct a PE/COFF machine code streamer which will generate a PE/COFF
86// object file.
87MCStreamer *createARMWinCOFFStreamer(MCContext &Context, MCAsmBackend &MAB,
88                                     raw_pwrite_stream &OS,
89                                     MCCodeEmitter *Emitter, bool RelaxAll,
90                                     bool IncrementalLinkerCompatible);
91
92/// Construct an ELF Mach-O object writer.
93MCObjectWriter *createARMELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
94                                         bool IsLittleEndian);
95
96/// Construct an ARM Mach-O object writer.
97MCObjectWriter *createARMMachObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
98                                          uint32_t CPUType,
99                                          uint32_t CPUSubtype);
100
101/// Construct an ARM PE/COFF object writer.
102MCObjectWriter *createARMWinCOFFObjectWriter(raw_pwrite_stream &OS,
103                                             bool Is64Bit);
104
105/// Construct ARM Mach-O relocation info.
106MCRelocationInfo *createARMMachORelocationInfo(MCContext &Ctx);
107} // End llvm namespace
108
109// Defines symbolic names for ARM registers.  This defines a mapping from
110// register name to register number.
111//
112#define GET_REGINFO_ENUM
113#include "ARMGenRegisterInfo.inc"
114
115// Defines symbolic names for the ARM instructions.
116//
117#define GET_INSTRINFO_ENUM
118#include "ARMGenInstrInfo.inc"
119
120#define GET_SUBTARGETINFO_ENUM
121#include "ARMGenSubtargetInfo.inc"
122
123#endif
124