1//===-- LanaiTargetMachine.cpp - Define TargetMachine for Lanai ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Implements the info about Lanai target spec. 11// 12//===----------------------------------------------------------------------===// 13 14#include "LanaiTargetMachine.h" 15 16#include "Lanai.h" 17#include "LanaiTargetObjectFile.h" 18#include "LanaiTargetTransformInfo.h" 19#include "llvm/Analysis/TargetTransformInfo.h" 20#include "llvm/CodeGen/Passes.h" 21#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 22#include "llvm/CodeGen/TargetPassConfig.h" 23#include "llvm/Support/FormattedStream.h" 24#include "llvm/Support/TargetRegistry.h" 25#include "llvm/Target/TargetOptions.h" 26 27using namespace llvm; 28 29namespace llvm { 30void initializeLanaiMemAluCombinerPass(PassRegistry &); 31} // namespace llvm 32 33extern "C" void LLVMInitializeLanaiTarget() { 34 // Register the target. 35 RegisterTargetMachine<LanaiTargetMachine> registered_target(TheLanaiTarget); 36} 37 38static std::string computeDataLayout(const Triple &TT) { 39 // Data layout (keep in sync with clang/lib/Basic/Targets.cpp) 40 return "E" // Big endian 41 "-m:e" // ELF name manging 42 "-p:32:32" // 32-bit pointers, 32 bit aligned 43 "-i64:64" // 64 bit integers, 64 bit aligned 44 "-a:0:32" // 32 bit alignment of objects of aggregate type 45 "-n32" // 32 bit native integer width 46 "-S64"; // 64 bit natural stack alignment 47} 48 49static Reloc::Model getEffectiveRelocModel(const Triple &TT, 50 Optional<Reloc::Model> RM) { 51 if (!RM.hasValue()) 52 return Reloc::PIC_; 53 return *RM; 54} 55 56LanaiTargetMachine::LanaiTargetMachine(const Target &T, const Triple &TT, 57 StringRef Cpu, StringRef FeatureString, 58 const TargetOptions &Options, 59 Optional<Reloc::Model> RM, 60 CodeModel::Model CodeModel, 61 CodeGenOpt::Level OptLevel) 62 : LLVMTargetMachine(T, computeDataLayout(TargetTriple), TT, Cpu, 63 FeatureString, Options, getEffectiveRelocModel(TT, RM), 64 CodeModel, OptLevel), 65 Subtarget(TT, Cpu, FeatureString, *this, Options, CodeModel, OptLevel), 66 TLOF(new LanaiTargetObjectFile()) { 67 initAsmInfo(); 68} 69 70TargetIRAnalysis LanaiTargetMachine::getTargetIRAnalysis() { 71 return TargetIRAnalysis([this](const Function &F) { 72 return TargetTransformInfo(LanaiTTIImpl(this, F)); 73 }); 74} 75 76namespace { 77// Lanai Code Generator Pass Configuration Options. 78class LanaiPassConfig : public TargetPassConfig { 79public: 80 LanaiPassConfig(LanaiTargetMachine *TM, PassManagerBase *PassManager) 81 : TargetPassConfig(TM, *PassManager) {} 82 83 LanaiTargetMachine &getLanaiTargetMachine() const { 84 return getTM<LanaiTargetMachine>(); 85 } 86 87 bool addInstSelector() override; 88 void addPreSched2() override; 89 void addPreEmitPass() override; 90}; 91} // namespace 92 93TargetPassConfig * 94LanaiTargetMachine::createPassConfig(PassManagerBase &PassManager) { 95 return new LanaiPassConfig(this, &PassManager); 96} 97 98// Install an instruction selector pass. 99bool LanaiPassConfig::addInstSelector() { 100 addPass(createLanaiISelDag(getLanaiTargetMachine())); 101 return false; 102} 103 104// Implemented by targets that want to run passes immediately before 105// machine code is emitted. 106void LanaiPassConfig::addPreEmitPass() { 107 addPass(createLanaiDelaySlotFillerPass(getLanaiTargetMachine())); 108} 109 110// Run passes after prolog-epilog insertion and before the second instruction 111// scheduling pass. 112void LanaiPassConfig::addPreSched2() { 113 addPass(createLanaiMemAluCombinerPass()); 114} 115