1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that Mips uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 16#define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 17 18#include "MCTargetDesc/MipsABIInfo.h" 19#include "MCTargetDesc/MipsBaseInfo.h" 20#include "Mips.h" 21#include "llvm/CodeGen/CallingConvLower.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/IR/Function.h" 24#include "llvm/Target/TargetLowering.h" 25#include <deque> 26#include <string> 27 28namespace llvm { 29 namespace MipsISD { 30 enum NodeType : unsigned { 31 // Start the numbering from where ISD NodeType finishes. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 // Jump and link (call) 35 JmpLink, 36 37 // Tail call 38 TailCall, 39 40 // Get the Higher 16 bits from a 32-bit immediate 41 // No relation with Mips Hi register 42 Hi, 43 44 // Get the Lower 16 bits from a 32-bit immediate 45 // No relation with Mips Lo register 46 Lo, 47 48 // Handle gp_rel (small data/bss sections) relocation. 49 GPRel, 50 51 // Thread Pointer 52 ThreadPointer, 53 54 // Floating Point Branch Conditional 55 FPBrcond, 56 57 // Floating Point Compare 58 FPCmp, 59 60 // Floating Point Conditional Moves 61 CMovFP_T, 62 CMovFP_F, 63 64 // FP-to-int truncation node. 65 TruncIntFP, 66 67 // Return 68 Ret, 69 70 // Interrupt, exception, error trap Return 71 ERet, 72 73 // Software Exception Return. 74 EH_RETURN, 75 76 // Node used to extract integer from accumulator. 77 MFHI, 78 MFLO, 79 80 // Node used to insert integers to accumulator. 81 MTLOHI, 82 83 // Mult nodes. 84 Mult, 85 Multu, 86 87 // MAdd/Sub nodes 88 MAdd, 89 MAddu, 90 MSub, 91 MSubu, 92 93 // DivRem(u) 94 DivRem, 95 DivRemU, 96 DivRem16, 97 DivRemU16, 98 99 BuildPairF64, 100 ExtractElementF64, 101 102 Wrapper, 103 104 DynAlloc, 105 106 Sync, 107 108 Ext, 109 Ins, 110 111 // EXTR.W instrinsic nodes. 112 EXTP, 113 EXTPDP, 114 EXTR_S_H, 115 EXTR_W, 116 EXTR_R_W, 117 EXTR_RS_W, 118 SHILO, 119 MTHLIP, 120 121 // DPA.W intrinsic nodes. 122 MULSAQ_S_W_PH, 123 MAQ_S_W_PHL, 124 MAQ_S_W_PHR, 125 MAQ_SA_W_PHL, 126 MAQ_SA_W_PHR, 127 DPAU_H_QBL, 128 DPAU_H_QBR, 129 DPSU_H_QBL, 130 DPSU_H_QBR, 131 DPAQ_S_W_PH, 132 DPSQ_S_W_PH, 133 DPAQ_SA_L_W, 134 DPSQ_SA_L_W, 135 DPA_W_PH, 136 DPS_W_PH, 137 DPAQX_S_W_PH, 138 DPAQX_SA_W_PH, 139 DPAX_W_PH, 140 DPSX_W_PH, 141 DPSQX_S_W_PH, 142 DPSQX_SA_W_PH, 143 MULSA_W_PH, 144 145 MULT, 146 MULTU, 147 MADD_DSP, 148 MADDU_DSP, 149 MSUB_DSP, 150 MSUBU_DSP, 151 152 // DSP shift nodes. 153 SHLL_DSP, 154 SHRA_DSP, 155 SHRL_DSP, 156 157 // DSP setcc and select_cc nodes. 158 SETCC_DSP, 159 SELECT_CC_DSP, 160 161 // Vector comparisons. 162 // These take a vector and return a boolean. 163 VALL_ZERO, 164 VANY_ZERO, 165 VALL_NONZERO, 166 VANY_NONZERO, 167 168 // These take a vector and return a vector bitmask. 169 VCEQ, 170 VCLE_S, 171 VCLE_U, 172 VCLT_S, 173 VCLT_U, 174 175 // Element-wise vector max/min. 176 VSMAX, 177 VSMIN, 178 VUMAX, 179 VUMIN, 180 181 // Vector Shuffle with mask as an operand 182 VSHF, // Generic shuffle 183 SHF, // 4-element set shuffle. 184 ILVEV, // Interleave even elements 185 ILVOD, // Interleave odd elements 186 ILVL, // Interleave left elements 187 ILVR, // Interleave right elements 188 PCKEV, // Pack even elements 189 PCKOD, // Pack odd elements 190 191 // Vector Lane Copy 192 INSVE, // Copy element from one vector to another 193 194 // Combined (XOR (OR $a, $b), -1) 195 VNOR, 196 197 // Extended vector element extraction 198 VEXTRACT_SEXT_ELT, 199 VEXTRACT_ZEXT_ELT, 200 201 // Load/Store Left/Right nodes. 202 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 203 LWR, 204 SWL, 205 SWR, 206 LDL, 207 LDR, 208 SDL, 209 SDR 210 }; 211 } 212 213 //===--------------------------------------------------------------------===// 214 // TargetLowering Implementation 215 //===--------------------------------------------------------------------===// 216 class MipsFunctionInfo; 217 class MipsSubtarget; 218 class MipsCCState; 219 220 class MipsTargetLowering : public TargetLowering { 221 bool isMicroMips; 222 public: 223 explicit MipsTargetLowering(const MipsTargetMachine &TM, 224 const MipsSubtarget &STI); 225 226 static const MipsTargetLowering *create(const MipsTargetMachine &TM, 227 const MipsSubtarget &STI); 228 229 /// createFastISel - This method returns a target specific FastISel object, 230 /// or null if the target does not support "fast" ISel. 231 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 232 const TargetLibraryInfo *libInfo) const override; 233 234 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 235 return MVT::i32; 236 } 237 238 bool isCheapToSpeculateCttz() const override; 239 bool isCheapToSpeculateCtlz() const override; 240 241 ISD::NodeType getExtendForAtomicOps() const override { 242 return ISD::SIGN_EXTEND; 243 } 244 245 void LowerOperationWrapper(SDNode *N, 246 SmallVectorImpl<SDValue> &Results, 247 SelectionDAG &DAG) const override; 248 249 /// LowerOperation - Provide custom lowering hooks for some operations. 250 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 251 252 /// ReplaceNodeResults - Replace the results of node with an illegal result 253 /// type with new values built out of custom code. 254 /// 255 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 256 SelectionDAG &DAG) const override; 257 258 /// getTargetNodeName - This method returns the name of a target specific 259 // DAG node. 260 const char *getTargetNodeName(unsigned Opcode) const override; 261 262 /// getSetCCResultType - get the ISD::SETCC result ValueType 263 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 264 EVT VT) const override; 265 266 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 267 268 MachineBasicBlock * 269 EmitInstrWithCustomInserter(MachineInstr &MI, 270 MachineBasicBlock *MBB) const override; 271 272 void HandleByVal(CCState *, unsigned &, unsigned) const override; 273 274 unsigned getRegisterByName(const char* RegName, EVT VT, 275 SelectionDAG &DAG) const override; 276 277 /// If a physical register, this returns the register that receives the 278 /// exception address on entry to an EH pad. 279 unsigned 280 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 281 return ABI.IsN64() ? Mips::A0_64 : Mips::A0; 282 } 283 284 /// If a physical register, this returns the register that receives the 285 /// exception typeid on entry to a landing pad. 286 unsigned 287 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 288 return ABI.IsN64() ? Mips::A1_64 : Mips::A1; 289 } 290 291 /// Returns true if a cast between SrcAS and DestAS is a noop. 292 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 293 // Mips doesn't have any special address spaces so we just reserve 294 // the first 256 for software use (e.g. OpenCL) and treat casts 295 // between them as noops. 296 return SrcAS < 256 && DestAS < 256; 297 } 298 299 protected: 300 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 301 302 // This method creates the following nodes, which are necessary for 303 // computing a local symbol's address: 304 // 305 // (add (load (wrapper $gp, %got(sym)), %lo(sym)) 306 template <class NodeTy> 307 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, 308 bool IsN32OrN64) const { 309 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 310 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 311 getTargetNode(N, Ty, DAG, GOTFlag)); 312 SDValue Load = 313 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 314 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 315 false, false, false, 0); 316 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 317 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, 318 getTargetNode(N, Ty, DAG, LoFlag)); 319 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 320 } 321 322 // This method creates the following nodes, which are necessary for 323 // computing a global symbol's address: 324 // 325 // (load (wrapper $gp, %got(sym))) 326 template <class NodeTy> 327 SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, 328 unsigned Flag, SDValue Chain, 329 const MachinePointerInfo &PtrInfo) const { 330 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 331 getTargetNode(N, Ty, DAG, Flag)); 332 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0); 333 } 334 335 // This method creates the following nodes, which are necessary for 336 // computing a global symbol's address in large-GOT mode: 337 // 338 // (load (wrapper (add %hi(sym), $gp), %lo(sym))) 339 template <class NodeTy> 340 SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, 341 SelectionDAG &DAG, unsigned HiFlag, 342 unsigned LoFlag, SDValue Chain, 343 const MachinePointerInfo &PtrInfo) const { 344 SDValue Hi = 345 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag)); 346 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); 347 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 348 getTargetNode(N, Ty, DAG, LoFlag)); 349 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false, 350 0); 351 } 352 353 // This method creates the following nodes, which are necessary for 354 // computing a symbol's address in non-PIC mode: 355 // 356 // (add %hi(sym), %lo(sym)) 357 template <class NodeTy> 358 SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty, 359 SelectionDAG &DAG) const { 360 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); 361 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); 362 return DAG.getNode(ISD::ADD, DL, Ty, 363 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 364 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 365 } 366 367 // This method creates the following nodes, which are necessary for 368 // computing a symbol's address using gp-relative addressing: 369 // 370 // (add $gp, %gp_rel(sym)) 371 template <class NodeTy> 372 SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, 373 SelectionDAG &DAG) const { 374 assert(Ty == MVT::i32); 375 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL); 376 return DAG.getNode(ISD::ADD, DL, Ty, 377 DAG.getRegister(Mips::GP, Ty), 378 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), 379 GPRel)); 380 } 381 382 /// This function fills Ops, which is the list of operands that will later 383 /// be used when a function call node is created. It also generates 384 /// copyToReg nodes to set up argument registers. 385 virtual void 386 getOpndList(SmallVectorImpl<SDValue> &Ops, 387 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 388 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 389 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 390 SDValue Chain) const; 391 392 protected: 393 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 394 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 395 396 // Subtarget Info 397 const MipsSubtarget &Subtarget; 398 // Cache the ABI from the TargetMachine, we use it everywhere. 399 const MipsABIInfo &ABI; 400 401 private: 402 // Create a TargetGlobalAddress node. 403 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 404 unsigned Flag) const; 405 406 // Create a TargetExternalSymbol node. 407 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, 408 unsigned Flag) const; 409 410 // Create a TargetBlockAddress node. 411 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 412 unsigned Flag) const; 413 414 // Create a TargetJumpTable node. 415 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 416 unsigned Flag) const; 417 418 // Create a TargetConstantPool node. 419 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 420 unsigned Flag) const; 421 422 // Lower Operand helpers 423 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 424 CallingConv::ID CallConv, bool isVarArg, 425 const SmallVectorImpl<ISD::InputArg> &Ins, 426 const SDLoc &dl, SelectionDAG &DAG, 427 SmallVectorImpl<SDValue> &InVals, 428 TargetLowering::CallLoweringInfo &CLI) const; 429 430 // Lower Operand specifics 431 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 432 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 433 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 434 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 435 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 436 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 437 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 438 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 439 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 440 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 441 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const; 442 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 443 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 444 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 445 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 446 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 447 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 448 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 449 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 450 bool IsSRA) const; 451 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const; 452 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 453 454 /// isEligibleForTailCallOptimization - Check whether the call is eligible 455 /// for tail call optimization. 456 virtual bool 457 isEligibleForTailCallOptimization(const CCState &CCInfo, 458 unsigned NextStackOffset, 459 const MipsFunctionInfo &FI) const = 0; 460 461 /// copyByValArg - Copy argument registers which were used to pass a byval 462 /// argument to the stack. Create a stack frame object for the byval 463 /// argument. 464 void copyByValRegs(SDValue Chain, const SDLoc &DL, 465 std::vector<SDValue> &OutChains, SelectionDAG &DAG, 466 const ISD::ArgFlagsTy &Flags, 467 SmallVectorImpl<SDValue> &InVals, 468 const Argument *FuncArg, unsigned FirstReg, 469 unsigned LastReg, const CCValAssign &VA, 470 MipsCCState &State) const; 471 472 /// passByValArg - Pass a byval argument in registers or on stack. 473 void passByValArg(SDValue Chain, const SDLoc &DL, 474 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 475 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 476 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 477 unsigned FirstReg, unsigned LastReg, 478 const ISD::ArgFlagsTy &Flags, bool isLittle, 479 const CCValAssign &VA) const; 480 481 /// writeVarArgRegs - Write variable function arguments passed in registers 482 /// to the stack. Also create a stack frame object for the first variable 483 /// argument. 484 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain, 485 const SDLoc &DL, SelectionDAG &DAG, 486 CCState &State) const; 487 488 SDValue 489 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 490 const SmallVectorImpl<ISD::InputArg> &Ins, 491 const SDLoc &dl, SelectionDAG &DAG, 492 SmallVectorImpl<SDValue> &InVals) const override; 493 494 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 495 SDValue Arg, const SDLoc &DL, bool IsTailCall, 496 SelectionDAG &DAG) const; 497 498 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 499 SmallVectorImpl<SDValue> &InVals) const override; 500 501 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 502 bool isVarArg, 503 const SmallVectorImpl<ISD::OutputArg> &Outs, 504 LLVMContext &Context) const override; 505 506 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 507 const SmallVectorImpl<ISD::OutputArg> &Outs, 508 const SmallVectorImpl<SDValue> &OutVals, 509 const SDLoc &dl, SelectionDAG &DAG) const override; 510 511 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, 512 const SDLoc &DL, SelectionDAG &DAG) const; 513 514 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 515 516 // Inline asm support 517 ConstraintType getConstraintType(StringRef Constraint) const override; 518 519 /// Examine constraint string and operand type and determine a weight value. 520 /// The operand object must already have been set up with the operand type. 521 ConstraintWeight getSingleConstraintMatchWeight( 522 AsmOperandInfo &info, const char *constraint) const override; 523 524 /// This function parses registers that appear in inline-asm constraints. 525 /// It returns pair (0, 0) on failure. 526 std::pair<unsigned, const TargetRegisterClass *> 527 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const; 528 529 std::pair<unsigned, const TargetRegisterClass *> 530 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 531 StringRef Constraint, MVT VT) const override; 532 533 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 534 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 535 /// true it means one of the asm constraint of the inline asm instruction 536 /// being processed is 'm'. 537 void LowerAsmOperandForConstraint(SDValue Op, 538 std::string &Constraint, 539 std::vector<SDValue> &Ops, 540 SelectionDAG &DAG) const override; 541 542 unsigned 543 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 544 if (ConstraintCode == "R") 545 return InlineAsm::Constraint_R; 546 else if (ConstraintCode == "ZC") 547 return InlineAsm::Constraint_ZC; 548 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 549 } 550 551 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 552 Type *Ty, unsigned AS) const override; 553 554 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 555 556 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 557 unsigned SrcAlign, 558 bool IsMemset, bool ZeroMemset, 559 bool MemcpyStrSrc, 560 MachineFunction &MF) const override; 561 562 /// isFPImmLegal - Returns true if the target can instruction select the 563 /// specified FP immediate natively. If false, the legalizer will 564 /// materialize the FP immediate as a load from a constant pool. 565 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 566 567 unsigned getJumpTableEncoding() const override; 568 bool useSoftFloat() const override; 569 570 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 571 return true; 572 } 573 574 /// Emit a sign-extension using sll/sra, seb, or seh appropriately. 575 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI, 576 MachineBasicBlock *BB, 577 unsigned Size, unsigned DstReg, 578 unsigned SrcRec) const; 579 580 MachineBasicBlock *emitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB, 581 unsigned Size, unsigned BinOpcode, 582 bool Nand = false) const; 583 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI, 584 MachineBasicBlock *BB, 585 unsigned Size, 586 unsigned BinOpcode, 587 bool Nand = false) const; 588 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI, 589 MachineBasicBlock *BB, 590 unsigned Size) const; 591 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI, 592 MachineBasicBlock *BB, 593 unsigned Size) const; 594 MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const; 595 MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB, 596 bool isFPCmp, unsigned Opc) const; 597 }; 598 599 /// Create MipsTargetLowering objects. 600 const MipsTargetLowering * 601 createMips16TargetLowering(const MipsTargetMachine &TM, 602 const MipsSubtarget &STI); 603 const MipsTargetLowering * 604 createMipsSETargetLowering(const MipsTargetMachine &TM, 605 const MipsSubtarget &STI); 606 607 namespace Mips { 608 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 609 const TargetLibraryInfo *libInfo); 610 } 611} 612 613#endif 614