1//===-- MipsInstrFPU.td - Mips FPU Instruction Information -*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Mips FPU instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Floating Point Instructions
16// ------------------------
17// * 64bit fp:
18//    - 32 64-bit registers (default mode)
19//    - 16 even 32-bit registers (32-bit compatible mode) for
20//      single and double access.
21// * 32bit fp:
22//    - 16 even 32-bit registers - single and double (aliased)
23//    - 32 32-bit registers (within single-only mode)
24//===----------------------------------------------------------------------===//
25
26// Floating Point Compare and Branch
27def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>,
28                                            SDTCisVT<1, i32>,
29                                            SDTCisVT<2, OtherVT>]>;
30def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>,
31                                         SDTCisVT<2, i32>]>;
32def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>,
33                                          SDTCisSameAs<1, 3>]>;
34def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
35def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>,
36                                                SDTCisVT<1, i32>,
37                                                SDTCisSameAs<1, 2>]>;
38def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
39                                                     SDTCisVT<1, f64>,
40                                                     SDTCisVT<2, i32>]>;
41
42def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>;
43def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>;
44def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>;
45def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
46                          [SDNPHasChain, SDNPOptInGlue]>;
47def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>;
48def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>;
49def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64",
50                                   SDT_MipsExtractElementF64>;
51
52// Operand for printing out a condition code.
53let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in
54  def condcode : Operand<i32>;
55
56//===----------------------------------------------------------------------===//
57// Feature predicates.
58//===----------------------------------------------------------------------===//
59
60def IsFP64bit        : Predicate<"Subtarget->isFP64bit()">,
61                       AssemblerPredicate<"FeatureFP64Bit">;
62def NotFP64bit       : Predicate<"!Subtarget->isFP64bit()">,
63                       AssemblerPredicate<"!FeatureFP64Bit">;
64def IsSingleFloat    : Predicate<"Subtarget->isSingleFloat()">,
65                       AssemblerPredicate<"FeatureSingleFloat">;
66def IsNotSingleFloat : Predicate<"!Subtarget->isSingleFloat()">,
67                       AssemblerPredicate<"!FeatureSingleFloat">;
68def IsNotSoftFloat   : Predicate<"!Subtarget->useSoftFloat()">,
69                       AssemblerPredicate<"!FeatureSoftFloat">;
70
71//===----------------------------------------------------------------------===//
72// Mips FGR size adjectives.
73// They are mutually exclusive.
74//===----------------------------------------------------------------------===//
75
76class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; }
77class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; }
78class HARDFLOAT { list<Predicate> HardFloatPredicate = [IsNotSoftFloat]; }
79
80//===----------------------------------------------------------------------===//
81
82// FP immediate patterns.
83def fpimm0 : PatLeaf<(fpimm), [{
84  return N->isExactlyValue(+0.0);
85}]>;
86
87def fpimm0neg : PatLeaf<(fpimm), [{
88  return N->isExactlyValue(-0.0);
89}]>;
90
91//===----------------------------------------------------------------------===//
92// Instruction Class Templates
93//
94// A set of multiclasses is used to address the register usage.
95//
96// S32 - single precision in 16 32bit even fp registers
97//       single precision in 32 32bit fp registers in SingleOnly mode
98// S64 - single precision in 32 64bit fp registers (In64BitMode)
99// D32 - double precision in 16 32bit even fp registers
100// D64 - double precision in 32 64bit fp registers (In64BitMode)
101//
102// Only S32 and D32 are supported right now.
103//===----------------------------------------------------------------------===//
104class ADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin, bit IsComm,
105              SDPatternOperator OpNode= null_frag> :
106  InstSE<(outs RC:$fd), (ins RC:$fs, RC:$ft),
107         !strconcat(opstr, "\t$fd, $fs, $ft"),
108         [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
109  HARDFLOAT {
110  let isCommutable = IsComm;
111}
112
113multiclass ADDS_M<string opstr, InstrItinClass Itin, bit IsComm,
114                  SDPatternOperator OpNode = null_frag> {
115  def _D32 : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>, FGR_32;
116  def _D64 : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
117    string DecoderNamespace = "Mips64";
118  }
119}
120
121class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
122              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
123  InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124         [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
125  HARDFLOAT,
126  NeverHasSideEffects;
127
128multiclass ABSS_M<string opstr, InstrItinClass Itin,
129                  SDPatternOperator OpNode= null_frag> {
130  def _D32 : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
131             FGR_32;
132  def _D64 : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>, FGR_64 {
133    string DecoderNamespace = "Mips64";
134  }
135}
136
137multiclass ROUND_M<string opstr, InstrItinClass Itin> {
138  def _D32 : MMRel, ABSS_FT<opstr, FGR32Opnd, AFGR64Opnd, Itin>, FGR_32;
139  def _D64 : StdMMR6Rel, ABSS_FT<opstr, FGR32Opnd, FGR64Opnd, Itin>, FGR_64 {
140    let DecoderNamespace = "Mips64";
141  }
142}
143
144class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
145              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
146  InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
147         [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT;
148
149class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
150              InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
151  InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
152         [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT;
153
154class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
155                 InstrItinClass Itin> :
156  InstSE<(outs DstRC:$fs), (ins DstRC:$fs_in, SrcRC:$rt),
157         !strconcat(opstr, "\t$rt, $fs"), [], Itin, FrmFR, opstr>, HARDFLOAT {
158  // $fs_in is part of a white lie to work around a widespread bug in the FPU
159  // implementation. See expandBuildPairF64 for details.
160  let Constraints = "$fs = $fs_in";
161}
162
163class LW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
164            InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
165  InstSE<(outs RC:$rt), (ins MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
166         [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr>,
167  HARDFLOAT {
168  let DecoderMethod = "DecodeFMem";
169  let mayLoad = 1;
170}
171
172class SW_FT<string opstr, RegisterOperand RC, DAGOperand MO,
173            InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
174  InstSE<(outs), (ins RC:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
175         [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr>, HARDFLOAT {
176  let DecoderMethod = "DecodeFMem";
177  let mayStore = 1;
178}
179
180class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
181               SDPatternOperator OpNode = null_frag> :
182  InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
183         !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
184         [(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
185         FrmFR, opstr>, HARDFLOAT;
186
187class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
188                SDPatternOperator OpNode = null_frag> :
189  InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
190         !strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
191         [(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
192         Itin, FrmFR, opstr>, HARDFLOAT;
193
194class LWXC1_FT<string opstr, RegisterOperand DRC,
195               InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
196  InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
197         !strconcat(opstr, "\t$fd, ${index}(${base})"),
198         [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
199         FrmFI, opstr>, HARDFLOAT {
200  let AddedComplexity = 20;
201}
202
203class SWXC1_FT<string opstr, RegisterOperand DRC,
204               InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
205  InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
206         !strconcat(opstr, "\t$fs, ${index}(${base})"),
207         [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
208         FrmFI, opstr>, HARDFLOAT {
209  let AddedComplexity = 20;
210}
211
212class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin,
213              SDPatternOperator Op = null_frag, bit DelaySlot = 1> :
214  InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset),
215         !strconcat(opstr, "\t$fcc, $offset"),
216         [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin,
217         FrmFI, opstr>, HARDFLOAT {
218  let isBranch = 1;
219  let isTerminator = 1;
220  let hasDelaySlot = DelaySlot;
221  let Defs = [AT];
222}
223
224class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin,
225              SDPatternOperator OpNode = null_frag>  :
226  InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond),
227         !strconcat("c.$cond.", typestr, "\t$fs, $ft"),
228         [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR,
229         !strconcat("c.$cond.", typestr)>, HARDFLOAT {
230  let Defs = [FCC0];
231  let isCodeGenOnly = 1;
232}
233
234class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC,
235                InstrItinClass itin>  :
236   InstSE<(outs), (ins RC:$fs, RC:$ft),
237          !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin,
238          FrmFR>, HARDFLOAT;
239
240multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt,
241                    InstrItinClass itin> {
242  def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>;
243  def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>;
244  def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>;
245  def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>;
246  def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>;
247  def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>;
248  def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>;
249  def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>;
250  def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>;
251  def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>;
252  def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>;
253  def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>;
254  def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>;
255  def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>;
256  def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>;
257  def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>;
258}
259
260defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6;
261defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
262           FGR_32;
263let DecoderNamespace = "Mips64" in
264defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6,
265           FGR_64;
266
267//===----------------------------------------------------------------------===//
268// Floating Point Instructions
269//===----------------------------------------------------------------------===//
270def ROUND_W_S  : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>,
271                 ABSS_FM<0xc, 16>, ISA_MIPS2;
272defm ROUND_W : ROUND_M<"round.w.d", II_ROUND>, ABSS_FM<0xc, 17>, ISA_MIPS2;
273def TRUNC_W_S  : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>,
274                 ABSS_FM<0xd, 16>, ISA_MIPS2;
275def CEIL_W_S   : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
276                 ABSS_FM<0xe, 16>, ISA_MIPS2;
277def FLOOR_W_S  : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>,
278                 ABSS_FM<0xf, 16>, ISA_MIPS2;
279def CVT_W_S    : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
280                 ABSS_FM<0x24, 16>;
281
282defm TRUNC_W : ROUND_M<"trunc.w.d", II_TRUNC>, ABSS_FM<0xd, 17>, ISA_MIPS2;
283defm CEIL_W  : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
284defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
285defm CVT_W   : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
286
287let DecoderNamespace = "Mips64" in {
288  let AdditionalPredicates = [NotInMicroMips] in {
289  def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
290                  ABSS_FM<0x8, 16>, FGR_64;
291  def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
292                    ABSS_FM<0x8, 17>, FGR_64;
293  def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
294                  ABSS_FM<0x9, 16>, FGR_64;
295  def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
296                    ABSS_FM<0x9, 17>, FGR_64;
297  def CEIL_L_S  : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
298                  ABSS_FM<0xa, 16>, FGR_64;
299  def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
300                   ABSS_FM<0xa, 17>, FGR_64;
301  def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
302                  ABSS_FM<0xb, 16>, FGR_64;
303  def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
304                    ABSS_FM<0xb, 17>, FGR_64;
305  }
306}
307
308def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
309              ABSS_FM<0x20, 20>;
310let AdditionalPredicates = [NotInMicroMips] in{
311  def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
312                ABSS_FM<0x25, 16>, INSN_MIPS3_32R2;
313  def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
314                 ABSS_FM<0x25, 17>, INSN_MIPS3_32R2;
315}
316
317def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
318                ABSS_FM<0x20, 17>, FGR_32;
319def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
320                ABSS_FM<0x21, 20>, FGR_32;
321def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
322                ABSS_FM<0x21, 16>, FGR_32;
323
324let DecoderNamespace = "Mips64" in {
325  def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
326                  ABSS_FM<0x20, 17>, FGR_64;
327  let AdditionalPredicates = [NotInMicroMips] in{
328    def CVT_S_L   : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
329                    ABSS_FM<0x20, 21>, FGR_64;
330  }
331  def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
332                  ABSS_FM<0x21, 20>, FGR_64;
333  def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
334                  ABSS_FM<0x21, 16>, FGR_64;
335  def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
336                  ABSS_FM<0x21, 21>, FGR_64;
337}
338
339let isPseudo = 1, isCodeGenOnly = 1 in {
340  def PseudoCVT_S_W : ABSS_FT<"", FGR32Opnd, GPR32Opnd, II_CVT>;
341  def PseudoCVT_D32_W : ABSS_FT<"", AFGR64Opnd, GPR32Opnd, II_CVT>;
342  def PseudoCVT_S_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
343  def PseudoCVT_D64_W : ABSS_FT<"", FGR64Opnd, GPR32Opnd, II_CVT>;
344  def PseudoCVT_D64_L : ABSS_FT<"", FGR64Opnd, GPR64Opnd, II_CVT>;
345}
346
347def FABS_S : MMRel, ABSS_FT<"abs.s", FGR32Opnd, FGR32Opnd, II_ABS, fabs>,
348             ABSS_FM<0x5, 16>;
349def FNEG_S : MMRel, ABSS_FT<"neg.s", FGR32Opnd, FGR32Opnd, II_NEG, fneg>,
350             ABSS_FM<0x7, 16>;
351defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>;
352defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>;
353
354def FSQRT_S : MMRel, StdMMR6Rel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd,
355              II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2;
356defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2;
357
358// The odd-numbered registers are only referenced when doing loads,
359// stores, and moves between floating-point and integer registers.
360// When defining instructions, we reference all 32-bit registers,
361// regardless of register aliasing.
362
363/// Move Control Registers From/To CPU Registers
364def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
365def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
366def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
367                          bitconvert>, MFC1_FM<0>;
368def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
369                          bitconvert>, MFC1_FM<4>;
370let AdditionalPredicates = [NotInMicroMips] in {
371  def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
372                  MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
373  def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
374                  MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
375    let DecoderNamespace = "Mips64";
376  }
377}
378let AdditionalPredicates = [NotInMicroMips] in {
379  def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
380                  MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
381  def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
382                  MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
383    let DecoderNamespace = "Mips64";
384  }
385}
386let AdditionalPredicates = [NotInMicroMips] in {
387  def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
388              bitconvert>, MFC1_FM<5>, ISA_MIPS3;
389  def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
390                      bitconvert>, MFC1_FM<1>, ISA_MIPS3;
391}
392
393def FMOV_S   : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
394               ABSS_FM<0x6, 16>;
395def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>,
396               ABSS_FM<0x6, 17>, FGR_32;
397def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
398               ABSS_FM<0x6, 17>, FGR_64 {
399                 let DecoderNamespace = "Mips64";
400}
401
402/// Floating Point Memory Instructions
403let AdditionalPredicates = [NotInMicroMips] in {
404  def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,
405             LW_FM<0x31>;
406  def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, mem_simm16, II_SWC1, store>,
407             LW_FM<0x39>;
408}
409
410let DecoderNamespace = "Mips64", AdditionalPredicates = [NotInMicroMips] in {
411  def LDC164 : StdMMR6Rel, LW_FT<"ldc1", FGR64Opnd, mem_simm16, II_LDC1, load>,
412               LW_FM<0x35>, ISA_MIPS2, FGR_64 {
413    let BaseOpcode = "LDC164";
414  }
415  def SDC164 : StdMMR6Rel, SW_FT<"sdc1", FGR64Opnd, mem_simm16, II_SDC1, store>,
416               LW_FM<0x3d>, ISA_MIPS2, FGR_64;
417}
418
419let AdditionalPredicates = [NotInMicroMips] in {
420  def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1,
421                                      load>, LW_FM<0x35>, ISA_MIPS2, FGR_32 {
422    let BaseOpcode = "LDC132";
423  }
424  def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, mem_simm16, II_SDC1, store>,
425             LW_FM<0x3d>, ISA_MIPS2, FGR_32;
426}
427
428// Indexed loads and stores.
429// Base register + offset register addressing mode (indicated by "x" in the
430// instruction mnemonic) is disallowed under NaCl.
431let AdditionalPredicates = [IsNotNaCl] in {
432  def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>,
433              INSN_MIPS4_32R2_NOT_32R6_64R6;
434  def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>,
435              INSN_MIPS4_32R2_NOT_32R6_64R6;
436}
437
438let AdditionalPredicates = [NotInMicroMips, IsNotNaCl] in {
439  def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
440              INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
441  def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
442              INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
443}
444
445let DecoderNamespace="Mips64" in {
446  def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
447                INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
448  def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
449                INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
450}
451
452// Load/store doubleword indexed unaligned.
453let AdditionalPredicates = [IsNotNaCl] in {
454  def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
455              INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
456  def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
457              INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
458}
459
460let DecoderNamespace="Mips64" in {
461  def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
462                INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
463  def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
464                INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
465}
466
467/// Floating-point Aritmetic
468def FADD_S : MMRel, ADDS_FT<"add.s", FGR32Opnd, II_ADD_S, 1, fadd>,
469             ADDS_FM<0x00, 16>;
470defm FADD :  ADDS_M<"add.d", II_ADD_D, 1, fadd>, ADDS_FM<0x00, 17>;
471def FDIV_S : MMRel, ADDS_FT<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>,
472             ADDS_FM<0x03, 16>;
473defm FDIV :  ADDS_M<"div.d", II_DIV_D, 0, fdiv>, ADDS_FM<0x03, 17>;
474def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
475             ADDS_FM<0x02, 16>;
476defm FMUL :  ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
477def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
478             ADDS_FM<0x01, 16>;
479defm FSUB :  ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
480
481def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
482             MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
483def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
484             MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
485
486let AdditionalPredicates = [NoNaNsFPMath] in {
487  def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
488                MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
489  def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
490                MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
491}
492
493def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
494               MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
495def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
496               MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
497
498let AdditionalPredicates = [NoNaNsFPMath] in {
499  def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
500                  MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
501  def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
502                  MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
503}
504
505let DecoderNamespace = "Mips64" in {
506  def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
507                 MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
508  def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
509                 MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
510}
511
512let AdditionalPredicates = [NoNaNsFPMath],
513    DecoderNamespace = "Mips64" in {
514  def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
515                  MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
516  def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
517                  MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
518}
519
520//===----------------------------------------------------------------------===//
521// Floating Point Branch Codes
522//===----------------------------------------------------------------------===//
523// Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
524// They must be kept in synch.
525def MIPS_BRANCH_F  : PatLeaf<(i32 0)>;
526def MIPS_BRANCH_T  : PatLeaf<(i32 1)>;
527
528def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
529           BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
530def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, II_BC1FL, MIPS_BRANCH_F, 0>,
531            BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
532def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
533           BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
534def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>,
535            BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
536
537/// Floating Point Compare
538let AdditionalPredicates = [NotInMicroMips] in {
539  def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
540                 ISA_MIPS1_NOT_32R6_64R6;
541  def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
542                 ISA_MIPS1_NOT_32R6_64R6, FGR_32;
543}
544let DecoderNamespace = "Mips64" in
545def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>,
546               ISA_MIPS1_NOT_32R6_64R6, FGR_64;
547
548//===----------------------------------------------------------------------===//
549// Floating Point Pseudo-Instructions
550//===----------------------------------------------------------------------===//
551
552// This pseudo instr gets expanded into 2 mtc1 instrs after register
553// allocation.
554class BuildPairF64Base<RegisterOperand RO> :
555  PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
556           [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))],
557           II_MTC1>;
558
559def BuildPairF64 : BuildPairF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
560def BuildPairF64_64 : BuildPairF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
561
562// This pseudo instr gets expanded into 2 mfc1 instrs after register
563// allocation.
564// if n is 0, lower part of src is extracted.
565// if n is 1, higher part of src is extracted.
566// This node has associated scheduling information as the pre RA scheduler
567// asserts otherwise.
568class ExtractElementF64Base<RegisterOperand RO> :
569  PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
570           [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))],
571           II_MFC1>;
572
573def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
574def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
575
576def PseudoTRUNC_W_S : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
577                                        (ins FGR32Opnd:$fs, GPR32Opnd:$rs),
578                                        "trunc.w.s\t$fd, $fs, $rs">;
579
580def PseudoTRUNC_W_D32 : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
581                                          (ins AFGR64Opnd:$fs, GPR32Opnd:$rs),
582                                          "trunc.w.d\t$fd, $fs, $rs">,
583                        FGR_32, HARDFLOAT;
584
585def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd),
586                                        (ins FGR64Opnd:$fs, GPR32Opnd:$rs),
587                                        "trunc.w.d\t$fd, $fs, $rs">,
588                      FGR_64, HARDFLOAT;
589
590//===----------------------------------------------------------------------===//
591// InstAliases.
592//===----------------------------------------------------------------------===//
593def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
594      ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
595def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
596      ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT;
597def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
598      ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT;
599def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
600      ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT;
601
602//===----------------------------------------------------------------------===//
603// Floating Point Patterns
604//===----------------------------------------------------------------------===//
605def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
606def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
607
608def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
609              (PseudoCVT_S_W GPR32Opnd:$src)>;
610def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
611              (TRUNC_W_S FGR32Opnd:$src)>;
612
613def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
614              (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
615def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
616              (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32;
617def : MipsPat<(f32 (fround AFGR64Opnd:$src)),
618              (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32;
619def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
620              (CVT_D32_S FGR32Opnd:$src)>, FGR_32;
621
622def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64;
623def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
624
625def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
626              (PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
627def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
628              (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;
629def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
630              (PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;
631
632def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
633              (TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64;
634def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
635              (TRUNC_L_S FGR32Opnd:$src)>, FGR_64;
636def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
637              (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64;
638
639def : MipsPat<(f32 (fround FGR64Opnd:$src)),
640              (CVT_S_D64 FGR64Opnd:$src)>, FGR_64;
641def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
642              (CVT_D64_S FGR32Opnd:$src)>, FGR_64;
643
644// Patterns for loads/stores with a reg+imm operand.
645let AdditionalPredicates = [NotInMicroMips] in {
646  let AddedComplexity = 40 in {
647    def : LoadRegImmPat<LWC1, f32, load>;
648    def : StoreRegImmPat<SWC1, f32>;
649
650    def : LoadRegImmPat<LDC164, f64, load>, FGR_64;
651    def : StoreRegImmPat<SDC164, f64>, FGR_64;
652
653    def : LoadRegImmPat<LDC1, f64, load>, FGR_32;
654    def : StoreRegImmPat<SDC1, f64>, FGR_32;
655  }
656}
657