1//===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the MIPS32/64 implementation of the TargetRegisterInfo
11// class.
12//
13//===----------------------------------------------------------------------===//
14
15#include "MipsSERegisterInfo.h"
16#include "Mips.h"
17#include "MipsMachineFunction.h"
18#include "MipsSEInstrInfo.h"
19#include "MipsSubtarget.h"
20#include "MipsTargetMachine.h"
21#include "llvm/ADT/STLExtras.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineRegisterInfo.h"
26#include "llvm/IR/Constants.h"
27#include "llvm/IR/DebugInfo.h"
28#include "llvm/IR/Function.h"
29#include "llvm/IR/Type.h"
30#include "llvm/Support/Debug.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/raw_ostream.h"
33#include "llvm/Target/TargetFrameLowering.h"
34#include "llvm/Target/TargetInstrInfo.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetOptions.h"
37
38using namespace llvm;
39
40#define DEBUG_TYPE "mips-reg-info"
41
42MipsSERegisterInfo::MipsSERegisterInfo() : MipsRegisterInfo() {}
43
44bool MipsSERegisterInfo::
45requiresRegisterScavenging(const MachineFunction &MF) const {
46  return true;
47}
48
49bool MipsSERegisterInfo::
50requiresFrameIndexScavenging(const MachineFunction &MF) const {
51  return true;
52}
53
54const TargetRegisterClass *
55MipsSERegisterInfo::intRegClass(unsigned Size) const {
56  if (Size == 4)
57    return &Mips::GPR32RegClass;
58
59  assert(Size == 8);
60  return &Mips::GPR64RegClass;
61}
62
63/// Get the size of the offset supported by the given load/store.
64/// The result includes the effects of any scale factors applied to the
65/// instruction immediate.
66static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) {
67  switch (Opcode) {
68  case Mips::LD_B:
69  case Mips::ST_B:
70    return 10;
71  case Mips::LD_H:
72  case Mips::ST_H:
73    return 10 + 1 /* scale factor */;
74  case Mips::LD_W:
75  case Mips::ST_W:
76    return 10 + 2 /* scale factor */;
77  case Mips::LD_D:
78  case Mips::ST_D:
79    return 10 + 3 /* scale factor */;
80  default:
81    return 16;
82  }
83}
84
85/// Get the scale factor applied to the immediate in the given load/store.
86static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
87  switch (Opcode) {
88  case Mips::LD_H:
89  case Mips::ST_H:
90    return 2;
91  case Mips::LD_W:
92  case Mips::ST_W:
93    return 4;
94  case Mips::LD_D:
95  case Mips::ST_D:
96    return 8;
97  default:
98    return 1;
99  }
100}
101
102void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
103                                     unsigned OpNo, int FrameIndex,
104                                     uint64_t StackSize,
105                                     int64_t SPOffset) const {
106  MachineInstr &MI = *II;
107  MachineFunction &MF = *MI.getParent()->getParent();
108  MachineFrameInfo *MFI = MF.getFrameInfo();
109  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
110
111  MipsABIInfo ABI =
112      static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
113  const MipsRegisterInfo *RegInfo =
114    static_cast<const MipsRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
115
116  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
117  int MinCSFI = 0;
118  int MaxCSFI = -1;
119
120  if (CSI.size()) {
121    MinCSFI = CSI[0].getFrameIdx();
122    MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
123  }
124
125  bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
126  bool IsISRRegFI = MipsFI->isISRRegFI(FrameIndex);
127  // The following stack frame objects are always referenced relative to $sp:
128  //  1. Outgoing arguments.
129  //  2. Pointer to dynamically allocated stack space.
130  //  3. Locations for callee-saved registers.
131  //  4. Locations for eh data registers.
132  //  5. Locations for ISR saved Coprocessor 0 registers 12 & 14.
133  // Everything else is referenced relative to whatever register
134  // getFrameRegister() returns.
135  unsigned FrameReg;
136
137  if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI ||
138      IsISRRegFI)
139    FrameReg = ABI.GetStackPtr();
140  else if (RegInfo->needsStackRealignment(MF)) {
141    if (MFI->hasVarSizedObjects() && !MFI->isFixedObjectIndex(FrameIndex))
142      FrameReg = ABI.GetBasePtr();
143    else if (MFI->isFixedObjectIndex(FrameIndex))
144      FrameReg = getFrameRegister(MF);
145    else
146      FrameReg = ABI.GetStackPtr();
147  } else
148    FrameReg = getFrameRegister(MF);
149
150  // Calculate final offset.
151  // - There is no need to change the offset if the frame object is one of the
152  //   following: an outgoing argument, pointer to a dynamically allocated
153  //   stack space or a $gp restore location,
154  // - If the frame object is any of the following, its offset must be adjusted
155  //   by adding the size of the stack:
156  //   incoming argument, callee-saved register location or local variable.
157  bool IsKill = false;
158  int64_t Offset;
159
160  Offset = SPOffset + (int64_t)StackSize;
161  Offset += MI.getOperand(OpNo + 1).getImm();
162
163  DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
164
165  if (!MI.isDebugValue()) {
166    // Make sure Offset fits within the field available.
167    // For MSA instructions, this is a 10-bit signed immediate (scaled by
168    // element size), otherwise it is a 16-bit signed immediate.
169    unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode());
170    unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
171
172    if (OffsetBitSize < 16 && isInt<16>(Offset) &&
173        (!isIntN(OffsetBitSize, Offset) ||
174         OffsetToAlignment(Offset, OffsetAlign) != 0)) {
175      // If we have an offset that needs to fit into a signed n-bit immediate
176      // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
177      MachineBasicBlock &MBB = *MI.getParent();
178      DebugLoc DL = II->getDebugLoc();
179      const TargetRegisterClass *PtrRC =
180          ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
181      MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
182      unsigned Reg = RegInfo.createVirtualRegister(PtrRC);
183      const MipsSEInstrInfo &TII =
184          *static_cast<const MipsSEInstrInfo *>(
185              MBB.getParent()->getSubtarget().getInstrInfo());
186      BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAddiuOp()), Reg)
187          .addReg(FrameReg)
188          .addImm(Offset);
189
190      FrameReg = Reg;
191      Offset = 0;
192      IsKill = true;
193    } else if (!isInt<16>(Offset)) {
194      // Otherwise split the offset into 16-bit pieces and add it in multiple
195      // instructions.
196      MachineBasicBlock &MBB = *MI.getParent();
197      DebugLoc DL = II->getDebugLoc();
198      unsigned NewImm = 0;
199      const MipsSEInstrInfo &TII =
200          *static_cast<const MipsSEInstrInfo *>(
201              MBB.getParent()->getSubtarget().getInstrInfo());
202      unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
203                                       OffsetBitSize == 16 ? &NewImm : nullptr);
204      BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
205        .addReg(Reg, RegState::Kill);
206
207      FrameReg = Reg;
208      Offset = SignExtend64<16>(NewImm);
209      IsKill = true;
210    }
211  }
212
213  MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
214  MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
215}
216