1//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an PPC MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstPrinter.h"
15#include "MCTargetDesc/PPCMCTargetDesc.h"
16#include "MCTargetDesc/PPCPredicates.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstrInfo.h"
20#include "llvm/MC/MCRegisterInfo.h"
21#include "llvm/MC/MCSubtargetInfo.h"
22#include "llvm/MC/MCSymbol.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/raw_ostream.h"
25#include "llvm/Target/TargetOpcodes.h"
26using namespace llvm;
27
28#define DEBUG_TYPE "asm-printer"
29
30// FIXME: Once the integrated assembler supports full register names, tie this
31// to the verbose-asm setting.
32static cl::opt<bool>
33FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
34             cl::desc("Use full register names when printing assembly"));
35
36#define PRINT_ALIAS_INSTR
37#include "PPCGenAsmWriter.inc"
38
39void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
40  const char *RegName = getRegisterName(RegNo);
41  if (RegName[0] == 'q' /* QPX */) {
42    // The system toolchain on the BG/Q does not understand QPX register names
43    // in .cfi_* directives, so print the name of the floating-point
44    // subregister instead.
45    std::string RN(RegName);
46
47    RN[0] = 'f';
48    OS << RN;
49
50    return;
51  }
52
53  OS << RegName;
54}
55
56void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
57                               StringRef Annot, const MCSubtargetInfo &STI) {
58  // Check for slwi/srwi mnemonics.
59  if (MI->getOpcode() == PPC::RLWINM) {
60    unsigned char SH = MI->getOperand(2).getImm();
61    unsigned char MB = MI->getOperand(3).getImm();
62    unsigned char ME = MI->getOperand(4).getImm();
63    bool useSubstituteMnemonic = false;
64    if (SH <= 31 && MB == 0 && ME == (31-SH)) {
65      O << "\tslwi "; useSubstituteMnemonic = true;
66    }
67    if (SH <= 31 && MB == (32-SH) && ME == 31) {
68      O << "\tsrwi "; useSubstituteMnemonic = true;
69      SH = 32-SH;
70    }
71    if (useSubstituteMnemonic) {
72      printOperand(MI, 0, O);
73      O << ", ";
74      printOperand(MI, 1, O);
75      O << ", " << (unsigned int)SH;
76
77      printAnnotation(O, Annot);
78      return;
79    }
80  }
81
82  if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
83      MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
84    O << "\tmr ";
85    printOperand(MI, 0, O);
86    O << ", ";
87    printOperand(MI, 1, O);
88    printAnnotation(O, Annot);
89    return;
90  }
91
92  if (MI->getOpcode() == PPC::RLDICR) {
93    unsigned char SH = MI->getOperand(2).getImm();
94    unsigned char ME = MI->getOperand(3).getImm();
95    // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
96    if (63-SH == ME) {
97      O << "\tsldi ";
98      printOperand(MI, 0, O);
99      O << ", ";
100      printOperand(MI, 1, O);
101      O << ", " << (unsigned int)SH;
102      printAnnotation(O, Annot);
103      return;
104    }
105  }
106
107  // dcbt[st] is printed manually here because:
108  //  1. The assembly syntax is different between embedded and server targets
109  //  2. We must print the short mnemonics for TH == 0 because the
110  //     embedded/server syntax default will not be stable across assemblers
111  //  The syntax for dcbt is:
112  //    dcbt ra, rb, th [server]
113  //    dcbt th, ra, rb [embedded]
114  //  where th can be omitted when it is 0. dcbtst is the same.
115  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
116    unsigned char TH = MI->getOperand(0).getImm();
117    O << "\tdcbt";
118    if (MI->getOpcode() == PPC::DCBTST)
119      O << "st";
120    if (TH == 16)
121      O << "t";
122    O << " ";
123
124    bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
125    if (IsBookE && TH != 0 && TH != 16)
126      O << (unsigned int) TH << ", ";
127
128    printOperand(MI, 1, O);
129    O << ", ";
130    printOperand(MI, 2, O);
131
132    if (!IsBookE && TH != 0 && TH != 16)
133      O << ", " << (unsigned int) TH;
134
135    printAnnotation(O, Annot);
136    return;
137  }
138
139  if (!printAliasInstr(MI, O))
140    printInstruction(MI, O);
141  printAnnotation(O, Annot);
142}
143
144
145void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
146                                           raw_ostream &O,
147                                           const char *Modifier) {
148  unsigned Code = MI->getOperand(OpNo).getImm();
149
150  if (StringRef(Modifier) == "cc") {
151    switch ((PPC::Predicate)Code) {
152    case PPC::PRED_LT_MINUS:
153    case PPC::PRED_LT_PLUS:
154    case PPC::PRED_LT:
155      O << "lt";
156      return;
157    case PPC::PRED_LE_MINUS:
158    case PPC::PRED_LE_PLUS:
159    case PPC::PRED_LE:
160      O << "le";
161      return;
162    case PPC::PRED_EQ_MINUS:
163    case PPC::PRED_EQ_PLUS:
164    case PPC::PRED_EQ:
165      O << "eq";
166      return;
167    case PPC::PRED_GE_MINUS:
168    case PPC::PRED_GE_PLUS:
169    case PPC::PRED_GE:
170      O << "ge";
171      return;
172    case PPC::PRED_GT_MINUS:
173    case PPC::PRED_GT_PLUS:
174    case PPC::PRED_GT:
175      O << "gt";
176      return;
177    case PPC::PRED_NE_MINUS:
178    case PPC::PRED_NE_PLUS:
179    case PPC::PRED_NE:
180      O << "ne";
181      return;
182    case PPC::PRED_UN_MINUS:
183    case PPC::PRED_UN_PLUS:
184    case PPC::PRED_UN:
185      O << "un";
186      return;
187    case PPC::PRED_NU_MINUS:
188    case PPC::PRED_NU_PLUS:
189    case PPC::PRED_NU:
190      O << "nu";
191      return;
192    case PPC::PRED_BIT_SET:
193    case PPC::PRED_BIT_UNSET:
194      llvm_unreachable("Invalid use of bit predicate code");
195    }
196    llvm_unreachable("Invalid predicate code");
197  }
198
199  if (StringRef(Modifier) == "pm") {
200    switch ((PPC::Predicate)Code) {
201    case PPC::PRED_LT:
202    case PPC::PRED_LE:
203    case PPC::PRED_EQ:
204    case PPC::PRED_GE:
205    case PPC::PRED_GT:
206    case PPC::PRED_NE:
207    case PPC::PRED_UN:
208    case PPC::PRED_NU:
209      return;
210    case PPC::PRED_LT_MINUS:
211    case PPC::PRED_LE_MINUS:
212    case PPC::PRED_EQ_MINUS:
213    case PPC::PRED_GE_MINUS:
214    case PPC::PRED_GT_MINUS:
215    case PPC::PRED_NE_MINUS:
216    case PPC::PRED_UN_MINUS:
217    case PPC::PRED_NU_MINUS:
218      O << "-";
219      return;
220    case PPC::PRED_LT_PLUS:
221    case PPC::PRED_LE_PLUS:
222    case PPC::PRED_EQ_PLUS:
223    case PPC::PRED_GE_PLUS:
224    case PPC::PRED_GT_PLUS:
225    case PPC::PRED_NE_PLUS:
226    case PPC::PRED_UN_PLUS:
227    case PPC::PRED_NU_PLUS:
228      O << "+";
229      return;
230    case PPC::PRED_BIT_SET:
231    case PPC::PRED_BIT_UNSET:
232      llvm_unreachable("Invalid use of bit predicate code");
233    }
234    llvm_unreachable("Invalid predicate code");
235  }
236
237  assert(StringRef(Modifier) == "reg" &&
238         "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
239  printOperand(MI, OpNo+1, O);
240}
241
242void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
243                                       raw_ostream &O) {
244  unsigned int Value = MI->getOperand(OpNo).getImm();
245  assert(Value <= 1 && "Invalid u1imm argument!");
246  O << (unsigned int)Value;
247}
248
249void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
250                                       raw_ostream &O) {
251  unsigned int Value = MI->getOperand(OpNo).getImm();
252  assert(Value <= 3 && "Invalid u2imm argument!");
253  O << (unsigned int)Value;
254}
255
256void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
257                                       raw_ostream &O) {
258  unsigned int Value = MI->getOperand(OpNo).getImm();
259  assert(Value <= 8 && "Invalid u3imm argument!");
260  O << (unsigned int)Value;
261}
262
263void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
264                                       raw_ostream &O) {
265  unsigned int Value = MI->getOperand(OpNo).getImm();
266  assert(Value <= 15 && "Invalid u4imm argument!");
267  O << (unsigned int)Value;
268}
269
270void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
271                                       raw_ostream &O) {
272  int Value = MI->getOperand(OpNo).getImm();
273  Value = SignExtend32<5>(Value);
274  O << (int)Value;
275}
276
277void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
278                                       raw_ostream &O) {
279  unsigned int Value = MI->getOperand(OpNo).getImm();
280  assert(Value <= 31 && "Invalid u5imm argument!");
281  O << (unsigned int)Value;
282}
283
284void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
285                                       raw_ostream &O) {
286  unsigned int Value = MI->getOperand(OpNo).getImm();
287  assert(Value <= 63 && "Invalid u6imm argument!");
288  O << (unsigned int)Value;
289}
290
291void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
292                                       raw_ostream &O) {
293  unsigned int Value = MI->getOperand(OpNo).getImm();
294  assert(Value <= 127 && "Invalid u7imm argument!");
295  O << (unsigned int)Value;
296}
297
298void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
299                                       raw_ostream &O) {
300  unsigned int Value = MI->getOperand(OpNo).getImm();
301  assert(Value <= 255 && "Invalid u8imm argument!");
302  O << (unsigned int)Value;
303}
304
305void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
306                                        raw_ostream &O) {
307  unsigned short Value = MI->getOperand(OpNo).getImm();
308  assert(Value <= 1023 && "Invalid u10imm argument!");
309  O << (unsigned short)Value;
310}
311
312void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
313                                        raw_ostream &O) {
314  unsigned short Value = MI->getOperand(OpNo).getImm();
315  assert(Value <= 4095 && "Invalid u12imm argument!");
316  O << (unsigned short)Value;
317}
318
319void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
320                                        raw_ostream &O) {
321  if (MI->getOperand(OpNo).isImm())
322    O << (short)MI->getOperand(OpNo).getImm();
323  else
324    printOperand(MI, OpNo, O);
325}
326
327void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
328                                        raw_ostream &O) {
329  if (MI->getOperand(OpNo).isImm())
330    O << (unsigned short)MI->getOperand(OpNo).getImm();
331  else
332    printOperand(MI, OpNo, O);
333}
334
335void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
336                                        raw_ostream &O) {
337  if (!MI->getOperand(OpNo).isImm())
338    return printOperand(MI, OpNo, O);
339
340  // Branches can take an immediate operand.  This is used by the branch
341  // selection pass to print .+8, an eight byte displacement from the PC.
342  O << ".+";
343  printAbsBranchOperand(MI, OpNo, O);
344}
345
346void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
347                                           raw_ostream &O) {
348  if (!MI->getOperand(OpNo).isImm())
349    return printOperand(MI, OpNo, O);
350
351  O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
352}
353
354
355void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
356                                 raw_ostream &O) {
357  unsigned CCReg = MI->getOperand(OpNo).getReg();
358  unsigned RegNo;
359  switch (CCReg) {
360  default: llvm_unreachable("Unknown CR register");
361  case PPC::CR0: RegNo = 0; break;
362  case PPC::CR1: RegNo = 1; break;
363  case PPC::CR2: RegNo = 2; break;
364  case PPC::CR3: RegNo = 3; break;
365  case PPC::CR4: RegNo = 4; break;
366  case PPC::CR5: RegNo = 5; break;
367  case PPC::CR6: RegNo = 6; break;
368  case PPC::CR7: RegNo = 7; break;
369  }
370  O << (0x80 >> RegNo);
371}
372
373void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
374                                    raw_ostream &O) {
375  printS16ImmOperand(MI, OpNo, O);
376  O << '(';
377  if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
378    O << "0";
379  else
380    printOperand(MI, OpNo+1, O);
381  O << ')';
382}
383
384void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
385                                    raw_ostream &O) {
386  // When used as the base register, r0 reads constant zero rather than
387  // the value contained in the register.  For this reason, the darwin
388  // assembler requires that we print r0 as 0 (no r) when used as the base.
389  if (MI->getOperand(OpNo).getReg() == PPC::R0)
390    O << "0";
391  else
392    printOperand(MI, OpNo, O);
393  O << ", ";
394  printOperand(MI, OpNo+1, O);
395}
396
397void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
398                                  raw_ostream &O) {
399  // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
400  // come at the _end_ of the expression.
401  const MCOperand &Op = MI->getOperand(OpNo);
402  const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
403  O << refExp.getSymbol().getName();
404  O << '(';
405  printOperand(MI, OpNo+1, O);
406  O << ')';
407  if (refExp.getKind() != MCSymbolRefExpr::VK_None)
408    O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
409}
410
411
412/// stripRegisterPrefix - This method strips the character prefix from a
413/// register name so that only the number is left.  Used by for linux asm.
414static const char *stripRegisterPrefix(const char *RegName) {
415  if (FullRegNames)
416    return RegName;
417
418  switch (RegName[0]) {
419  case 'r':
420  case 'f':
421  case 'q': // for QPX
422  case 'v':
423    if (RegName[1] == 's')
424      return RegName + 2;
425    return RegName + 1;
426  case 'c': if (RegName[1] == 'r') return RegName + 2;
427  }
428
429  return RegName;
430}
431
432void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
433                                  raw_ostream &O) {
434  const MCOperand &Op = MI->getOperand(OpNo);
435  if (Op.isReg()) {
436    const char *RegName = getRegisterName(Op.getReg());
437    // The linux and AIX assembler does not take register prefixes.
438    if (!isDarwinSyntax())
439      RegName = stripRegisterPrefix(RegName);
440
441    O << RegName;
442    return;
443  }
444
445  if (Op.isImm()) {
446    O << Op.getImm();
447    return;
448  }
449
450  assert(Op.isExpr() && "unknown operand kind in printOperand");
451  Op.getExpr()->print(O, &MAI);
452}
453
454