PPCHazardRecognizers.cpp revision 88d211f82304e53694ece666d4a2507b170e4582 
1//===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements hazard recognizers for scheduling on PowerPC processors.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "sched"
15#include "PPCHazardRecognizers.h"
16#include "PPC.h"
17#include "PPCInstrInfo.h"
18#include "llvm/Support/Debug.h"
19#include <iostream>
20using namespace llvm;
21
22
23//===----------------------------------------------------------------------===//
24// PowerPC 970 Hazard Recognizer
25//
26// This models the dispatch group formation of the PPC970 processor.  Dispatch
27// groups are bundles of up to five instructions that can contain various mixes
28// of instructions.  The PPC970 can dispatch a peak of 4 non-branch and one
29// branch instruction per-cycle.
30//
31// There are a number of restrictions to dispatch group formation: some
32// instructions can only be issued in the first slot of a dispatch group, & some
33// instructions fill an entire dispatch group.  Additionally, only branches can
34// issue in the 5th (last) slot.
35//
36// Finally, there are a number of "structural" hazards on the PPC970.  These
37// conditions cause large performance penalties due to misprediction, recovery,
38// and replay logic that has to happen.  These cases include setting a CTR and
39// branching through it in the same dispatch group, and storing to an address,
40// then loading from the same address within a dispatch group.  To avoid these
41// conditions, we insert no-op instructions when appropriate.
42//
43// FIXME: This is missing some significant cases:
44//   1. Modeling of microcoded instructions.
45//   2. Handling of cracked instructions.
46//   3. Handling of serialized operations.
47//   4. Handling of the esoteric cases in "Resource-based Instruction Grouping",
48//      e.g. integer divides that only execute in the second slot.
49//
50
51PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
52  : TII(tii) {
53  EndDispatchGroup();
54}
55
56void PPCHazardRecognizer970::EndDispatchGroup() {
57  DEBUG(std::cerr << "=== Start of dispatch group\n");
58  NumIssued = 0;
59
60  // Structural hazard info.
61  HasCTRSet = false;
62  NumStores = 0;
63}
64
65
66PPCII::PPC970_Unit
67PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
68                                     bool &isFirst, bool &isSingle,
69                                     bool &isLoad, bool &isStore){
70  if (Opcode < ISD::BUILTIN_OP_END) {
71    isFirst = isSingle = isLoad = isStore = false;
72    return PPCII::PPC970_Pseudo;
73  }
74  Opcode -= ISD::BUILTIN_OP_END;
75
76  const TargetInstrDescriptor &TID = TII.get(Opcode);
77
78  isLoad  = TID.Flags & M_LOAD_FLAG;
79  isStore = TID.Flags & M_STORE_FLAG;
80
81  unsigned TSFlags = TID.TSFlags;
82
83  isFirst  = TSFlags & PPCII::PPC970_First;
84  isSingle = TSFlags & PPCII::PPC970_Single;
85  return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
86}
87
88/// isLoadOfStoredAddress - If we have a load from the previously stored pointer
89/// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
90bool PPCHazardRecognizer970::
91isLoadOfStoredAddress(unsigned LoadSize, SDOperand Ptr1, SDOperand Ptr2) const {
92  for (unsigned i = 0, e = NumStores; i != e; ++i) {
93    // Handle exact and commuted addresses.
94    if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i])
95      return true;
96    if (Ptr2 == StorePtr1[i] && Ptr1 == StorePtr2[i])
97      return true;
98
99    // Okay, we don't have an exact match, if this is an indexed offset, see if
100    // we have overlap (which happens during fp->int conversion for example).
101    if (StorePtr2[i] == Ptr2) {
102      if (ConstantSDNode *StoreOffset = dyn_cast<ConstantSDNode>(StorePtr1[i]))
103        if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) {
104          // Okay the base pointers match, so we have [c1+r] vs [c2+r].  Check
105          // to see if the load and store actually overlap.
106          int StoreOffs = StoreOffset->getValue();
107          int LoadOffs  = LoadOffset->getValue();
108          if (StoreOffs < LoadOffs) {
109            if (int(StoreOffs+StoreSize) > LoadOffs) return true;
110          } else {
111            if (int(LoadOffs+LoadSize) > StoreOffs) return true;
112          }
113        }
114    }
115  }
116  return false;
117}
118
119/// getHazardType - We return hazard for any non-branch instruction that would
120/// terminate terminate the dispatch group.  We turn NoopHazard for any
121/// instructions that wouldn't terminate the dispatch group that would cause a
122/// pipeline flush.
123HazardRecognizer::HazardType PPCHazardRecognizer970::
124getHazardType(SDNode *Node) {
125  bool isFirst, isSingle, isLoad, isStore;
126  PPCII::PPC970_Unit InstrType =
127    GetInstrType(Node->getOpcode(), isFirst, isSingle, isLoad, isStore);
128  if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
129  unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
130
131  // We can only issue a PPC970_First/PPC970_Single instruction (such as
132  // crand/mtspr/etc) if this is the first cycle of the dispatch group.
133  if (NumIssued != 0 && (isFirst || isSingle) )
134    return Hazard;
135
136  switch (InstrType) {
137  default: assert(0 && "Unknown instruction type!");
138  case PPCII::PPC970_FXU:
139  case PPCII::PPC970_LSU:
140  case PPCII::PPC970_FPU:
141  case PPCII::PPC970_VALU:
142  case PPCII::PPC970_VPERM:
143    // We can only issue a branch as the last instruction in a group.
144    if (NumIssued == 4) return Hazard;
145    break;
146  case PPCII::PPC970_CRU:
147    // We can only issue a CR instruction in the first two slots.
148    if (NumIssued >= 2) return Hazard;
149    break;
150  case PPCII::PPC970_BRU:
151    break;
152  }
153
154  // Do not allow MTCTR and BCTRL to be in the same dispatch group.
155  if (HasCTRSet && Opcode == PPC::BCTRL)
156    return NoopHazard;
157
158  // If this is a load following a store, make sure it's not to the same or
159  // overlapping address.
160  if (isLoad && StoreSize) {
161    unsigned LoadSize;
162    switch (Opcode) {
163    default: assert(0 && "Unknown load!");
164    case PPC::LBZ:
165    case PPC::LBZX:
166    case PPC::LVEBX:
167      LoadSize = 1;
168      break;
169    case PPC::LHA:
170    case PPC::LHAX:
171    case PPC::LHZ:
172    case PPC::LHZX:
173    case PPC::LVEHX:
174      LoadSize = 2;
175      break;
176    case PPC::LFS:
177    case PPC::LFSX:
178    case PPC::LWZ:
179    case PPC::LWZX:
180    case PPC::LWZU:
181    case PPC::LWA:
182    case PPC::LWAX:
183    case PPC::LVEWX:
184      LoadSize = 4;
185      break;
186    case PPC::LFD:
187    case PPC::LFDX:
188    case PPC::LD:
189    case PPC::LDX:
190      LoadSize = 8;
191      break;
192    case PPC::LVX:
193      LoadSize = 16;
194      break;
195    }
196
197    if (isLoadOfStoredAddress(LoadSize,
198                              Node->getOperand(0), Node->getOperand(1)))
199      return NoopHazard;
200  }
201
202  return NoHazard;
203}
204
205void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) {
206  bool isFirst, isSingle, isLoad, isStore;
207  PPCII::PPC970_Unit InstrType =
208    GetInstrType(Node->getOpcode(), isFirst, isSingle, isLoad, isStore);
209  if (InstrType == PPCII::PPC970_Pseudo) return;
210  unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
211
212  // Update structural hazard information.
213  if (Opcode == PPC::MTCTR) HasCTRSet = true;
214
215  // Track the address stored to.
216  if (isStore) {
217    unsigned ThisStoreSize;
218    switch (Opcode) {
219    default: assert(0 && "Unknown store instruction!");
220    case PPC::STBX:
221    case PPC::STB:
222    case PPC::STVEBX:
223      ThisStoreSize = 1;
224      break;
225    case PPC::STHX:
226    case PPC::STH:
227    case PPC::STVEHX:
228      ThisStoreSize = 2;
229      break;
230    case PPC::STFS:
231    case PPC::STFSX:
232    case PPC::STWU:
233    case PPC::STWX:
234    case PPC::STWUX:
235    case PPC::STW:
236    case PPC::STVEWX:
237    case PPC::STFIWX:
238      ThisStoreSize = 4;
239      break;
240    case PPC::STD:
241    case PPC::STDU:
242    case PPC::STFD:
243    case PPC::STFDX:
244    case PPC::STDX:
245    case PPC::STDUX:
246      ThisStoreSize = 8;
247      break;
248    case PPC::STVX:
249      ThisStoreSize = 16;
250      break;
251    }
252
253    StoreSize[NumStores] = ThisStoreSize;
254    StorePtr1[NumStores] = Node->getOperand(1);
255    StorePtr2[NumStores] = Node->getOperand(2);
256    ++NumStores;
257  }
258
259  if (InstrType == PPCII::PPC970_BRU || isSingle)
260    NumIssued = 4;  // Terminate a d-group.
261  ++NumIssued;
262
263  if (NumIssued == 5)
264    EndDispatchGroup();
265}
266
267void PPCHazardRecognizer970::AdvanceCycle() {
268  assert(NumIssued < 5 && "Illegal dispatch group!");
269  ++NumIssued;
270  if (NumIssued == 5)
271    EndDispatchGroup();
272}
273
274void PPCHazardRecognizer970::EmitNoop() {
275  AdvanceCycle();
276}
277