History log of /external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
de2d8694e25a814696358e95141f4b1aa4d8847e 20-Sep-2016 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r275480

Bug: http://b/31320715

This merges commit 7dcf7f03e005379ef2f06db96aa93f06186b66d5 from
aosp/dev.

Test: Build AOSP and run RenderScript tests (host tests for slang and
libbcc, RsTest, CTS)

Change-Id: Iaf3738f74312d875e69f61d604ac058f381a2a1a
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
ebe69fe11e48d322045d5949c83283927a0d790b 23-Mar-2015 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r230699.

Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
c6a4f5e819217e1e12c458aed8e7b122e23a3a58 21-Jul-2014 Stephen Hines <srhines@google.com> Update LLVM for rebase to r212749.

Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls

Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
80ada583f3b40ffb201e54cd57c42f9518039c9e 07-Jun-2013 Bill Wendling <isanbard@gmail.com> Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
86765fbe170198e7bb40fd8499d1354f4c786f60 22-Mar-2013 Ulrich Weigand <ulrich.weigand@de.ibm.com> Remove ABI-duplicated call instruction patterns.

We currently have a duplicated set of call instruction patterns depending
on the ABI to be followed (Darwin vs. Linux). This is a bit odd; while the
different ABIs will result in different instruction sequences, the actual
instructions themselves ought to be independent of the ABI. And in fact it
turns out that the only nontrivial difference between the two sets of
patterns is that in the PPC64 Linux ABI, the instruction used for indirect
calls is marked to take X11 as extra input register (which is indeed used
only with that ABI to hold an incoming environment pointer for nested
functions). However, this does not need to be hard-coded at the .td
pattern level; instead, the C++ code expanding calls can simply add that
use, just like it adds uses for argument registers anyway.

No change in generated code expected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
5b00ceaeeabff8c25abb09926343c3fcb06053d8 31-Mar-2012 Hal Finkel <hfinkel@anl.gov> Fix dynamic linking on PPC64.

Dynamic linking on PPC64 has had problems since we had to move the top-down
hazard-detection logic post-ra. For dynamic linking to work there needs to be
a nop placed after every call. It turns out that it is really hard to guarantee
that nothing will be placed in between the call (bl) and the nop during post-ra
scheduling. Previous attempts at fixing this by placing logic inside the
hazard detector only partially worked.

This is now fixed in a different way: call+nop codegen-only instructions. As far
as CodeGen is concerned the pair is now a single instruction and cannot be split.
This solution works much better than previous attempts.

The scoreboard hazard detector is also renamed to be more generic, there is currently
no cpu-specific logic in it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
7f370b615515af6422eb0d5d08f1c4c5db95fbbc 15-Dec-2011 Hal Finkel <hfinkel@anl.gov> Ensure that the nop that should follow a bl call in PPC64 ELF actually does

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
826941a0af2c8ef695a6424cc5c712ac3df67f4c 02-Dec-2011 Hal Finkel <hfinkel@anl.gov> remove unneeded FIXME comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
64c34e253563a8ba6b41fbce2bb020632cf65961 02-Dec-2011 Hal Finkel <hfinkel@anl.gov> update PPC 940 hazard rec. to function in postRA mode

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
c6d08f10bf797cc78068ef30bd0e8812a5bdc9a2 17-Oct-2011 Hal Finkel <hfinkel@anl.gov> Add PPC 440 scheduler and some associated tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
e837dead3c8dc3445ef6a0e2322179c57e264a13 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
0c9b559bfd0b476c2dde787285a1195f3142c423 03-Jun-2011 Roman Divacky <rdivacky@freebsd.org> Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.

- Check for MTCTR8 in addition to MTCTR when looking up a hazard.

- When lowering an indirect call use CTR8 when targeting 64bit.

- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.

The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
2da8bc8a5f7705ac131184cd247f48500da0d74e 24-Dec-2010 Andrew Trick <atrick@apple.com> Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
6e8f4c404825b79f9b9176483653f1aa927dfbde 24-Dec-2010 Andrew Trick <atrick@apple.com> whitespace


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
29d8f0cae425f1bba583565227eaebf58f26ce73 23-Dec-2010 Chris Lattner <sabre@nondot.org> flags -> glue for selectiondag


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
99405df044f2c584242e711cc9023ec90356da82 09-Jun-2010 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
1087f54ddb70bd2a7ab62608161e4a3f0c345935 05-Jun-2010 Chris Lattner <sabre@nondot.org> revert r105521, which is breaking the buildbots with stuff like this:

In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
3eca98bb3ab1ec27ab8763298c416d282cdaa261 05-Jun-2010 Bruno Cardoso Lopes <bruno.cardoso@gmail.com> Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
9fa200d2a2360412465bbd6cfb485af2e9d5b1b4 27-Feb-2010 Chris Lattner <sabre@nondot.org> remove a bogus pattern, which had the same pattern as STDU
but codegen'd differently. This really wanted to use some
sort of subreg to get the low 4 bytes of the G8RC register
or something. However, it's invalid and nothing is testing
it, so I'm just zapping the bogosity.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
f451cb870efcf9e0302d25ed05f4cac6bb494e42 10-Feb-2010 Dan Gohman <gohman@apple.com> Fix "the the" and similar typos.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
893e1c90a03a53cf13f73849324e83612688428a 23-Aug-2009 Chris Lattner <sabre@nondot.org> eliminate the last DOUTs from the targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
c23197a26f34f559ea9797de51e187087c039c42 14-Jul-2009 Torok Edwin <edwintorok@gmail.com> llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
c25e7581b9b8088910da31702d4ca21c4734c6d7 11-Jul-2009 Torok Edwin <edwintorok@gmail.com> assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
2a9ddfb903ae3baede7282348afae1f750905248 03-Jul-2009 Tilmann Scheller <tilmann.scheller@googlemail.com> Refactor ABI code in the PowerPC backend.

Make CalculateParameterAndLinkageAreaSize() Darwin-specific.
Remove SVR4 specific code from LowerCALL_Darwin() and LowerFORMAL_ARGUMENTS_Darwin().
Rename MachoABI to DarwinABI for consistency.
Rename ELF ABI to SVR4 ABI for consistency.
Factor out common call return lowering between the Darwin and SVR4 ABI.
Factor out common call lowering between the Darwin and SVR4 ABI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
2836c283bb1c14baa50994f60769d665da608ad7 16-Jan-2009 Dan Gohman <gohman@apple.com> Initial hazard recognizer support in post-pass scheduling. This includes
a new toy hazard recognizier heuristic which attempts to direct the
scheduler to avoid clumping large groups of loads or stores too densely.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
fc54c552963545a81e4ea38e60460590afb2d5ae 15-Jan-2009 Dan Gohman <gohman@apple.com> Generalize the HazardRecognizer interface so that it can be used
to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
41474baac839da410302950305722cb0e026a094 03-Dec-2008 Dan Gohman <gohman@apple.com> Add a sanity-check to tablegen to catch the case where isSimpleLoad
is set but mayLoad is not set. Fix all the problems this turned up.

Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
f5aeb1a8e4cf272c7348376d185ef8d8267653e0 12-Sep-2008 Dan Gohman <gohman@apple.com> Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
475871a144eb604ddaf37503397ba0941442e5fb 27-Jul-2008 Dan Gohman <gohman@apple.com> Rename SDOperand to SDValue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
e8be6c63915e0389f1eef6b53c64300d13b2ce99 17-Jul-2008 Dan Gohman <gohman@apple.com> Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
749c6f6b5ed301c84aac562e414486549d7b98eb 07-Jan-2008 Chris Lattner <sabre@nondot.org> rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
c17d69fa1e084668d6bb27441dbb505e2024f579 07-Jan-2008 Chris Lattner <sabre@nondot.org> use predicate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
834f1ce0312e3d00d836f9560cb63182c2c4570f 07-Jan-2008 Chris Lattner <sabre@nondot.org> rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
2e48a70b35635165703838fc8d3796b664207aa1 06-Jan-2008 Chris Lattner <sabre@nondot.org> rename isStore -> mayStore to more accurately reflect what it captures.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
4ee451de366474b9c228b4e5fa573795a715216d 29-Dec-2007 Chris Lattner <sabre@nondot.org> Remove attribution from file headers, per discussion on llvmdev.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
399ea50dc3321b4cc16e0a5ea7c41495c55a01ba 06-Sep-2007 Bill Wendling <isanbard@gmail.com> LVXL and STVXL are also a load and store resp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
e7e7d0d7e39d0c7c659d26b97e8081fce0fcd749 13-Jul-2007 Dale Johannesen <dalej@apple.com> Skeleton of post-RA scheduler; doesn't do anything yet.
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
05c180b34763c2891a2bf467c48bcf2a96f7e660 27-Feb-2007 Nicolas Geoffray <nicolas.geoffray@lip6.fr> Fix parenthesis for BCTRL_{ELF|Macho} test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34668 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
9f0bc659c8d2f1e401a9690e4900b0fd2a70bdfe 25-Feb-2007 Chris Lattner <sabre@nondot.org> implement support for the linux/ppc function call ABI. Patch by
Nicolas Geoffray!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8 07-Dec-2006 Bill Wendling <isanbard@gmail.com> What should be the last unnecessary <iostream>s in the library.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
80df01d2cf68b680b1c90eb0d3b0f2defcdf202b 16-Nov-2006 Chris Lattner <sabre@nondot.org> add ppc64 r+i stores with update.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31776 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
f8e07f448a241789ff987179d67fd7c87d844ee8 15-Nov-2006 Chris Lattner <sabre@nondot.org> Switch loads over to use memri as the operand instead of a reg/imm operand
pair for cleanliness. Add instructions for PPC32 preinc-stores with commented
out patterns. More improvement is needed to enable the patterns, but we're
getting close.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
c9dcf289557017742fb507f985b3bf9f44982031 13-Nov-2006 Chris Lattner <sabre@nondot.org> teach the g5 hazard recognizer about update loads. This fixes
Ptrdist/anagram among others.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
518f9c7ad0566a69886a4db1b76e995df22bca0f 14-Jul-2006 Chris Lattner <sabre@nondot.org> Add missing PPC64 extload/truncstores


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
d9989384592a3bd9dd374470a723ca8303071a2d 10-Jul-2006 Chris Lattner <sabre@nondot.org> Implement Regression/CodeGen/PowerPC/bswap-load-store.ll by folding bswaps
into i16/i32 load/stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
ecfe55e65b6a72fddd543c42f2e2df4c96c647ba 22-Mar-2006 Chris Lattner <sabre@nondot.org> When possible, custom lower 32-bit SINT_TO_FP to this:

_foo2:
extsw r2, r3
std r2, -8(r1)
lfd f0, -8(r1)
fcfid f0, f0
frsp f1, f0
blr

instead of this:

_foo2:
lis r2, ha16(LCPI2_0)
lis r4, 17200
xoris r3, r3, 32768
stw r3, -4(r1)
stw r4, -8(r1)
lfs f0, lo16(LCPI2_0)(r2)
lfd f1, -8(r1)
fsub f0, f1, f0
frsp f1, f0
blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
64ce964673ca5c71f46933d8699aa557fbc5f15a 13-Mar-2006 Chris Lattner <sabre@nondot.org> Fix a couple of bugs that broke the alpha tester build


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
3faad495bc5c23de4852e7a3a13c25203cabfc3e 13-Mar-2006 Chris Lattner <sabre@nondot.org> Handle cracked instructions in dispatch group formation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
88d211f82304e53694ece666d4a2507b170e4582 12-Mar-2006 Chris Lattner <sabre@nondot.org> Several big changes:
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
9c2c38674a204452eeb50f1f0e3e7d26005a8cde 11-Mar-2006 Chris Lattner <sabre@nondot.org> blr is a branch too


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26710 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
b0d21ef20c29f4ea46d21b488f17feaa6a8760e1 08-Mar-2006 Chris Lattner <sabre@nondot.org> Change the interface for getting a target HazardRecognizer to be more clean.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
b84225b080a6ad72c4eecececc0a4fdffc9455a8 07-Mar-2006 Chris Lattner <sabre@nondot.org> add another missing store.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26595 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
ab5801cb28168b22444a95dd4c3783f4eba25801 07-Mar-2006 Chris Lattner <sabre@nondot.org> add a couple more load/store instrs, add a newline to the end of file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
3acbe5d4f0d6163cb761368692c830c1a4f27e31 07-Mar-2006 Nate Begeman <natebegeman@mac.com> This kinda sorta implements "things that have to lead a dispatch group".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
2046371e70e90d4435fcdf1b2ebeb64a2e5b2626 07-Mar-2006 Chris Lattner <sabre@nondot.org> add some new instructions to the classifier. With this, we correctly insert
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
7ce64852e8fc260f8a7434217c1b57b85a70a1c8 07-Mar-2006 Chris Lattner <sabre@nondot.org> add some comments that describe what we model


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
c6644188208d4aee9a9d6c428710ec1f69837944 07-Mar-2006 Chris Lattner <sabre@nondot.org> Implement a very very simple hazard recognizer for LSU rejects and ctr set/read
flushes


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp