PPCHazardRecognizers.cpp revision 99405df044f2c584242e711cc9023ec90356da82 
1//===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements hazard recognizers for scheduling on PowerPC processors.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "pre-RA-sched"
15#include "PPCHazardRecognizers.h"
16#include "PPC.h"
17#include "PPCInstrInfo.h"
18#include "llvm/CodeGen/ScheduleDAG.h"
19#include "llvm/Support/Debug.h"
20#include "llvm/Support/ErrorHandling.h"
21#include "llvm/Support/raw_ostream.h"
22using namespace llvm;
23
24//===----------------------------------------------------------------------===//
25// PowerPC 970 Hazard Recognizer
26//
27// This models the dispatch group formation of the PPC970 processor.  Dispatch
28// groups are bundles of up to five instructions that can contain various mixes
29// of instructions.  The PPC970 can dispatch a peak of 4 non-branch and one
30// branch instruction per-cycle.
31//
32// There are a number of restrictions to dispatch group formation: some
33// instructions can only be issued in the first slot of a dispatch group, & some
34// instructions fill an entire dispatch group.  Additionally, only branches can
35// issue in the 5th (last) slot.
36//
37// Finally, there are a number of "structural" hazards on the PPC970.  These
38// conditions cause large performance penalties due to misprediction, recovery,
39// and replay logic that has to happen.  These cases include setting a CTR and
40// branching through it in the same dispatch group, and storing to an address,
41// then loading from the same address within a dispatch group.  To avoid these
42// conditions, we insert no-op instructions when appropriate.
43//
44// FIXME: This is missing some significant cases:
45//   1. Modeling of microcoded instructions.
46//   2. Handling of serialized operations.
47//   3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
48//
49
50PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
51  : TII(tii) {
52  EndDispatchGroup();
53}
54
55void PPCHazardRecognizer970::EndDispatchGroup() {
56  DEBUG(errs() << "=== Start of dispatch group\n");
57  NumIssued = 0;
58
59  // Structural hazard info.
60  HasCTRSet = false;
61  NumStores = 0;
62}
63
64
65PPCII::PPC970_Unit
66PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
67                                     bool &isFirst, bool &isSingle,
68                                     bool &isCracked,
69                                     bool &isLoad, bool &isStore) {
70  if ((int)Opcode >= 0) {
71    isFirst = isSingle = isCracked = isLoad = isStore = false;
72    return PPCII::PPC970_Pseudo;
73  }
74  Opcode = ~Opcode;
75
76  const TargetInstrDesc &TID = TII.get(Opcode);
77
78  isLoad  = TID.mayLoad();
79  isStore = TID.mayStore();
80
81  uint64_t TSFlags = TID.TSFlags;
82
83  isFirst   = TSFlags & PPCII::PPC970_First;
84  isSingle  = TSFlags & PPCII::PPC970_Single;
85  isCracked = TSFlags & PPCII::PPC970_Cracked;
86  return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
87}
88
89/// isLoadOfStoredAddress - If we have a load from the previously stored pointer
90/// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
91bool PPCHazardRecognizer970::
92isLoadOfStoredAddress(unsigned LoadSize, SDValue Ptr1, SDValue Ptr2) const {
93  for (unsigned i = 0, e = NumStores; i != e; ++i) {
94    // Handle exact and commuted addresses.
95    if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i])
96      return true;
97    if (Ptr2 == StorePtr1[i] && Ptr1 == StorePtr2[i])
98      return true;
99
100    // Okay, we don't have an exact match, if this is an indexed offset, see if
101    // we have overlap (which happens during fp->int conversion for example).
102    if (StorePtr2[i] == Ptr2) {
103      if (ConstantSDNode *StoreOffset = dyn_cast<ConstantSDNode>(StorePtr1[i]))
104        if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) {
105          // Okay the base pointers match, so we have [c1+r] vs [c2+r].  Check
106          // to see if the load and store actually overlap.
107          int StoreOffs = StoreOffset->getZExtValue();
108          int LoadOffs  = LoadOffset->getZExtValue();
109          if (StoreOffs < LoadOffs) {
110            if (int(StoreOffs+StoreSize[i]) > LoadOffs) return true;
111          } else {
112            if (int(LoadOffs+LoadSize) > StoreOffs) return true;
113          }
114        }
115    }
116  }
117  return false;
118}
119
120/// getHazardType - We return hazard for any non-branch instruction that would
121/// terminate the dispatch group.  We turn NoopHazard for any
122/// instructions that wouldn't terminate the dispatch group that would cause a
123/// pipeline flush.
124ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::
125getHazardType(SUnit *SU) {
126  const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
127  bool isFirst, isSingle, isCracked, isLoad, isStore;
128  PPCII::PPC970_Unit InstrType =
129    GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
130                 isLoad, isStore);
131  if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
132  unsigned Opcode = Node->getMachineOpcode();
133
134  // We can only issue a PPC970_First/PPC970_Single instruction (such as
135  // crand/mtspr/etc) if this is the first cycle of the dispatch group.
136  if (NumIssued != 0 && (isFirst || isSingle))
137    return Hazard;
138
139  // If this instruction is cracked into two ops by the decoder, we know that
140  // it is not a branch and that it cannot issue if 3 other instructions are
141  // already in the dispatch group.
142  if (isCracked && NumIssued > 2)
143    return Hazard;
144
145  switch (InstrType) {
146  default: llvm_unreachable("Unknown instruction type!");
147  case PPCII::PPC970_FXU:
148  case PPCII::PPC970_LSU:
149  case PPCII::PPC970_FPU:
150  case PPCII::PPC970_VALU:
151  case PPCII::PPC970_VPERM:
152    // We can only issue a branch as the last instruction in a group.
153    if (NumIssued == 4) return Hazard;
154    break;
155  case PPCII::PPC970_CRU:
156    // We can only issue a CR instruction in the first two slots.
157    if (NumIssued >= 2) return Hazard;
158    break;
159  case PPCII::PPC970_BRU:
160    break;
161  }
162
163  // Do not allow MTCTR and BCTRL to be in the same dispatch group.
164  if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4))
165    return NoopHazard;
166
167  // If this is a load following a store, make sure it's not to the same or
168  // overlapping address.
169  if (isLoad && NumStores) {
170    unsigned LoadSize;
171    switch (Opcode) {
172    default: llvm_unreachable("Unknown load!");
173    case PPC::LBZ:   case PPC::LBZU:
174    case PPC::LBZX:
175    case PPC::LBZ8:  case PPC::LBZU8:
176    case PPC::LBZX8:
177    case PPC::LVEBX:
178      LoadSize = 1;
179      break;
180    case PPC::LHA:   case PPC::LHAU:
181    case PPC::LHAX:
182    case PPC::LHZ:   case PPC::LHZU:
183    case PPC::LHZX:
184    case PPC::LVEHX:
185    case PPC::LHBRX:
186    case PPC::LHA8:   case PPC::LHAU8:
187    case PPC::LHAX8:
188    case PPC::LHZ8:   case PPC::LHZU8:
189    case PPC::LHZX8:
190      LoadSize = 2;
191      break;
192    case PPC::LFS:    case PPC::LFSU:
193    case PPC::LFSX:
194    case PPC::LWZ:    case PPC::LWZU:
195    case PPC::LWZX:
196    case PPC::LWA:
197    case PPC::LWAX:
198    case PPC::LVEWX:
199    case PPC::LWBRX:
200    case PPC::LWZ8:
201    case PPC::LWZX8:
202      LoadSize = 4;
203      break;
204    case PPC::LFD:    case PPC::LFDU:
205    case PPC::LFDX:
206    case PPC::LD:     case PPC::LDU:
207    case PPC::LDX:
208      LoadSize = 8;
209      break;
210    case PPC::LVX:
211    case PPC::LVXL:
212      LoadSize = 16;
213      break;
214    }
215
216    if (isLoadOfStoredAddress(LoadSize,
217                              Node->getOperand(0), Node->getOperand(1)))
218      return NoopHazard;
219  }
220
221  return NoHazard;
222}
223
224void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
225  const SDNode *Node = SU->getNode()->getFlaggedMachineNode();
226  bool isFirst, isSingle, isCracked, isLoad, isStore;
227  PPCII::PPC970_Unit InstrType =
228    GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked,
229                 isLoad, isStore);
230  if (InstrType == PPCII::PPC970_Pseudo) return;
231  unsigned Opcode = Node->getMachineOpcode();
232
233  // Update structural hazard information.
234  if (Opcode == PPC::MTCTR) HasCTRSet = true;
235
236  // Track the address stored to.
237  if (isStore) {
238    unsigned ThisStoreSize;
239    switch (Opcode) {
240    default: llvm_unreachable("Unknown store instruction!");
241    case PPC::STB:    case PPC::STB8:
242    case PPC::STBU:   case PPC::STBU8:
243    case PPC::STBX:   case PPC::STBX8:
244    case PPC::STVEBX:
245      ThisStoreSize = 1;
246      break;
247    case PPC::STH:    case PPC::STH8:
248    case PPC::STHU:   case PPC::STHU8:
249    case PPC::STHX:   case PPC::STHX8:
250    case PPC::STVEHX:
251    case PPC::STHBRX:
252      ThisStoreSize = 2;
253      break;
254    case PPC::STFS:
255    case PPC::STFSU:
256    case PPC::STFSX:
257    case PPC::STWX:   case PPC::STWX8:
258    case PPC::STWUX:
259    case PPC::STW:    case PPC::STW8:
260    case PPC::STWU:
261    case PPC::STVEWX:
262    case PPC::STFIWX:
263    case PPC::STWBRX:
264      ThisStoreSize = 4;
265      break;
266    case PPC::STD_32:
267    case PPC::STDX_32:
268    case PPC::STD:
269    case PPC::STDU:
270    case PPC::STFD:
271    case PPC::STFDX:
272    case PPC::STDX:
273    case PPC::STDUX:
274      ThisStoreSize = 8;
275      break;
276    case PPC::STVX:
277    case PPC::STVXL:
278      ThisStoreSize = 16;
279      break;
280    }
281
282    StoreSize[NumStores] = ThisStoreSize;
283    StorePtr1[NumStores] = Node->getOperand(1);
284    StorePtr2[NumStores] = Node->getOperand(2);
285    ++NumStores;
286  }
287
288  if (InstrType == PPCII::PPC970_BRU || isSingle)
289    NumIssued = 4;  // Terminate a d-group.
290  ++NumIssued;
291
292  // If this instruction is cracked into two ops by the decoder, remember that
293  // we issued two pieces.
294  if (isCracked)
295    ++NumIssued;
296
297  if (NumIssued == 5)
298    EndDispatchGroup();
299}
300
301void PPCHazardRecognizer970::AdvanceCycle() {
302  assert(NumIssued < 5 && "Illegal dispatch group!");
303  ++NumIssued;
304  if (NumIssued == 5)
305    EndDispatchGroup();
306}
307