PPCInstrInfo.cpp revision 6a3a1ba97e996bfdc061f9a51bd4cf4915962913 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCGenInstrInfo.inc"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Target/TargetAsmInfo.h"
24using namespace llvm;
25
26extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
27extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
28
29PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
30  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
31    RI(*TM.getSubtargetImpl(), *this) {}
32
33bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
34                               unsigned& sourceReg,
35                               unsigned& destReg,
36                               unsigned& sourceSubIdx,
37                               unsigned& destSubIdx) const {
38  sourceSubIdx = destSubIdx = 0; // No sub-registers.
39
40  unsigned oc = MI.getOpcode();
41  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
42      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
43    assert(MI.getNumOperands() >= 3 &&
44           MI.getOperand(0).isReg() &&
45           MI.getOperand(1).isReg() &&
46           MI.getOperand(2).isReg() &&
47           "invalid PPC OR instruction!");
48    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
49      sourceReg = MI.getOperand(1).getReg();
50      destReg = MI.getOperand(0).getReg();
51      return true;
52    }
53  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
54    assert(MI.getNumOperands() >= 3 &&
55           MI.getOperand(0).isReg() &&
56           MI.getOperand(2).isImm() &&
57           "invalid PPC ADDI instruction!");
58    if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
59      sourceReg = MI.getOperand(1).getReg();
60      destReg = MI.getOperand(0).getReg();
61      return true;
62    }
63  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
64    assert(MI.getNumOperands() >= 3 &&
65           MI.getOperand(0).isReg() &&
66           MI.getOperand(1).isReg() &&
67           MI.getOperand(2).isImm() &&
68           "invalid PPC ORI instruction!");
69    if (MI.getOperand(2).getImm() == 0) {
70      sourceReg = MI.getOperand(1).getReg();
71      destReg = MI.getOperand(0).getReg();
72      return true;
73    }
74  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
75             oc == PPC::FMRSD) {      // fmr r1, r2
76    assert(MI.getNumOperands() >= 2 &&
77           MI.getOperand(0).isReg() &&
78           MI.getOperand(1).isReg() &&
79           "invalid PPC FMR instruction");
80    sourceReg = MI.getOperand(1).getReg();
81    destReg = MI.getOperand(0).getReg();
82    return true;
83  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
84    assert(MI.getNumOperands() >= 2 &&
85           MI.getOperand(0).isReg() &&
86           MI.getOperand(1).isReg() &&
87           "invalid PPC MCRF instruction");
88    sourceReg = MI.getOperand(1).getReg();
89    destReg = MI.getOperand(0).getReg();
90    return true;
91  }
92  return false;
93}
94
95unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
96                                           int &FrameIndex) const {
97  switch (MI->getOpcode()) {
98  default: break;
99  case PPC::LD:
100  case PPC::LWZ:
101  case PPC::LFS:
102  case PPC::LFD:
103    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
104        MI->getOperand(2).isFI()) {
105      FrameIndex = MI->getOperand(2).getIndex();
106      return MI->getOperand(0).getReg();
107    }
108    break;
109  }
110  return 0;
111}
112
113unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
114                                          int &FrameIndex) const {
115  switch (MI->getOpcode()) {
116  default: break;
117  case PPC::STD:
118  case PPC::STW:
119  case PPC::STFS:
120  case PPC::STFD:
121    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
122        MI->getOperand(2).isFI()) {
123      FrameIndex = MI->getOperand(2).getIndex();
124      return MI->getOperand(0).getReg();
125    }
126    break;
127  }
128  return 0;
129}
130
131// commuteInstruction - We can commute rlwimi instructions, but only if the
132// rotate amt is zero.  We also have to munge the immediates a bit.
133MachineInstr *
134PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
135  MachineFunction &MF = *MI->getParent()->getParent();
136
137  // Normal instructions can be commuted the obvious way.
138  if (MI->getOpcode() != PPC::RLWIMI)
139    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
140
141  // Cannot commute if it has a non-zero rotate count.
142  if (MI->getOperand(3).getImm() != 0)
143    return 0;
144
145  // If we have a zero rotate count, we have:
146  //   M = mask(MB,ME)
147  //   Op0 = (Op1 & ~M) | (Op2 & M)
148  // Change this to:
149  //   M = mask((ME+1)&31, (MB-1)&31)
150  //   Op0 = (Op2 & ~M) | (Op1 & M)
151
152  // Swap op1/op2
153  unsigned Reg0 = MI->getOperand(0).getReg();
154  unsigned Reg1 = MI->getOperand(1).getReg();
155  unsigned Reg2 = MI->getOperand(2).getReg();
156  bool Reg1IsKill = MI->getOperand(1).isKill();
157  bool Reg2IsKill = MI->getOperand(2).isKill();
158  bool ChangeReg0 = false;
159  // If machine instrs are no longer in two-address forms, update
160  // destination register as well.
161  if (Reg0 == Reg1) {
162    // Must be two address instruction!
163    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
164           "Expecting a two-address instruction!");
165    Reg2IsKill = false;
166    ChangeReg0 = true;
167  }
168
169  // Masks.
170  unsigned MB = MI->getOperand(4).getImm();
171  unsigned ME = MI->getOperand(5).getImm();
172
173  if (NewMI) {
174    // Create a new instruction.
175    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
176    bool Reg0IsDead = MI->getOperand(0).isDead();
177    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
178      .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
179      .addReg(Reg2, getKillRegState(Reg2IsKill))
180      .addReg(Reg1, getKillRegState(Reg1IsKill))
181      .addImm((ME+1) & 31)
182      .addImm((MB-1) & 31);
183  }
184
185  if (ChangeReg0)
186    MI->getOperand(0).setReg(Reg2);
187  MI->getOperand(2).setReg(Reg1);
188  MI->getOperand(1).setReg(Reg2);
189  MI->getOperand(2).setIsKill(Reg1IsKill);
190  MI->getOperand(1).setIsKill(Reg2IsKill);
191
192  // Swap the mask around.
193  MI->getOperand(4).setImm((ME+1) & 31);
194  MI->getOperand(5).setImm((MB-1) & 31);
195  return MI;
196}
197
198void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
199                              MachineBasicBlock::iterator MI) const {
200  DebugLoc DL = DebugLoc::getUnknownLoc();
201  if (MI != MBB.end()) DL = MI->getDebugLoc();
202
203  BuildMI(MBB, MI, DL, get(PPC::NOP));
204}
205
206
207// Branch analysis.
208bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
209                                 MachineBasicBlock *&FBB,
210                                 SmallVectorImpl<MachineOperand> &Cond,
211                                 bool AllowModify) const {
212  // If the block has no terminators, it just falls into the block after it.
213  MachineBasicBlock::iterator I = MBB.end();
214  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
215    return false;
216
217  // Get the last instruction in the block.
218  MachineInstr *LastInst = I;
219
220  // If there is only one terminator instruction, process it.
221  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
222    if (LastInst->getOpcode() == PPC::B) {
223      if (!LastInst->getOperand(0).isMBB())
224        return true;
225      TBB = LastInst->getOperand(0).getMBB();
226      return false;
227    } else if (LastInst->getOpcode() == PPC::BCC) {
228      if (!LastInst->getOperand(2).isMBB())
229        return true;
230      // Block ends with fall-through condbranch.
231      TBB = LastInst->getOperand(2).getMBB();
232      Cond.push_back(LastInst->getOperand(0));
233      Cond.push_back(LastInst->getOperand(1));
234      return false;
235    }
236    // Otherwise, don't know what this is.
237    return true;
238  }
239
240  // Get the instruction before it if it's a terminator.
241  MachineInstr *SecondLastInst = I;
242
243  // If there are three terminators, we don't know what sort of block this is.
244  if (SecondLastInst && I != MBB.begin() &&
245      isUnpredicatedTerminator(--I))
246    return true;
247
248  // If the block ends with PPC::B and PPC:BCC, handle it.
249  if (SecondLastInst->getOpcode() == PPC::BCC &&
250      LastInst->getOpcode() == PPC::B) {
251    if (!SecondLastInst->getOperand(2).isMBB() ||
252        !LastInst->getOperand(0).isMBB())
253      return true;
254    TBB =  SecondLastInst->getOperand(2).getMBB();
255    Cond.push_back(SecondLastInst->getOperand(0));
256    Cond.push_back(SecondLastInst->getOperand(1));
257    FBB = LastInst->getOperand(0).getMBB();
258    return false;
259  }
260
261  // If the block ends with two PPC:Bs, handle it.  The second one is not
262  // executed, so remove it.
263  if (SecondLastInst->getOpcode() == PPC::B &&
264      LastInst->getOpcode() == PPC::B) {
265    if (!SecondLastInst->getOperand(0).isMBB())
266      return true;
267    TBB = SecondLastInst->getOperand(0).getMBB();
268    I = LastInst;
269    if (AllowModify)
270      I->eraseFromParent();
271    return false;
272  }
273
274  // Otherwise, can't handle this.
275  return true;
276}
277
278unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
279  MachineBasicBlock::iterator I = MBB.end();
280  if (I == MBB.begin()) return 0;
281  --I;
282  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
283    return 0;
284
285  // Remove the branch.
286  I->eraseFromParent();
287
288  I = MBB.end();
289
290  if (I == MBB.begin()) return 1;
291  --I;
292  if (I->getOpcode() != PPC::BCC)
293    return 1;
294
295  // Remove the branch.
296  I->eraseFromParent();
297  return 2;
298}
299
300unsigned
301PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
302                           MachineBasicBlock *FBB,
303                           const SmallVectorImpl<MachineOperand> &Cond) const {
304  // FIXME this should probably have a DebugLoc argument
305  DebugLoc dl = DebugLoc::getUnknownLoc();
306  // Shouldn't be a fall through.
307  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
308  assert((Cond.size() == 2 || Cond.size() == 0) &&
309         "PPC branch conditions have two components!");
310
311  // One-way branch.
312  if (FBB == 0) {
313    if (Cond.empty())   // Unconditional branch
314      BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB);
315    else                // Conditional branch
316      BuildMI(&MBB, dl, get(PPC::BCC))
317        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
318    return 1;
319  }
320
321  // Two-way Conditional Branch.
322  BuildMI(&MBB, dl, get(PPC::BCC))
323    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
324  BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB);
325  return 2;
326}
327
328bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
329                                   MachineBasicBlock::iterator MI,
330                                   unsigned DestReg, unsigned SrcReg,
331                                   const TargetRegisterClass *DestRC,
332                                   const TargetRegisterClass *SrcRC) const {
333  if (DestRC != SrcRC) {
334    // Not yet supported!
335    return false;
336  }
337
338  DebugLoc DL = DebugLoc::getUnknownLoc();
339  if (MI != MBB.end()) DL = MI->getDebugLoc();
340
341  if (DestRC == PPC::GPRCRegisterClass) {
342    BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
343  } else if (DestRC == PPC::G8RCRegisterClass) {
344    BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
345  } else if (DestRC == PPC::F4RCRegisterClass) {
346    BuildMI(MBB, MI, DL, get(PPC::FMRS), DestReg).addReg(SrcReg);
347  } else if (DestRC == PPC::F8RCRegisterClass) {
348    BuildMI(MBB, MI, DL, get(PPC::FMRD), DestReg).addReg(SrcReg);
349  } else if (DestRC == PPC::CRRCRegisterClass) {
350    BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
351  } else if (DestRC == PPC::VRRCRegisterClass) {
352    BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
353  } else if (DestRC == PPC::CRBITRCRegisterClass) {
354    BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
355  } else {
356    // Attempt to copy register that is not GPR or FPR
357    return false;
358  }
359
360  return true;
361}
362
363bool
364PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
365                                  unsigned SrcReg, bool isKill,
366                                  int FrameIdx,
367                                  const TargetRegisterClass *RC,
368                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
369  DebugLoc DL = DebugLoc::getUnknownLoc();
370  if (RC == PPC::GPRCRegisterClass) {
371    if (SrcReg != PPC::LR) {
372      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
373                                         .addReg(SrcReg,
374                                                 getKillRegState(isKill)),
375                                         FrameIdx));
376    } else {
377      // FIXME: this spills LR immediately to memory in one step.  To do this,
378      // we use R11, which we know cannot be used in the prolog/epilog.  This is
379      // a hack.
380      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
381      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
382                                         .addReg(PPC::R11,
383                                                 getKillRegState(isKill)),
384                                         FrameIdx));
385    }
386  } else if (RC == PPC::G8RCRegisterClass) {
387    if (SrcReg != PPC::LR8) {
388      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
389                                         .addReg(SrcReg,
390                                                 getKillRegState(isKill)),
391                                         FrameIdx));
392    } else {
393      // FIXME: this spills LR immediately to memory in one step.  To do this,
394      // we use R11, which we know cannot be used in the prolog/epilog.  This is
395      // a hack.
396      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
397      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
398                                         .addReg(PPC::X11,
399                                                 getKillRegState(isKill)),
400                                         FrameIdx));
401    }
402  } else if (RC == PPC::F8RCRegisterClass) {
403    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
404                                       .addReg(SrcReg,
405                                               getKillRegState(isKill)),
406                                       FrameIdx));
407  } else if (RC == PPC::F4RCRegisterClass) {
408    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
409                                       .addReg(SrcReg,
410                                               getKillRegState(isKill)),
411                                       FrameIdx));
412  } else if (RC == PPC::CRRCRegisterClass) {
413    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
414        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
415      // FIXME (64-bit): Enable
416      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
417                                         .addReg(SrcReg,
418                                                 getKillRegState(isKill)),
419                                         FrameIdx));
420      return true;
421    } else {
422      // FIXME: We use R0 here, because it isn't available for RA.  We need to
423      // store the CR in the low 4-bits of the saved value.  First, issue a MFCR
424      // to save all of the CRBits.
425      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), PPC::R0));
426
427      // If the saved register wasn't CR0, shift the bits left so that they are
428      // in CR0's slot.
429      if (SrcReg != PPC::CR0) {
430        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
431        // rlwinm r0, r0, ShiftBits, 0, 31.
432        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
433                       .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
434      }
435
436      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
437                                         .addReg(PPC::R0,
438                                                 getKillRegState(isKill)),
439                                         FrameIdx));
440    }
441  } else if (RC == PPC::CRBITRCRegisterClass) {
442    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
443    // backend currently only uses CR1EQ as an individual bit, this should
444    // not cause any bug. If we need other uses of CR bits, the following
445    // code may be invalid.
446    unsigned Reg = 0;
447    if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
448        SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
449      Reg = PPC::CR0;
450    else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
451             SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
452      Reg = PPC::CR1;
453    else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
454             SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
455      Reg = PPC::CR2;
456    else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
457             SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
458      Reg = PPC::CR3;
459    else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
460             SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
461      Reg = PPC::CR4;
462    else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
463             SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
464      Reg = PPC::CR5;
465    else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
466             SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
467      Reg = PPC::CR6;
468    else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
469             SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
470      Reg = PPC::CR7;
471
472    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
473                               PPC::CRRCRegisterClass, NewMIs);
474
475  } else if (RC == PPC::VRRCRegisterClass) {
476    // We don't have indexed addressing for vector loads.  Emit:
477    // R0 = ADDI FI#
478    // STVX VAL, 0, R0
479    //
480    // FIXME: We use R0 here, because it isn't available for RA.
481    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
482                                       FrameIdx, 0, 0));
483    NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
484                     .addReg(SrcReg, getKillRegState(isKill))
485                     .addReg(PPC::R0)
486                     .addReg(PPC::R0));
487  } else {
488    assert(0 && "Unknown regclass!");
489    abort();
490  }
491
492  return false;
493}
494
495void
496PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
497                                  MachineBasicBlock::iterator MI,
498                                  unsigned SrcReg, bool isKill, int FrameIdx,
499                                  const TargetRegisterClass *RC) const {
500  MachineFunction &MF = *MBB.getParent();
501  SmallVector<MachineInstr*, 4> NewMIs;
502
503  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
504    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
505    FuncInfo->setSpillsCR();
506  }
507
508  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
509    MBB.insert(MI, NewMIs[i]);
510}
511
512void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
513                                  bool isKill,
514                                  SmallVectorImpl<MachineOperand> &Addr,
515                                  const TargetRegisterClass *RC,
516                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
517  if (Addr[0].isFI()) {
518    if (StoreRegToStackSlot(MF, SrcReg, isKill,
519                            Addr[0].getIndex(), RC, NewMIs)) {
520      PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
521      FuncInfo->setSpillsCR();
522    }
523
524    return;
525  }
526
527  DebugLoc DL = DebugLoc::getUnknownLoc();
528  unsigned Opc = 0;
529  if (RC == PPC::GPRCRegisterClass) {
530    Opc = PPC::STW;
531  } else if (RC == PPC::G8RCRegisterClass) {
532    Opc = PPC::STD;
533  } else if (RC == PPC::F8RCRegisterClass) {
534    Opc = PPC::STFD;
535  } else if (RC == PPC::F4RCRegisterClass) {
536    Opc = PPC::STFS;
537  } else if (RC == PPC::VRRCRegisterClass) {
538    Opc = PPC::STVX;
539  } else {
540    assert(0 && "Unknown regclass!");
541    abort();
542  }
543  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
544    .addReg(SrcReg, getKillRegState(isKill));
545  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
546    MIB.addOperand(Addr[i]);
547  NewMIs.push_back(MIB);
548  return;
549}
550
551void
552PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
553                                   unsigned DestReg, int FrameIdx,
554                                   const TargetRegisterClass *RC,
555                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
556  if (RC == PPC::GPRCRegisterClass) {
557    if (DestReg != PPC::LR) {
558      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
559                                                 DestReg), FrameIdx));
560    } else {
561      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
562                                                 PPC::R11), FrameIdx));
563      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
564    }
565  } else if (RC == PPC::G8RCRegisterClass) {
566    if (DestReg != PPC::LR8) {
567      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
568                                         FrameIdx));
569    } else {
570      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
571                                                 PPC::R11), FrameIdx));
572      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
573    }
574  } else if (RC == PPC::F8RCRegisterClass) {
575    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
576                                       FrameIdx));
577  } else if (RC == PPC::F4RCRegisterClass) {
578    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
579                                       FrameIdx));
580  } else if (RC == PPC::CRRCRegisterClass) {
581    // FIXME: We use R0 here, because it isn't available for RA.
582    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), PPC::R0),
583                                       FrameIdx));
584
585    // If the reloaded register isn't CR0, shift the bits right so that they are
586    // in the right CR's slot.
587    if (DestReg != PPC::CR0) {
588      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
589      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
590      NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), PPC::R0)
591                    .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
592    }
593
594    NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
595  } else if (RC == PPC::CRBITRCRegisterClass) {
596
597    unsigned Reg = 0;
598    if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
599        DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
600      Reg = PPC::CR0;
601    else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
602             DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
603      Reg = PPC::CR1;
604    else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
605             DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
606      Reg = PPC::CR2;
607    else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
608             DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
609      Reg = PPC::CR3;
610    else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
611             DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
612      Reg = PPC::CR4;
613    else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
614             DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
615      Reg = PPC::CR5;
616    else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
617             DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
618      Reg = PPC::CR6;
619    else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
620             DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
621      Reg = PPC::CR7;
622
623    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
624                                PPC::CRRCRegisterClass, NewMIs);
625
626  } else if (RC == PPC::VRRCRegisterClass) {
627    // We don't have indexed addressing for vector loads.  Emit:
628    // R0 = ADDI FI#
629    // Dest = LVX 0, R0
630    //
631    // FIXME: We use R0 here, because it isn't available for RA.
632    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
633                                       FrameIdx, 0, 0));
634    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
635                     .addReg(PPC::R0));
636  } else {
637    assert(0 && "Unknown regclass!");
638    abort();
639  }
640}
641
642void
643PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
644                                   MachineBasicBlock::iterator MI,
645                                   unsigned DestReg, int FrameIdx,
646                                   const TargetRegisterClass *RC) const {
647  MachineFunction &MF = *MBB.getParent();
648  SmallVector<MachineInstr*, 4> NewMIs;
649  DebugLoc DL = DebugLoc::getUnknownLoc();
650  if (MI != MBB.end()) DL = MI->getDebugLoc();
651  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
652  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
653    MBB.insert(MI, NewMIs[i]);
654}
655
656void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
657                                   SmallVectorImpl<MachineOperand> &Addr,
658                                   const TargetRegisterClass *RC,
659                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
660  if (Addr[0].isFI()) {
661    LoadRegFromStackSlot(MF, DebugLoc::getUnknownLoc(),
662                         DestReg, Addr[0].getIndex(), RC, NewMIs);
663    return;
664  }
665
666  unsigned Opc = 0;
667  if (RC == PPC::GPRCRegisterClass) {
668    assert(DestReg != PPC::LR && "Can't handle this yet!");
669    Opc = PPC::LWZ;
670  } else if (RC == PPC::G8RCRegisterClass) {
671    assert(DestReg != PPC::LR8 && "Can't handle this yet!");
672    Opc = PPC::LD;
673  } else if (RC == PPC::F8RCRegisterClass) {
674    Opc = PPC::LFD;
675  } else if (RC == PPC::F4RCRegisterClass) {
676    Opc = PPC::LFS;
677  } else if (RC == PPC::VRRCRegisterClass) {
678    Opc = PPC::LVX;
679  } else {
680    assert(0 && "Unknown regclass!");
681    abort();
682  }
683  DebugLoc DL = DebugLoc::getUnknownLoc();
684  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
685  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
686    MIB.addOperand(Addr[i]);
687  NewMIs.push_back(MIB);
688  return;
689}
690
691/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
692/// copy instructions, turning them into load/store instructions.
693MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
694                                                  MachineInstr *MI,
695                                           const SmallVectorImpl<unsigned> &Ops,
696                                                  int FrameIndex) const {
697  if (Ops.size() != 1) return NULL;
698
699  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
700  // it takes more than one instruction to store it.
701  unsigned Opc = MI->getOpcode();
702  unsigned OpNum = Ops[0];
703
704  MachineInstr *NewMI = NULL;
705  if ((Opc == PPC::OR &&
706       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
707    if (OpNum == 0) {  // move -> store
708      unsigned InReg = MI->getOperand(1).getReg();
709      bool isKill = MI->getOperand(1).isKill();
710      bool isUndef = MI->getOperand(1).isUndef();
711      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
712                                .addReg(InReg,
713                                        getKillRegState(isKill) |
714                                        getUndefRegState(isUndef)),
715                                FrameIndex);
716    } else {           // move -> load
717      unsigned OutReg = MI->getOperand(0).getReg();
718      bool isDead = MI->getOperand(0).isDead();
719      bool isUndef = MI->getOperand(0).isUndef();
720      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
721                                .addReg(OutReg,
722                                        RegState::Define |
723                                        getDeadRegState(isDead) |
724                                        getUndefRegState(isUndef)),
725                                FrameIndex);
726    }
727  } else if ((Opc == PPC::OR8 &&
728              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
729    if (OpNum == 0) {  // move -> store
730      unsigned InReg = MI->getOperand(1).getReg();
731      bool isKill = MI->getOperand(1).isKill();
732      bool isUndef = MI->getOperand(1).isUndef();
733      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
734                                .addReg(InReg,
735                                        getKillRegState(isKill) |
736                                        getUndefRegState(isUndef)),
737                                FrameIndex);
738    } else {           // move -> load
739      unsigned OutReg = MI->getOperand(0).getReg();
740      bool isDead = MI->getOperand(0).isDead();
741      bool isUndef = MI->getOperand(0).isUndef();
742      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
743                                .addReg(OutReg,
744                                        RegState::Define |
745                                        getDeadRegState(isDead) |
746                                        getUndefRegState(isUndef)),
747                                FrameIndex);
748    }
749  } else if (Opc == PPC::FMRD) {
750    if (OpNum == 0) {  // move -> store
751      unsigned InReg = MI->getOperand(1).getReg();
752      bool isKill = MI->getOperand(1).isKill();
753      bool isUndef = MI->getOperand(1).isUndef();
754      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD))
755                                .addReg(InReg,
756                                        getKillRegState(isKill) |
757                                        getUndefRegState(isUndef)),
758                                FrameIndex);
759    } else {           // move -> load
760      unsigned OutReg = MI->getOperand(0).getReg();
761      bool isDead = MI->getOperand(0).isDead();
762      bool isUndef = MI->getOperand(0).isUndef();
763      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD))
764                                .addReg(OutReg,
765                                        RegState::Define |
766                                        getDeadRegState(isDead) |
767                                        getUndefRegState(isUndef)),
768                                FrameIndex);
769    }
770  } else if (Opc == PPC::FMRS) {
771    if (OpNum == 0) {  // move -> store
772      unsigned InReg = MI->getOperand(1).getReg();
773      bool isKill = MI->getOperand(1).isKill();
774      bool isUndef = MI->getOperand(1).isUndef();
775      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS))
776                                .addReg(InReg,
777                                        getKillRegState(isKill) |
778                                        getUndefRegState(isUndef)),
779                                FrameIndex);
780    } else {           // move -> load
781      unsigned OutReg = MI->getOperand(0).getReg();
782      bool isDead = MI->getOperand(0).isDead();
783      bool isUndef = MI->getOperand(0).isUndef();
784      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS))
785                                .addReg(OutReg,
786                                        RegState::Define |
787                                        getDeadRegState(isDead) |
788                                        getUndefRegState(isUndef)),
789                                FrameIndex);
790    }
791  }
792
793  return NewMI;
794}
795
796bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
797                                  const SmallVectorImpl<unsigned> &Ops) const {
798  if (Ops.size() != 1) return false;
799
800  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
801  // it takes more than one instruction to store it.
802  unsigned Opc = MI->getOpcode();
803
804  if ((Opc == PPC::OR &&
805       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
806    return true;
807  else if ((Opc == PPC::OR8 &&
808              MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
809    return true;
810  else if (Opc == PPC::FMRD || Opc == PPC::FMRS)
811    return true;
812
813  return false;
814}
815
816
817bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
818  if (MBB.empty()) return false;
819
820  switch (MBB.back().getOpcode()) {
821  case PPC::BLR:   // Return.
822  case PPC::B:     // Uncond branch.
823  case PPC::BCTR:  // Indirect branch.
824    return true;
825  default: return false;
826  }
827}
828
829bool PPCInstrInfo::
830ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
831  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
832  // Leave the CR# the same, but invert the condition.
833  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
834  return false;
835}
836
837/// GetInstSize - Return the number of bytes of code the specified
838/// instruction may be.  This returns the maximum number of bytes.
839///
840unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
841  switch (MI->getOpcode()) {
842  case PPC::INLINEASM: {       // Inline Asm: Variable size.
843    const MachineFunction *MF = MI->getParent()->getParent();
844    const char *AsmStr = MI->getOperand(0).getSymbolName();
845    return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
846  }
847  case PPC::DBG_LABEL:
848  case PPC::EH_LABEL:
849  case PPC::GC_LABEL:
850    return 0;
851  default:
852    return 4; // PowerPC instructions are all 4 bytes
853  }
854}
855