PPCInstrInfo.cpp revision b410dc99774d52b4491750dab10b91cca1d661d8 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCGenInstrInfo.inc"
16#include "PPCTargetMachine.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include <iostream>
19using namespace llvm;
20
21PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
22  : TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm) {}
23
24/// getPointerRegClass - Return the register class to use to hold pointers.
25/// This is used for addressing modes.
26const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
27  if (TM.getSubtargetImpl()->isPPC64())
28    return &PPC::G8RCRegClass;
29  else
30    return &PPC::GPRCRegClass;
31}
32
33
34bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
35                               unsigned& sourceReg,
36                               unsigned& destReg) const {
37  MachineOpCode oc = MI.getOpcode();
38  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
39      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
40    assert(MI.getNumOperands() == 3 &&
41           MI.getOperand(0).isRegister() &&
42           MI.getOperand(1).isRegister() &&
43           MI.getOperand(2).isRegister() &&
44           "invalid PPC OR instruction!");
45    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
46      sourceReg = MI.getOperand(1).getReg();
47      destReg = MI.getOperand(0).getReg();
48      return true;
49    }
50  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
51    assert(MI.getNumOperands() == 3 &&
52           MI.getOperand(0).isRegister() &&
53           MI.getOperand(2).isImmediate() &&
54           "invalid PPC ADDI instruction!");
55    if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
56      sourceReg = MI.getOperand(1).getReg();
57      destReg = MI.getOperand(0).getReg();
58      return true;
59    }
60  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
61    assert(MI.getNumOperands() == 3 &&
62           MI.getOperand(0).isRegister() &&
63           MI.getOperand(1).isRegister() &&
64           MI.getOperand(2).isImmediate() &&
65           "invalid PPC ORI instruction!");
66    if (MI.getOperand(2).getImmedValue()==0) {
67      sourceReg = MI.getOperand(1).getReg();
68      destReg = MI.getOperand(0).getReg();
69      return true;
70    }
71  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
72             oc == PPC::FMRSD) {      // fmr r1, r2
73    assert(MI.getNumOperands() == 2 &&
74           MI.getOperand(0).isRegister() &&
75           MI.getOperand(1).isRegister() &&
76           "invalid PPC FMR instruction");
77    sourceReg = MI.getOperand(1).getReg();
78    destReg = MI.getOperand(0).getReg();
79    return true;
80  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
81    assert(MI.getNumOperands() == 2 &&
82           MI.getOperand(0).isRegister() &&
83           MI.getOperand(1).isRegister() &&
84           "invalid PPC MCRF instruction");
85    sourceReg = MI.getOperand(1).getReg();
86    destReg = MI.getOperand(0).getReg();
87    return true;
88  }
89  return false;
90}
91
92unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
93                                           int &FrameIndex) const {
94  switch (MI->getOpcode()) {
95  default: break;
96  case PPC::LD:
97  case PPC::LWZ:
98  case PPC::LFS:
99  case PPC::LFD:
100    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
101        MI->getOperand(2).isFrameIndex()) {
102      FrameIndex = MI->getOperand(2).getFrameIndex();
103      return MI->getOperand(0).getReg();
104    }
105    break;
106  }
107  return 0;
108}
109
110unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
111                                          int &FrameIndex) const {
112  switch (MI->getOpcode()) {
113  default: break;
114  case PPC::STD:
115  case PPC::STW:
116  case PPC::STFS:
117  case PPC::STFD:
118    if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
119        MI->getOperand(2).isFrameIndex()) {
120      FrameIndex = MI->getOperand(2).getFrameIndex();
121      return MI->getOperand(0).getReg();
122    }
123    break;
124  }
125  return 0;
126}
127
128// commuteInstruction - We can commute rlwimi instructions, but only if the
129// rotate amt is zero.  We also have to munge the immediates a bit.
130MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
131  // Normal instructions can be commuted the obvious way.
132  if (MI->getOpcode() != PPC::RLWIMI)
133    return TargetInstrInfo::commuteInstruction(MI);
134
135  // Cannot commute if it has a non-zero rotate count.
136  if (MI->getOperand(3).getImmedValue() != 0)
137    return 0;
138
139  // If we have a zero rotate count, we have:
140  //   M = mask(MB,ME)
141  //   Op0 = (Op1 & ~M) | (Op2 & M)
142  // Change this to:
143  //   M = mask((ME+1)&31, (MB-1)&31)
144  //   Op0 = (Op2 & ~M) | (Op1 & M)
145
146  // Swap op1/op2
147  unsigned Reg1 = MI->getOperand(1).getReg();
148  unsigned Reg2 = MI->getOperand(2).getReg();
149  MI->getOperand(2).setReg(Reg1);
150  MI->getOperand(1).setReg(Reg2);
151
152  // Swap the mask around.
153  unsigned MB = MI->getOperand(4).getImmedValue();
154  unsigned ME = MI->getOperand(5).getImmedValue();
155  MI->getOperand(4).setImmedValue((ME+1) & 31);
156  MI->getOperand(5).setImmedValue((MB-1) & 31);
157  return MI;
158}
159
160void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
161                              MachineBasicBlock::iterator MI) const {
162  BuildMI(MBB, MI, PPC::NOP, 0);
163}
164