1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "SparcISelLowering.h"
16#include "MCTargetDesc/SparcMCExpr.h"
17#include "SparcMachineFunctionInfo.h"
18#include "SparcRegisterInfo.h"
19#include "SparcTargetMachine.h"
20#include "SparcTargetObjectFile.h"
21#include "llvm/ADT/StringSwitch.h"
22#include "llvm/CodeGen/CallingConvLower.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/CodeGen/SelectionDAG.h"
28#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29#include "llvm/IR/DerivedTypes.h"
30#include "llvm/IR/Function.h"
31#include "llvm/IR/Module.h"
32#include "llvm/Support/ErrorHandling.h"
33using namespace llvm;
34
35//===----------------------------------------------------------------------===//
36// Calling Convention Implementation
37//===----------------------------------------------------------------------===//
38
39static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
40                                 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
41                                 ISD::ArgFlagsTy &ArgFlags, CCState &State)
42{
43  assert (ArgFlags.isSRet());
44
45  // Assign SRet argument.
46  State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
47                                         0,
48                                         LocVT, LocInfo));
49  return true;
50}
51
52static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
53                                     MVT &LocVT, CCValAssign::LocInfo &LocInfo,
54                                     ISD::ArgFlagsTy &ArgFlags, CCState &State)
55{
56  static const MCPhysReg RegList[] = {
57    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
58  };
59  // Try to get first reg.
60  if (unsigned Reg = State.AllocateReg(RegList)) {
61    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
62  } else {
63    // Assign whole thing in stack.
64    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
65                                           State.AllocateStack(8,4),
66                                           LocVT, LocInfo));
67    return true;
68  }
69
70  // Try to get second reg.
71  if (unsigned Reg = State.AllocateReg(RegList))
72    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
73  else
74    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
75                                           State.AllocateStack(4,4),
76                                           LocVT, LocInfo));
77  return true;
78}
79
80static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
81                                         MVT &LocVT, CCValAssign::LocInfo &LocInfo,
82                                         ISD::ArgFlagsTy &ArgFlags, CCState &State)
83{
84  static const MCPhysReg RegList[] = {
85    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
86  };
87
88  // Try to get first reg.
89  if (unsigned Reg = State.AllocateReg(RegList))
90    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
91  else
92    return false;
93
94  // Try to get second reg.
95  if (unsigned Reg = State.AllocateReg(RegList))
96    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
97  else
98    return false;
99
100  return true;
101}
102
103// Allocate a full-sized argument for the 64-bit ABI.
104static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
105                            MVT &LocVT, CCValAssign::LocInfo &LocInfo,
106                            ISD::ArgFlagsTy &ArgFlags, CCState &State) {
107  assert((LocVT == MVT::f32 || LocVT == MVT::f128
108          || LocVT.getSizeInBits() == 64) &&
109         "Can't handle non-64 bits locations");
110
111  // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
112  unsigned size      = (LocVT == MVT::f128) ? 16 : 8;
113  unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
114  unsigned Offset = State.AllocateStack(size, alignment);
115  unsigned Reg = 0;
116
117  if (LocVT == MVT::i64 && Offset < 6*8)
118    // Promote integers to %i0-%i5.
119    Reg = SP::I0 + Offset/8;
120  else if (LocVT == MVT::f64 && Offset < 16*8)
121    // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
122    Reg = SP::D0 + Offset/8;
123  else if (LocVT == MVT::f32 && Offset < 16*8)
124    // Promote floats to %f1, %f3, ...
125    Reg = SP::F1 + Offset/4;
126  else if (LocVT == MVT::f128 && Offset < 16*8)
127    // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
128    Reg = SP::Q0 + Offset/16;
129
130  // Promote to register when possible, otherwise use the stack slot.
131  if (Reg) {
132    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
133    return true;
134  }
135
136  // This argument goes on the stack in an 8-byte slot.
137  // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
138  // the right-aligned float. The first 4 bytes of the stack slot are undefined.
139  if (LocVT == MVT::f32)
140    Offset += 4;
141
142  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
143  return true;
144}
145
146// Allocate a half-sized argument for the 64-bit ABI.
147//
148// This is used when passing { float, int } structs by value in registers.
149static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
150                            MVT &LocVT, CCValAssign::LocInfo &LocInfo,
151                            ISD::ArgFlagsTy &ArgFlags, CCState &State) {
152  assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
153  unsigned Offset = State.AllocateStack(4, 4);
154
155  if (LocVT == MVT::f32 && Offset < 16*8) {
156    // Promote floats to %f0-%f31.
157    State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
158                                     LocVT, LocInfo));
159    return true;
160  }
161
162  if (LocVT == MVT::i32 && Offset < 6*8) {
163    // Promote integers to %i0-%i5, using half the register.
164    unsigned Reg = SP::I0 + Offset/8;
165    LocVT = MVT::i64;
166    LocInfo = CCValAssign::AExt;
167
168    // Set the Custom bit if this i32 goes in the high bits of a register.
169    if (Offset % 8 == 0)
170      State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
171                                             LocVT, LocInfo));
172    else
173      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
174    return true;
175  }
176
177  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
178  return true;
179}
180
181#include "SparcGenCallingConv.inc"
182
183// The calling conventions in SparcCallingConv.td are described in terms of the
184// callee's register window. This function translates registers to the
185// corresponding caller window %o register.
186static unsigned toCallerWindow(unsigned Reg) {
187  static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
188                "Unexpected enum");
189  if (Reg >= SP::I0 && Reg <= SP::I7)
190    return Reg - SP::I0 + SP::O0;
191  return Reg;
192}
193
194SDValue
195SparcTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
196                                 bool IsVarArg,
197                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
198                                 const SmallVectorImpl<SDValue> &OutVals,
199                                 const SDLoc &DL, SelectionDAG &DAG) const {
200  if (Subtarget->is64Bit())
201    return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
202  return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
203}
204
205SDValue
206SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
207                                    bool IsVarArg,
208                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
209                                    const SmallVectorImpl<SDValue> &OutVals,
210                                    const SDLoc &DL, SelectionDAG &DAG) const {
211  MachineFunction &MF = DAG.getMachineFunction();
212
213  // CCValAssign - represent the assignment of the return value to locations.
214  SmallVector<CCValAssign, 16> RVLocs;
215
216  // CCState - Info about the registers and stack slot.
217  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
218                 *DAG.getContext());
219
220  // Analyze return values.
221  CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
222
223  SDValue Flag;
224  SmallVector<SDValue, 4> RetOps(1, Chain);
225  // Make room for the return address offset.
226  RetOps.push_back(SDValue());
227
228  // Copy the result values into the output registers.
229  for (unsigned i = 0, realRVLocIdx = 0;
230       i != RVLocs.size();
231       ++i, ++realRVLocIdx) {
232    CCValAssign &VA = RVLocs[i];
233    assert(VA.isRegLoc() && "Can only return in registers!");
234
235    SDValue Arg = OutVals[realRVLocIdx];
236
237    if (VA.needsCustom()) {
238      assert(VA.getLocVT() == MVT::v2i32);
239      // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
240      // happen by default if this wasn't a legal type)
241
242      SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
243                                  Arg,
244                                  DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout())));
245      SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
246                                  Arg,
247                                  DAG.getConstant(1, DL, getVectorIdxTy(DAG.getDataLayout())));
248
249      Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag);
250      Flag = Chain.getValue(1);
251      RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
252      VA = RVLocs[++i]; // skip ahead to next loc
253      Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1,
254                               Flag);
255    } else
256      Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
257
258    // Guarantee that all emitted copies are stuck together with flags.
259    Flag = Chain.getValue(1);
260    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
261  }
262
263  unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
264  // If the function returns a struct, copy the SRetReturnReg to I0
265  if (MF.getFunction()->hasStructRetAttr()) {
266    SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
267    unsigned Reg = SFI->getSRetReturnReg();
268    if (!Reg)
269      llvm_unreachable("sret virtual register not created in the entry block");
270    auto PtrVT = getPointerTy(DAG.getDataLayout());
271    SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, PtrVT);
272    Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
273    Flag = Chain.getValue(1);
274    RetOps.push_back(DAG.getRegister(SP::I0, PtrVT));
275    RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
276  }
277
278  RetOps[0] = Chain;  // Update chain.
279  RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32);
280
281  // Add the flag if we have it.
282  if (Flag.getNode())
283    RetOps.push_back(Flag);
284
285  return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
286}
287
288// Lower return values for the 64-bit ABI.
289// Return values are passed the exactly the same way as function arguments.
290SDValue
291SparcTargetLowering::LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
292                                    bool IsVarArg,
293                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
294                                    const SmallVectorImpl<SDValue> &OutVals,
295                                    const SDLoc &DL, SelectionDAG &DAG) const {
296  // CCValAssign - represent the assignment of the return value to locations.
297  SmallVector<CCValAssign, 16> RVLocs;
298
299  // CCState - Info about the registers and stack slot.
300  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
301                 *DAG.getContext());
302
303  // Analyze return values.
304  CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
305
306  SDValue Flag;
307  SmallVector<SDValue, 4> RetOps(1, Chain);
308
309  // The second operand on the return instruction is the return address offset.
310  // The return address is always %i7+8 with the 64-bit ABI.
311  RetOps.push_back(DAG.getConstant(8, DL, MVT::i32));
312
313  // Copy the result values into the output registers.
314  for (unsigned i = 0; i != RVLocs.size(); ++i) {
315    CCValAssign &VA = RVLocs[i];
316    assert(VA.isRegLoc() && "Can only return in registers!");
317    SDValue OutVal = OutVals[i];
318
319    // Integer return values must be sign or zero extended by the callee.
320    switch (VA.getLocInfo()) {
321    case CCValAssign::Full: break;
322    case CCValAssign::SExt:
323      OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
324      break;
325    case CCValAssign::ZExt:
326      OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
327      break;
328    case CCValAssign::AExt:
329      OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
330      break;
331    default:
332      llvm_unreachable("Unknown loc info!");
333    }
334
335    // The custom bit on an i32 return value indicates that it should be passed
336    // in the high bits of the register.
337    if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
338      OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
339                           DAG.getConstant(32, DL, MVT::i32));
340
341      // The next value may go in the low bits of the same register.
342      // Handle both at once.
343      if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
344        SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
345        OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
346        // Skip the next value, it's already done.
347        ++i;
348      }
349    }
350
351    Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
352
353    // Guarantee that all emitted copies are stuck together with flags.
354    Flag = Chain.getValue(1);
355    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
356  }
357
358  RetOps[0] = Chain;  // Update chain.
359
360  // Add the flag if we have it.
361  if (Flag.getNode())
362    RetOps.push_back(Flag);
363
364  return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
365}
366
367SDValue SparcTargetLowering::LowerFormalArguments(
368    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
369    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
370    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
371  if (Subtarget->is64Bit())
372    return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
373                                   DL, DAG, InVals);
374  return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
375                                 DL, DAG, InVals);
376}
377
378/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
379/// passed in either one or two GPRs, including FP values.  TODO: we should
380/// pass FP values in FP registers for fastcc functions.
381SDValue SparcTargetLowering::LowerFormalArguments_32(
382    SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
383    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
384    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
385  MachineFunction &MF = DAG.getMachineFunction();
386  MachineRegisterInfo &RegInfo = MF.getRegInfo();
387  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
388
389  // Assign locations to all of the incoming arguments.
390  SmallVector<CCValAssign, 16> ArgLocs;
391  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
392                 *DAG.getContext());
393  CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
394
395  const unsigned StackOffset = 92;
396  bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
397
398  unsigned InIdx = 0;
399  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
400    CCValAssign &VA = ArgLocs[i];
401
402    if (Ins[InIdx].Flags.isSRet()) {
403      if (InIdx != 0)
404        report_fatal_error("sparc only supports sret on the first parameter");
405      // Get SRet from [%fp+64].
406      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
407      SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
408      SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
409                                MachinePointerInfo(),
410                                false, false, false, 0);
411      InVals.push_back(Arg);
412      continue;
413    }
414
415    if (VA.isRegLoc()) {
416      if (VA.needsCustom()) {
417        assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
418
419        unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
420        MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
421        SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
422
423        assert(i+1 < e);
424        CCValAssign &NextVA = ArgLocs[++i];
425
426        SDValue LoVal;
427        if (NextVA.isMemLoc()) {
428          int FrameIdx = MF.getFrameInfo()->
429            CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
430          SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
431          LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
432                              MachinePointerInfo(),
433                              false, false, false, 0);
434        } else {
435          unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
436                                        &SP::IntRegsRegClass);
437          LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
438        }
439
440        if (IsLittleEndian)
441          std::swap(LoVal, HiVal);
442
443        SDValue WholeValue =
444          DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
445        WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue);
446        InVals.push_back(WholeValue);
447        continue;
448      }
449      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
450      MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
451      SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
452      if (VA.getLocVT() == MVT::f32)
453        Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
454      else if (VA.getLocVT() != MVT::i32) {
455        Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
456                          DAG.getValueType(VA.getLocVT()));
457        Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
458      }
459      InVals.push_back(Arg);
460      continue;
461    }
462
463    assert(VA.isMemLoc());
464
465    unsigned Offset = VA.getLocMemOffset()+StackOffset;
466    auto PtrVT = getPointerTy(DAG.getDataLayout());
467
468    if (VA.needsCustom()) {
469      assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
470      // If it is double-word aligned, just load.
471      if (Offset % 8 == 0) {
472        int FI = MF.getFrameInfo()->CreateFixedObject(8,
473                                                      Offset,
474                                                      true);
475        SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
476        SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
477                                   MachinePointerInfo(),
478                                   false,false, false, 0);
479        InVals.push_back(Load);
480        continue;
481      }
482
483      int FI = MF.getFrameInfo()->CreateFixedObject(4,
484                                                    Offset,
485                                                    true);
486      SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
487      SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
488                                  MachinePointerInfo(),
489                                  false, false, false, 0);
490      int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
491                                                     Offset+4,
492                                                     true);
493      SDValue FIPtr2 = DAG.getFrameIndex(FI2, PtrVT);
494
495      SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
496                                  MachinePointerInfo(),
497                                  false, false, false, 0);
498
499      if (IsLittleEndian)
500        std::swap(LoVal, HiVal);
501
502      SDValue WholeValue =
503        DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
504      WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue);
505      InVals.push_back(WholeValue);
506      continue;
507    }
508
509    int FI = MF.getFrameInfo()->CreateFixedObject(4,
510                                                  Offset,
511                                                  true);
512    SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
513    SDValue Load ;
514    if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
515      Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
516                         MachinePointerInfo(),
517                         false, false, false, 0);
518    } else if (VA.getValVT() == MVT::f128) {
519      report_fatal_error("SPARCv8 does not handle f128 in calls; "
520                         "pass indirectly");
521    } else {
522      // We shouldn't see any other value types here.
523      llvm_unreachable("Unexpected ValVT encountered in frame lowering.");
524    }
525    InVals.push_back(Load);
526  }
527
528  if (MF.getFunction()->hasStructRetAttr()) {
529    // Copy the SRet Argument to SRetReturnReg.
530    SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
531    unsigned Reg = SFI->getSRetReturnReg();
532    if (!Reg) {
533      Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
534      SFI->setSRetReturnReg(Reg);
535    }
536    SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
537    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
538  }
539
540  // Store remaining ArgRegs to the stack if this is a varargs function.
541  if (isVarArg) {
542    static const MCPhysReg ArgRegs[] = {
543      SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
544    };
545    unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
546    const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
547    unsigned ArgOffset = CCInfo.getNextStackOffset();
548    if (NumAllocated == 6)
549      ArgOffset += StackOffset;
550    else {
551      assert(!ArgOffset);
552      ArgOffset = 68+4*NumAllocated;
553    }
554
555    // Remember the vararg offset for the va_start implementation.
556    FuncInfo->setVarArgsFrameOffset(ArgOffset);
557
558    std::vector<SDValue> OutChains;
559
560    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
561      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
562      MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
563      SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
564
565      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
566                                                          true);
567      SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
568
569      OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
570                                       MachinePointerInfo(),
571                                       false, false, 0));
572      ArgOffset += 4;
573    }
574
575    if (!OutChains.empty()) {
576      OutChains.push_back(Chain);
577      Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
578    }
579  }
580
581  return Chain;
582}
583
584// Lower formal arguments for the 64 bit ABI.
585SDValue SparcTargetLowering::LowerFormalArguments_64(
586    SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
587    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
588    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
589  MachineFunction &MF = DAG.getMachineFunction();
590
591  // Analyze arguments according to CC_Sparc64.
592  SmallVector<CCValAssign, 16> ArgLocs;
593  CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
594                 *DAG.getContext());
595  CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
596
597  // The argument array begins at %fp+BIAS+128, after the register save area.
598  const unsigned ArgArea = 128;
599
600  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
601    CCValAssign &VA = ArgLocs[i];
602    if (VA.isRegLoc()) {
603      // This argument is passed in a register.
604      // All integer register arguments are promoted by the caller to i64.
605
606      // Create a virtual register for the promoted live-in value.
607      unsigned VReg = MF.addLiveIn(VA.getLocReg(),
608                                   getRegClassFor(VA.getLocVT()));
609      SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
610
611      // Get the high bits for i32 struct elements.
612      if (VA.getValVT() == MVT::i32 && VA.needsCustom())
613        Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
614                          DAG.getConstant(32, DL, MVT::i32));
615
616      // The caller promoted the argument, so insert an Assert?ext SDNode so we
617      // won't promote the value again in this function.
618      switch (VA.getLocInfo()) {
619      case CCValAssign::SExt:
620        Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
621                          DAG.getValueType(VA.getValVT()));
622        break;
623      case CCValAssign::ZExt:
624        Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
625                          DAG.getValueType(VA.getValVT()));
626        break;
627      default:
628        break;
629      }
630
631      // Truncate the register down to the argument type.
632      if (VA.isExtInLoc())
633        Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
634
635      InVals.push_back(Arg);
636      continue;
637    }
638
639    // The registers are exhausted. This argument was passed on the stack.
640    assert(VA.isMemLoc());
641    // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
642    // beginning of the arguments area at %fp+BIAS+128.
643    unsigned Offset = VA.getLocMemOffset() + ArgArea;
644    unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
645    // Adjust offset for extended arguments, SPARC is big-endian.
646    // The caller will have written the full slot with extended bytes, but we
647    // prefer our own extending loads.
648    if (VA.isExtInLoc())
649      Offset += 8 - ValSize;
650    int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
651    InVals.push_back(DAG.getLoad(
652        VA.getValVT(), DL, Chain,
653        DAG.getFrameIndex(FI, getPointerTy(MF.getDataLayout())),
654        MachinePointerInfo::getFixedStack(MF, FI), false, false, false, 0));
655  }
656
657  if (!IsVarArg)
658    return Chain;
659
660  // This function takes variable arguments, some of which may have been passed
661  // in registers %i0-%i5. Variable floating point arguments are never passed
662  // in floating point registers. They go on %i0-%i5 or on the stack like
663  // integer arguments.
664  //
665  // The va_start intrinsic needs to know the offset to the first variable
666  // argument.
667  unsigned ArgOffset = CCInfo.getNextStackOffset();
668  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
669  // Skip the 128 bytes of register save area.
670  FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
671                                  Subtarget->getStackPointerBias());
672
673  // Save the variable arguments that were passed in registers.
674  // The caller is required to reserve stack space for 6 arguments regardless
675  // of how many arguments were actually passed.
676  SmallVector<SDValue, 8> OutChains;
677  for (; ArgOffset < 6*8; ArgOffset += 8) {
678    unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
679    SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
680    int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
681    auto PtrVT = getPointerTy(MF.getDataLayout());
682    OutChains.push_back(DAG.getStore(
683        Chain, DL, VArg, DAG.getFrameIndex(FI, PtrVT),
684        MachinePointerInfo::getFixedStack(MF, FI), false, false, 0));
685  }
686
687  if (!OutChains.empty())
688    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
689
690  return Chain;
691}
692
693SDValue
694SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
695                               SmallVectorImpl<SDValue> &InVals) const {
696  if (Subtarget->is64Bit())
697    return LowerCall_64(CLI, InVals);
698  return LowerCall_32(CLI, InVals);
699}
700
701static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
702                                     ImmutableCallSite *CS) {
703  if (CS)
704    return CS->hasFnAttr(Attribute::ReturnsTwice);
705
706  const Function *CalleeFn = nullptr;
707  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
708    CalleeFn = dyn_cast<Function>(G->getGlobal());
709  } else if (ExternalSymbolSDNode *E =
710             dyn_cast<ExternalSymbolSDNode>(Callee)) {
711    const Function *Fn = DAG.getMachineFunction().getFunction();
712    const Module *M = Fn->getParent();
713    const char *CalleeName = E->getSymbol();
714    CalleeFn = M->getFunction(CalleeName);
715  }
716
717  if (!CalleeFn)
718    return false;
719  return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
720}
721
722// Lower a call for the 32-bit ABI.
723SDValue
724SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
725                                  SmallVectorImpl<SDValue> &InVals) const {
726  SelectionDAG &DAG                     = CLI.DAG;
727  SDLoc &dl                             = CLI.DL;
728  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
729  SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
730  SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
731  SDValue Chain                         = CLI.Chain;
732  SDValue Callee                        = CLI.Callee;
733  bool &isTailCall                      = CLI.IsTailCall;
734  CallingConv::ID CallConv              = CLI.CallConv;
735  bool isVarArg                         = CLI.IsVarArg;
736
737  // Sparc target does not yet support tail call optimization.
738  isTailCall = false;
739
740  // Analyze operands of the call, assigning locations to each operand.
741  SmallVector<CCValAssign, 16> ArgLocs;
742  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
743                 *DAG.getContext());
744  CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
745
746  // Get the size of the outgoing arguments stack space requirement.
747  unsigned ArgsSize = CCInfo.getNextStackOffset();
748
749  // Keep stack frames 8-byte aligned.
750  ArgsSize = (ArgsSize+7) & ~7;
751
752  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
753
754  // Create local copies for byval args.
755  SmallVector<SDValue, 8> ByValArgs;
756  for (unsigned i = 0,  e = Outs.size(); i != e; ++i) {
757    ISD::ArgFlagsTy Flags = Outs[i].Flags;
758    if (!Flags.isByVal())
759      continue;
760
761    SDValue Arg = OutVals[i];
762    unsigned Size = Flags.getByValSize();
763    unsigned Align = Flags.getByValAlign();
764
765    if (Size > 0U) {
766      int FI = MFI->CreateStackObject(Size, Align, false);
767      SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
768      SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32);
769
770      Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
771                            false,        // isVolatile,
772                            (Size <= 32), // AlwaysInline if size <= 32,
773                            false,        // isTailCall
774                            MachinePointerInfo(), MachinePointerInfo());
775      ByValArgs.push_back(FIPtr);
776    }
777    else {
778      SDValue nullVal;
779      ByValArgs.push_back(nullVal);
780    }
781  }
782
783  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
784                               dl);
785
786  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
787  SmallVector<SDValue, 8> MemOpChains;
788
789  const unsigned StackOffset = 92;
790  bool hasStructRetAttr = false;
791  // Walk the register/memloc assignments, inserting copies/loads.
792  for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
793       i != e;
794       ++i, ++realArgIdx) {
795    CCValAssign &VA = ArgLocs[i];
796    SDValue Arg = OutVals[realArgIdx];
797
798    ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
799
800    // Use local copy if it is a byval arg.
801    if (Flags.isByVal()) {
802      Arg = ByValArgs[byvalArgIdx++];
803      if (!Arg) {
804        continue;
805      }
806    }
807
808    // Promote the value if needed.
809    switch (VA.getLocInfo()) {
810    default: llvm_unreachable("Unknown loc info!");
811    case CCValAssign::Full: break;
812    case CCValAssign::SExt:
813      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
814      break;
815    case CCValAssign::ZExt:
816      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
817      break;
818    case CCValAssign::AExt:
819      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
820      break;
821    case CCValAssign::BCvt:
822      Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
823      break;
824    }
825
826    if (Flags.isSRet()) {
827      assert(VA.needsCustom());
828      // store SRet argument in %sp+64
829      SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
830      SDValue PtrOff = DAG.getIntPtrConstant(64, dl);
831      PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
832      MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
833                                         MachinePointerInfo(),
834                                         false, false, 0));
835      hasStructRetAttr = true;
836      continue;
837    }
838
839    if (VA.needsCustom()) {
840      assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
841
842      if (VA.isMemLoc()) {
843        unsigned Offset = VA.getLocMemOffset() + StackOffset;
844        // if it is double-word aligned, just store.
845        if (Offset % 8 == 0) {
846          SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
847          SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
848          PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
849          MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
850                                             MachinePointerInfo(),
851                                             false, false, 0));
852          continue;
853        }
854      }
855
856      if (VA.getLocVT() == MVT::f64) {
857        // Move from the float value from float registers into the
858        // integer registers.
859
860        // TODO: The f64 -> v2i32 conversion is super-inefficient for
861        // constants: it sticks them in the constant pool, then loads
862        // to a fp register, then stores to temp memory, then loads to
863        // integer registers.
864        Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
865      }
866
867      SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
868                                  Arg,
869                                  DAG.getConstant(0, dl, getVectorIdxTy(DAG.getDataLayout())));
870      SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
871                                  Arg,
872                                  DAG.getConstant(1, dl, getVectorIdxTy(DAG.getDataLayout())));
873
874      if (VA.isRegLoc()) {
875        RegsToPass.push_back(std::make_pair(VA.getLocReg(), Part0));
876        assert(i+1 != e);
877        CCValAssign &NextVA = ArgLocs[++i];
878        if (NextVA.isRegLoc()) {
879          RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Part1));
880        } else {
881          // Store the second part in stack.
882          unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
883          SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
884          SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
885          PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
886          MemOpChains.push_back(DAG.getStore(Chain, dl, Part1, PtrOff,
887                                             MachinePointerInfo(),
888                                             false, false, 0));
889        }
890      } else {
891        unsigned Offset = VA.getLocMemOffset() + StackOffset;
892        // Store the first part.
893        SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
894        SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
895        PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
896        MemOpChains.push_back(DAG.getStore(Chain, dl, Part0, PtrOff,
897                                           MachinePointerInfo(),
898                                           false, false, 0));
899        // Store the second part.
900        PtrOff = DAG.getIntPtrConstant(Offset + 4, dl);
901        PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
902        MemOpChains.push_back(DAG.getStore(Chain, dl, Part1, PtrOff,
903                                           MachinePointerInfo(),
904                                           false, false, 0));
905      }
906      continue;
907    }
908
909    // Arguments that can be passed on register must be kept at
910    // RegsToPass vector
911    if (VA.isRegLoc()) {
912      if (VA.getLocVT() != MVT::f32) {
913        RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
914        continue;
915      }
916      Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
917      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
918      continue;
919    }
920
921    assert(VA.isMemLoc());
922
923    // Create a store off the stack pointer for this argument.
924    SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
925    SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset,
926                                           dl);
927    PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
928    MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
929                                       MachinePointerInfo(),
930                                       false, false, 0));
931  }
932
933
934  // Emit all stores, make sure the occur before any copies into physregs.
935  if (!MemOpChains.empty())
936    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
937
938  // Build a sequence of copy-to-reg nodes chained together with token
939  // chain and flag operands which copy the outgoing args into registers.
940  // The InFlag in necessary since all emitted instructions must be
941  // stuck together.
942  SDValue InFlag;
943  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
944    unsigned Reg = toCallerWindow(RegsToPass[i].first);
945    Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
946    InFlag = Chain.getValue(1);
947  }
948
949  unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
950  bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
951
952  // If the callee is a GlobalAddress node (quite common, every direct call is)
953  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
954  // Likewise ExternalSymbol -> TargetExternalSymbol.
955  unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30 : 0;
956  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
957    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
958  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
959    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
960
961  // Returns a chain & a flag for retval copy to use
962  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
963  SmallVector<SDValue, 8> Ops;
964  Ops.push_back(Chain);
965  Ops.push_back(Callee);
966  if (hasStructRetAttr)
967    Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
968  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
969    Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
970                                  RegsToPass[i].second.getValueType()));
971
972  // Add a register mask operand representing the call-preserved registers.
973  const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
974  const uint32_t *Mask =
975      ((hasReturnsTwice)
976           ? TRI->getRTCallPreservedMask(CallConv)
977           : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
978  assert(Mask && "Missing call preserved mask for calling convention");
979  Ops.push_back(DAG.getRegisterMask(Mask));
980
981  if (InFlag.getNode())
982    Ops.push_back(InFlag);
983
984  Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
985  InFlag = Chain.getValue(1);
986
987  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
988                             DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
989  InFlag = Chain.getValue(1);
990
991  // Assign locations to each value returned by this call.
992  SmallVector<CCValAssign, 16> RVLocs;
993  CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
994                 *DAG.getContext());
995
996  RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
997
998  // Copy all of the result registers out of their specified physreg.
999  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1000    if (RVLocs[i].getLocVT() == MVT::v2i32) {
1001      SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32);
1002      SDValue Lo = DAG.getCopyFromReg(
1003          Chain, dl, toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InFlag);
1004      Chain = Lo.getValue(1);
1005      InFlag = Lo.getValue(2);
1006      Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo,
1007                        DAG.getConstant(0, dl, MVT::i32));
1008      SDValue Hi = DAG.getCopyFromReg(
1009          Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InFlag);
1010      Chain = Hi.getValue(1);
1011      InFlag = Hi.getValue(2);
1012      Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
1013                        DAG.getConstant(1, dl, MVT::i32));
1014      InVals.push_back(Vec);
1015    } else {
1016      Chain =
1017          DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
1018                             RVLocs[i].getValVT(), InFlag)
1019              .getValue(1);
1020      InFlag = Chain.getValue(2);
1021      InVals.push_back(Chain.getValue(0));
1022    }
1023  }
1024
1025  return Chain;
1026}
1027
1028// FIXME? Maybe this could be a TableGen attribute on some registers and
1029// this table could be generated automatically from RegInfo.
1030unsigned SparcTargetLowering::getRegisterByName(const char* RegName, EVT VT,
1031                                               SelectionDAG &DAG) const {
1032  unsigned Reg = StringSwitch<unsigned>(RegName)
1033    .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3)
1034    .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7)
1035    .Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3)
1036    .Case("o4", SP::O4).Case("o5", SP::O5).Case("o6", SP::O6).Case("o7", SP::O7)
1037    .Case("l0", SP::L0).Case("l1", SP::L1).Case("l2", SP::L2).Case("l3", SP::L3)
1038    .Case("l4", SP::L4).Case("l5", SP::L5).Case("l6", SP::L6).Case("l7", SP::L7)
1039    .Case("g0", SP::G0).Case("g1", SP::G1).Case("g2", SP::G2).Case("g3", SP::G3)
1040    .Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7", SP::G7)
1041    .Default(0);
1042
1043  if (Reg)
1044    return Reg;
1045
1046  report_fatal_error("Invalid register name global variable");
1047}
1048
1049// This functions returns true if CalleeName is a ABI function that returns
1050// a long double (fp128).
1051static bool isFP128ABICall(const char *CalleeName)
1052{
1053  static const char *const ABICalls[] =
1054    {  "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
1055       "_Q_sqrt", "_Q_neg",
1056       "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
1057       "_Q_lltoq", "_Q_ulltoq",
1058       nullptr
1059    };
1060  for (const char * const *I = ABICalls; *I != nullptr; ++I)
1061    if (strcmp(CalleeName, *I) == 0)
1062      return true;
1063  return false;
1064}
1065
1066unsigned
1067SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
1068{
1069  const Function *CalleeFn = nullptr;
1070  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1071    CalleeFn = dyn_cast<Function>(G->getGlobal());
1072  } else if (ExternalSymbolSDNode *E =
1073             dyn_cast<ExternalSymbolSDNode>(Callee)) {
1074    const Function *Fn = DAG.getMachineFunction().getFunction();
1075    const Module *M = Fn->getParent();
1076    const char *CalleeName = E->getSymbol();
1077    CalleeFn = M->getFunction(CalleeName);
1078    if (!CalleeFn && isFP128ABICall(CalleeName))
1079      return 16; // Return sizeof(fp128)
1080  }
1081
1082  if (!CalleeFn)
1083    return 0;
1084
1085  // It would be nice to check for the sret attribute on CalleeFn here,
1086  // but since it is not part of the function type, any check will misfire.
1087
1088  PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
1089  Type *ElementTy = Ty->getElementType();
1090  return DAG.getDataLayout().getTypeAllocSize(ElementTy);
1091}
1092
1093
1094// Fixup floating point arguments in the ... part of a varargs call.
1095//
1096// The SPARC v9 ABI requires that floating point arguments are treated the same
1097// as integers when calling a varargs function. This does not apply to the
1098// fixed arguments that are part of the function's prototype.
1099//
1100// This function post-processes a CCValAssign array created by
1101// AnalyzeCallOperands().
1102static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1103                                   ArrayRef<ISD::OutputArg> Outs) {
1104  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1105    const CCValAssign &VA = ArgLocs[i];
1106    MVT ValTy = VA.getLocVT();
1107    // FIXME: What about f32 arguments? C promotes them to f64 when calling
1108    // varargs functions.
1109    if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1110      continue;
1111    // The fixed arguments to a varargs function still go in FP registers.
1112    if (Outs[VA.getValNo()].IsFixed)
1113      continue;
1114
1115    // This floating point argument should be reassigned.
1116    CCValAssign NewVA;
1117
1118    // Determine the offset into the argument array.
1119    unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1120    unsigned argSize  = (ValTy == MVT::f64) ? 8 : 16;
1121    unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1122    assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1123
1124    if (Offset < 6*8) {
1125      // This argument should go in %i0-%i5.
1126      unsigned IReg = SP::I0 + Offset/8;
1127      if (ValTy == MVT::f64)
1128        // Full register, just bitconvert into i64.
1129        NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1130                                    IReg, MVT::i64, CCValAssign::BCvt);
1131      else {
1132        assert(ValTy == MVT::f128 && "Unexpected type!");
1133        // Full register, just bitconvert into i128 -- We will lower this into
1134        // two i64s in LowerCall_64.
1135        NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(),
1136                                          IReg, MVT::i128, CCValAssign::BCvt);
1137      }
1138    } else {
1139      // This needs to go to memory, we're out of integer registers.
1140      NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1141                                  Offset, VA.getLocVT(), VA.getLocInfo());
1142    }
1143    ArgLocs[i] = NewVA;
1144  }
1145}
1146
1147// Lower a call for the 64-bit ABI.
1148SDValue
1149SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1150                                  SmallVectorImpl<SDValue> &InVals) const {
1151  SelectionDAG &DAG = CLI.DAG;
1152  SDLoc DL = CLI.DL;
1153  SDValue Chain = CLI.Chain;
1154  auto PtrVT = getPointerTy(DAG.getDataLayout());
1155
1156  // Sparc target does not yet support tail call optimization.
1157  CLI.IsTailCall = false;
1158
1159  // Analyze operands of the call, assigning locations to each operand.
1160  SmallVector<CCValAssign, 16> ArgLocs;
1161  CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1162                 *DAG.getContext());
1163  CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1164
1165  // Get the size of the outgoing arguments stack space requirement.
1166  // The stack offset computed by CC_Sparc64 includes all arguments.
1167  // Called functions expect 6 argument words to exist in the stack frame, used
1168  // or not.
1169  unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1170
1171  // Keep stack frames 16-byte aligned.
1172  ArgsSize = alignTo(ArgsSize, 16);
1173
1174  // Varargs calls require special treatment.
1175  if (CLI.IsVarArg)
1176    fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1177
1178  // Adjust the stack pointer to make room for the arguments.
1179  // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1180  // with more than 6 arguments.
1181  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
1182                               DL);
1183
1184  // Collect the set of registers to pass to the function and their values.
1185  // This will be emitted as a sequence of CopyToReg nodes glued to the call
1186  // instruction.
1187  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1188
1189  // Collect chains from all the memory opeations that copy arguments to the
1190  // stack. They must follow the stack pointer adjustment above and precede the
1191  // call instruction itself.
1192  SmallVector<SDValue, 8> MemOpChains;
1193
1194  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1195    const CCValAssign &VA = ArgLocs[i];
1196    SDValue Arg = CLI.OutVals[i];
1197
1198    // Promote the value if needed.
1199    switch (VA.getLocInfo()) {
1200    default:
1201      llvm_unreachable("Unknown location info!");
1202    case CCValAssign::Full:
1203      break;
1204    case CCValAssign::SExt:
1205      Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1206      break;
1207    case CCValAssign::ZExt:
1208      Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1209      break;
1210    case CCValAssign::AExt:
1211      Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1212      break;
1213    case CCValAssign::BCvt:
1214      // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1215      // SPARC does not support i128 natively. Lower it into two i64, see below.
1216      if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1217          || VA.getLocVT() != MVT::i128)
1218        Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1219      break;
1220    }
1221
1222    if (VA.isRegLoc()) {
1223      if (VA.needsCustom() && VA.getValVT() == MVT::f128
1224          && VA.getLocVT() == MVT::i128) {
1225        // Store and reload into the interger register reg and reg+1.
1226        unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1227        unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1228        SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1229        SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL);
1230        HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff);
1231        SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL);
1232        LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff);
1233
1234        // Store to %sp+BIAS+128+Offset
1235        SDValue Store = DAG.getStore(Chain, DL, Arg, HiPtrOff,
1236                                     MachinePointerInfo(),
1237                                     false, false, 0);
1238        // Load into Reg and Reg+1
1239        SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff,
1240                                   MachinePointerInfo(),
1241                                   false, false, false, 0);
1242        SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff,
1243                                   MachinePointerInfo(),
1244                                   false, false, false, 0);
1245        RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()),
1246                                            Hi64));
1247        RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1),
1248                                            Lo64));
1249        continue;
1250      }
1251
1252      // The custom bit on an i32 return value indicates that it should be
1253      // passed in the high bits of the register.
1254      if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1255        Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1256                          DAG.getConstant(32, DL, MVT::i32));
1257
1258        // The next value may go in the low bits of the same register.
1259        // Handle both at once.
1260        if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1261            ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1262          SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1263                                   CLI.OutVals[i+1]);
1264          Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1265          // Skip the next value, it's already done.
1266          ++i;
1267        }
1268      }
1269      RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1270      continue;
1271    }
1272
1273    assert(VA.isMemLoc());
1274
1275    // Create a store off the stack pointer for this argument.
1276    SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1277    // The argument area starts at %fp+BIAS+128 in the callee frame,
1278    // %sp+BIAS+128 in ours.
1279    SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1280                                           Subtarget->getStackPointerBias() +
1281                                           128, DL);
1282    PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
1283    MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
1284                                       MachinePointerInfo(),
1285                                       false, false, 0));
1286  }
1287
1288  // Emit all stores, make sure they occur before the call.
1289  if (!MemOpChains.empty())
1290    Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1291
1292  // Build a sequence of CopyToReg nodes glued together with token chain and
1293  // glue operands which copy the outgoing args into registers. The InGlue is
1294  // necessary since all emitted instructions must be stuck together in order
1295  // to pass the live physical registers.
1296  SDValue InGlue;
1297  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1298    Chain = DAG.getCopyToReg(Chain, DL,
1299                             RegsToPass[i].first, RegsToPass[i].second, InGlue);
1300    InGlue = Chain.getValue(1);
1301  }
1302
1303  // If the callee is a GlobalAddress node (quite common, every direct call is)
1304  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1305  // Likewise ExternalSymbol -> TargetExternalSymbol.
1306  SDValue Callee = CLI.Callee;
1307  bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1308  unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30 : 0;
1309  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1310    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF);
1311  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1312    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF);
1313
1314  // Build the operands for the call instruction itself.
1315  SmallVector<SDValue, 8> Ops;
1316  Ops.push_back(Chain);
1317  Ops.push_back(Callee);
1318  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1319    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1320                                  RegsToPass[i].second.getValueType()));
1321
1322  // Add a register mask operand representing the call-preserved registers.
1323  const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1324  const uint32_t *Mask =
1325      ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
1326                         : TRI->getCallPreservedMask(DAG.getMachineFunction(),
1327                                                     CLI.CallConv));
1328  assert(Mask && "Missing call preserved mask for calling convention");
1329  Ops.push_back(DAG.getRegisterMask(Mask));
1330
1331  // Make sure the CopyToReg nodes are glued to the call instruction which
1332  // consumes the registers.
1333  if (InGlue.getNode())
1334    Ops.push_back(InGlue);
1335
1336  // Now the call itself.
1337  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1338  Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1339  InGlue = Chain.getValue(1);
1340
1341  // Revert the stack pointer immediately after the call.
1342  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
1343                             DAG.getIntPtrConstant(0, DL, true), InGlue, DL);
1344  InGlue = Chain.getValue(1);
1345
1346  // Now extract the return values. This is more or less the same as
1347  // LowerFormalArguments_64.
1348
1349  // Assign locations to each value returned by this call.
1350  SmallVector<CCValAssign, 16> RVLocs;
1351  CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1352                 *DAG.getContext());
1353
1354  // Set inreg flag manually for codegen generated library calls that
1355  // return float.
1356  if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == nullptr)
1357    CLI.Ins[0].Flags.setInReg();
1358
1359  RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1360
1361  // Copy all of the result registers out of their specified physreg.
1362  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1363    CCValAssign &VA = RVLocs[i];
1364    unsigned Reg = toCallerWindow(VA.getLocReg());
1365
1366    // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1367    // reside in the same register in the high and low bits. Reuse the
1368    // CopyFromReg previous node to avoid duplicate copies.
1369    SDValue RV;
1370    if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1371      if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1372        RV = Chain.getValue(0);
1373
1374    // But usually we'll create a new CopyFromReg for a different register.
1375    if (!RV.getNode()) {
1376      RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1377      Chain = RV.getValue(1);
1378      InGlue = Chain.getValue(2);
1379    }
1380
1381    // Get the high bits for i32 struct elements.
1382    if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1383      RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1384                       DAG.getConstant(32, DL, MVT::i32));
1385
1386    // The callee promoted the return value, so insert an Assert?ext SDNode so
1387    // we won't promote the value again in this function.
1388    switch (VA.getLocInfo()) {
1389    case CCValAssign::SExt:
1390      RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1391                       DAG.getValueType(VA.getValVT()));
1392      break;
1393    case CCValAssign::ZExt:
1394      RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1395                       DAG.getValueType(VA.getValVT()));
1396      break;
1397    default:
1398      break;
1399    }
1400
1401    // Truncate the register down to the return value type.
1402    if (VA.isExtInLoc())
1403      RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1404
1405    InVals.push_back(RV);
1406  }
1407
1408  return Chain;
1409}
1410
1411//===----------------------------------------------------------------------===//
1412// TargetLowering Implementation
1413//===----------------------------------------------------------------------===//
1414
1415TargetLowering::AtomicExpansionKind SparcTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
1416  if (AI->getOperation() == AtomicRMWInst::Xchg &&
1417      AI->getType()->getPrimitiveSizeInBits() == 32)
1418    return AtomicExpansionKind::None; // Uses xchg instruction
1419
1420  return AtomicExpansionKind::CmpXChg;
1421}
1422
1423/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1424/// condition.
1425static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1426  switch (CC) {
1427  default: llvm_unreachable("Unknown integer condition code!");
1428  case ISD::SETEQ:  return SPCC::ICC_E;
1429  case ISD::SETNE:  return SPCC::ICC_NE;
1430  case ISD::SETLT:  return SPCC::ICC_L;
1431  case ISD::SETGT:  return SPCC::ICC_G;
1432  case ISD::SETLE:  return SPCC::ICC_LE;
1433  case ISD::SETGE:  return SPCC::ICC_GE;
1434  case ISD::SETULT: return SPCC::ICC_CS;
1435  case ISD::SETULE: return SPCC::ICC_LEU;
1436  case ISD::SETUGT: return SPCC::ICC_GU;
1437  case ISD::SETUGE: return SPCC::ICC_CC;
1438  }
1439}
1440
1441/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1442/// FCC condition.
1443static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1444  switch (CC) {
1445  default: llvm_unreachable("Unknown fp condition code!");
1446  case ISD::SETEQ:
1447  case ISD::SETOEQ: return SPCC::FCC_E;
1448  case ISD::SETNE:
1449  case ISD::SETUNE: return SPCC::FCC_NE;
1450  case ISD::SETLT:
1451  case ISD::SETOLT: return SPCC::FCC_L;
1452  case ISD::SETGT:
1453  case ISD::SETOGT: return SPCC::FCC_G;
1454  case ISD::SETLE:
1455  case ISD::SETOLE: return SPCC::FCC_LE;
1456  case ISD::SETGE:
1457  case ISD::SETOGE: return SPCC::FCC_GE;
1458  case ISD::SETULT: return SPCC::FCC_UL;
1459  case ISD::SETULE: return SPCC::FCC_ULE;
1460  case ISD::SETUGT: return SPCC::FCC_UG;
1461  case ISD::SETUGE: return SPCC::FCC_UGE;
1462  case ISD::SETUO:  return SPCC::FCC_U;
1463  case ISD::SETO:   return SPCC::FCC_O;
1464  case ISD::SETONE: return SPCC::FCC_LG;
1465  case ISD::SETUEQ: return SPCC::FCC_UE;
1466  }
1467}
1468
1469SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
1470                                         const SparcSubtarget &STI)
1471    : TargetLowering(TM), Subtarget(&STI) {
1472  MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
1473
1474  // Instructions which use registers as conditionals examine all the
1475  // bits (as does the pseudo SELECT_CC expansion). I don't think it
1476  // matters much whether it's ZeroOrOneBooleanContent, or
1477  // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
1478  // former.
1479  setBooleanContents(ZeroOrOneBooleanContent);
1480  setBooleanVectorContents(ZeroOrOneBooleanContent);
1481
1482  // Set up the register classes.
1483  addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1484  if (!Subtarget->useSoftFloat()) {
1485    addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1486    addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1487    addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1488  }
1489  if (Subtarget->is64Bit()) {
1490    addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1491  } else {
1492    // On 32bit sparc, we define a double-register 32bit register
1493    // class, as well. This is modeled in LLVM as a 2-vector of i32.
1494    addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
1495
1496    // ...but almost all operations must be expanded, so set that as
1497    // the default.
1498    for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
1499      setOperationAction(Op, MVT::v2i32, Expand);
1500    }
1501    // Truncating/extending stores/loads are also not supported.
1502    for (MVT VT : MVT::integer_vector_valuetypes()) {
1503      setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand);
1504      setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand);
1505      setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand);
1506
1507      setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand);
1508      setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand);
1509      setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand);
1510
1511      setTruncStoreAction(VT, MVT::v2i32, Expand);
1512      setTruncStoreAction(MVT::v2i32, VT, Expand);
1513    }
1514    // However, load and store *are* legal.
1515    setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
1516    setOperationAction(ISD::STORE, MVT::v2i32, Legal);
1517    setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
1518    setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal);
1519
1520    // And we need to promote i64 loads/stores into vector load/store
1521    setOperationAction(ISD::LOAD, MVT::i64, Custom);
1522    setOperationAction(ISD::STORE, MVT::i64, Custom);
1523
1524    // Sadly, this doesn't work:
1525    //    AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
1526    //    AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1527  }
1528
1529  // Turn FP extload into load/fextend
1530  for (MVT VT : MVT::fp_valuetypes()) {
1531    setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1532    setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
1533  }
1534
1535  // Sparc doesn't have i1 sign extending load
1536  for (MVT VT : MVT::integer_valuetypes())
1537    setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1538
1539  // Turn FP truncstore into trunc + store.
1540  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1541  setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1542  setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1543
1544  // Custom legalize GlobalAddress nodes into LO/HI parts.
1545  setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
1546  setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
1547  setOperationAction(ISD::ConstantPool, PtrVT, Custom);
1548  setOperationAction(ISD::BlockAddress, PtrVT, Custom);
1549
1550  // Sparc doesn't have sext_inreg, replace them with shl/sra
1551  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1552  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1553  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1554
1555  // Sparc has no REM or DIVREM operations.
1556  setOperationAction(ISD::UREM, MVT::i32, Expand);
1557  setOperationAction(ISD::SREM, MVT::i32, Expand);
1558  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1559  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1560
1561  // ... nor does SparcV9.
1562  if (Subtarget->is64Bit()) {
1563    setOperationAction(ISD::UREM, MVT::i64, Expand);
1564    setOperationAction(ISD::SREM, MVT::i64, Expand);
1565    setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1566    setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1567  }
1568
1569  // Custom expand fp<->sint
1570  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1571  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1572  setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
1573  setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
1574
1575  // Custom Expand fp<->uint
1576  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1577  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1578  setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
1579  setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
1580
1581  setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1582  setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1583
1584  // Sparc has no select or setcc: expand to SELECT_CC.
1585  setOperationAction(ISD::SELECT, MVT::i32, Expand);
1586  setOperationAction(ISD::SELECT, MVT::f32, Expand);
1587  setOperationAction(ISD::SELECT, MVT::f64, Expand);
1588  setOperationAction(ISD::SELECT, MVT::f128, Expand);
1589
1590  setOperationAction(ISD::SETCC, MVT::i32, Expand);
1591  setOperationAction(ISD::SETCC, MVT::f32, Expand);
1592  setOperationAction(ISD::SETCC, MVT::f64, Expand);
1593  setOperationAction(ISD::SETCC, MVT::f128, Expand);
1594
1595  // Sparc doesn't have BRCOND either, it has BR_CC.
1596  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1597  setOperationAction(ISD::BRIND, MVT::Other, Expand);
1598  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1599  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1600  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1601  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1602  setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1603
1604  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1605  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1606  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1607  setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1608
1609  setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1610  setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1611
1612  if (Subtarget->is64Bit()) {
1613    setOperationAction(ISD::ADDC, MVT::i64, Custom);
1614    setOperationAction(ISD::ADDE, MVT::i64, Custom);
1615    setOperationAction(ISD::SUBC, MVT::i64, Custom);
1616    setOperationAction(ISD::SUBE, MVT::i64, Custom);
1617    setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1618    setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1619    setOperationAction(ISD::SELECT, MVT::i64, Expand);
1620    setOperationAction(ISD::SETCC, MVT::i64, Expand);
1621    setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1622    setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1623
1624    setOperationAction(ISD::CTPOP, MVT::i64,
1625                       Subtarget->usePopc() ? Legal : Expand);
1626    setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1627    setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1628    setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1629    setOperationAction(ISD::ROTL , MVT::i64, Expand);
1630    setOperationAction(ISD::ROTR , MVT::i64, Expand);
1631    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
1632  }
1633
1634  // ATOMICs.
1635  // Atomics are supported on SparcV9. 32-bit atomics are also
1636  // supported by some Leon SparcV8 variants. Otherwise, atomics
1637  // are unsupported.
1638  if (Subtarget->isV9() || Subtarget->hasLeonCasa())
1639    setMaxAtomicSizeInBitsSupported(64);
1640  else
1641    setMaxAtomicSizeInBitsSupported(0);
1642
1643  setMinCmpXchgSizeInBits(32);
1644
1645  setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
1646
1647  setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
1648
1649  // Custom Lower Atomic LOAD/STORE
1650  setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1651  setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1652
1653  if (Subtarget->is64Bit()) {
1654    setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
1655    setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
1656    setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
1657    setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
1658  }
1659
1660  if (!Subtarget->isV9()) {
1661    // SparcV8 does not have FNEGD and FABSD.
1662    setOperationAction(ISD::FNEG, MVT::f64, Custom);
1663    setOperationAction(ISD::FABS, MVT::f64, Custom);
1664  }
1665
1666  setOperationAction(ISD::FSIN , MVT::f128, Expand);
1667  setOperationAction(ISD::FCOS , MVT::f128, Expand);
1668  setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1669  setOperationAction(ISD::FREM , MVT::f128, Expand);
1670  setOperationAction(ISD::FMA  , MVT::f128, Expand);
1671  setOperationAction(ISD::FSIN , MVT::f64, Expand);
1672  setOperationAction(ISD::FCOS , MVT::f64, Expand);
1673  setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1674  setOperationAction(ISD::FREM , MVT::f64, Expand);
1675  setOperationAction(ISD::FMA  , MVT::f64, Expand);
1676  setOperationAction(ISD::FSIN , MVT::f32, Expand);
1677  setOperationAction(ISD::FCOS , MVT::f32, Expand);
1678  setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1679  setOperationAction(ISD::FREM , MVT::f32, Expand);
1680  setOperationAction(ISD::FMA  , MVT::f32, Expand);
1681  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1682  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1683  setOperationAction(ISD::ROTL , MVT::i32, Expand);
1684  setOperationAction(ISD::ROTR , MVT::i32, Expand);
1685  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1686  setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1687  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1688  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1689  setOperationAction(ISD::FPOW , MVT::f128, Expand);
1690  setOperationAction(ISD::FPOW , MVT::f64, Expand);
1691  setOperationAction(ISD::FPOW , MVT::f32, Expand);
1692
1693  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1694  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1695  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1696
1697  // FIXME: Sparc provides these multiplies, but we don't have them yet.
1698  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1699  setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1700
1701  if (Subtarget->is64Bit()) {
1702    setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1703    setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1704    setOperationAction(ISD::MULHU,     MVT::i64, Expand);
1705    setOperationAction(ISD::MULHS,     MVT::i64, Expand);
1706
1707    setOperationAction(ISD::UMULO,     MVT::i64, Custom);
1708    setOperationAction(ISD::SMULO,     MVT::i64, Custom);
1709
1710    setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
1711    setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
1712    setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
1713  }
1714
1715  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1716  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
1717  // VAARG needs to be lowered to not do unaligned accesses for doubles.
1718  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
1719
1720  setOperationAction(ISD::TRAP              , MVT::Other, Legal);
1721
1722  // Use the default implementation.
1723  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
1724  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
1725  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
1726  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
1727  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
1728
1729  setStackPointerRegisterToSaveRestore(SP::O6);
1730
1731  setOperationAction(ISD::CTPOP, MVT::i32,
1732                     Subtarget->usePopc() ? Legal : Expand);
1733
1734  if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1735    setOperationAction(ISD::LOAD, MVT::f128, Legal);
1736    setOperationAction(ISD::STORE, MVT::f128, Legal);
1737  } else {
1738    setOperationAction(ISD::LOAD, MVT::f128, Custom);
1739    setOperationAction(ISD::STORE, MVT::f128, Custom);
1740  }
1741
1742  if (Subtarget->hasHardQuad()) {
1743    setOperationAction(ISD::FADD,  MVT::f128, Legal);
1744    setOperationAction(ISD::FSUB,  MVT::f128, Legal);
1745    setOperationAction(ISD::FMUL,  MVT::f128, Legal);
1746    setOperationAction(ISD::FDIV,  MVT::f128, Legal);
1747    setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1748    setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1749    setOperationAction(ISD::FP_ROUND,  MVT::f64, Legal);
1750    if (Subtarget->isV9()) {
1751      setOperationAction(ISD::FNEG, MVT::f128, Legal);
1752      setOperationAction(ISD::FABS, MVT::f128, Legal);
1753    } else {
1754      setOperationAction(ISD::FNEG, MVT::f128, Custom);
1755      setOperationAction(ISD::FABS, MVT::f128, Custom);
1756    }
1757
1758    if (!Subtarget->is64Bit()) {
1759      setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1760      setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1761      setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1762      setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1763    }
1764
1765  } else {
1766    // Custom legalize f128 operations.
1767
1768    setOperationAction(ISD::FADD,  MVT::f128, Custom);
1769    setOperationAction(ISD::FSUB,  MVT::f128, Custom);
1770    setOperationAction(ISD::FMUL,  MVT::f128, Custom);
1771    setOperationAction(ISD::FDIV,  MVT::f128, Custom);
1772    setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1773    setOperationAction(ISD::FNEG,  MVT::f128, Custom);
1774    setOperationAction(ISD::FABS,  MVT::f128, Custom);
1775
1776    setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1777    setOperationAction(ISD::FP_ROUND,  MVT::f64, Custom);
1778    setOperationAction(ISD::FP_ROUND,  MVT::f32, Custom);
1779
1780    // Setup Runtime library names.
1781    if (Subtarget->is64Bit() && !Subtarget->useSoftFloat()) {
1782      setLibcallName(RTLIB::ADD_F128,  "_Qp_add");
1783      setLibcallName(RTLIB::SUB_F128,  "_Qp_sub");
1784      setLibcallName(RTLIB::MUL_F128,  "_Qp_mul");
1785      setLibcallName(RTLIB::DIV_F128,  "_Qp_div");
1786      setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1787      setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1788      setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1789      setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1790      setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1791      setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1792      setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1793      setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1794      setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1795      setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1796      setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1797      setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1798      setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1799    } else if (!Subtarget->useSoftFloat()) {
1800      setLibcallName(RTLIB::ADD_F128,  "_Q_add");
1801      setLibcallName(RTLIB::SUB_F128,  "_Q_sub");
1802      setLibcallName(RTLIB::MUL_F128,  "_Q_mul");
1803      setLibcallName(RTLIB::DIV_F128,  "_Q_div");
1804      setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1805      setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1806      setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1807      setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1808      setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1809      setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1810      setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1811      setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1812      setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1813      setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1814      setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1815      setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1816      setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1817    }
1818  }
1819
1820  if (Subtarget->fixAllFDIVSQRT()) {
1821    // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
1822    // the former instructions generate errata on LEON processors.
1823    setOperationAction(ISD::FDIV, MVT::f32, Promote);
1824    setOperationAction(ISD::FSQRT, MVT::f32, Promote);
1825  }
1826
1827  if (Subtarget->replaceFMULS()) {
1828    // Promote FMULS to FMULD instructions instead as
1829    // the former instructions generate errata on LEON processors.
1830    setOperationAction(ISD::FMUL, MVT::f32, Promote);
1831  }
1832
1833  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1834
1835  setMinFunctionAlignment(2);
1836
1837  computeRegisterProperties(Subtarget->getRegisterInfo());
1838}
1839
1840bool SparcTargetLowering::useSoftFloat() const {
1841  return Subtarget->useSoftFloat();
1842}
1843
1844const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1845  switch ((SPISD::NodeType)Opcode) {
1846  case SPISD::FIRST_NUMBER:    break;
1847  case SPISD::CMPICC:          return "SPISD::CMPICC";
1848  case SPISD::CMPFCC:          return "SPISD::CMPFCC";
1849  case SPISD::BRICC:           return "SPISD::BRICC";
1850  case SPISD::BRXCC:           return "SPISD::BRXCC";
1851  case SPISD::BRFCC:           return "SPISD::BRFCC";
1852  case SPISD::SELECT_ICC:      return "SPISD::SELECT_ICC";
1853  case SPISD::SELECT_XCC:      return "SPISD::SELECT_XCC";
1854  case SPISD::SELECT_FCC:      return "SPISD::SELECT_FCC";
1855  case SPISD::EH_SJLJ_SETJMP:  return "SPISD::EH_SJLJ_SETJMP";
1856  case SPISD::EH_SJLJ_LONGJMP: return "SPISD::EH_SJLJ_LONGJMP";
1857  case SPISD::Hi:              return "SPISD::Hi";
1858  case SPISD::Lo:              return "SPISD::Lo";
1859  case SPISD::FTOI:            return "SPISD::FTOI";
1860  case SPISD::ITOF:            return "SPISD::ITOF";
1861  case SPISD::FTOX:            return "SPISD::FTOX";
1862  case SPISD::XTOF:            return "SPISD::XTOF";
1863  case SPISD::CALL:            return "SPISD::CALL";
1864  case SPISD::RET_FLAG:        return "SPISD::RET_FLAG";
1865  case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1866  case SPISD::FLUSHW:          return "SPISD::FLUSHW";
1867  case SPISD::TLS_ADD:         return "SPISD::TLS_ADD";
1868  case SPISD::TLS_LD:          return "SPISD::TLS_LD";
1869  case SPISD::TLS_CALL:        return "SPISD::TLS_CALL";
1870  }
1871  return nullptr;
1872}
1873
1874EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
1875                                            EVT VT) const {
1876  if (!VT.isVector())
1877    return MVT::i32;
1878  return VT.changeVectorElementTypeToInteger();
1879}
1880
1881/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1882/// be zero. Op is expected to be a target specific node. Used by DAG
1883/// combiner.
1884void SparcTargetLowering::computeKnownBitsForTargetNode
1885                                (const SDValue Op,
1886                                 APInt &KnownZero,
1887                                 APInt &KnownOne,
1888                                 const SelectionDAG &DAG,
1889                                 unsigned Depth) const {
1890  APInt KnownZero2, KnownOne2;
1891  KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1892
1893  switch (Op.getOpcode()) {
1894  default: break;
1895  case SPISD::SELECT_ICC:
1896  case SPISD::SELECT_XCC:
1897  case SPISD::SELECT_FCC:
1898    DAG.computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1899    DAG.computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1900
1901    // Only known if known in both the LHS and RHS.
1902    KnownOne &= KnownOne2;
1903    KnownZero &= KnownZero2;
1904    break;
1905  }
1906}
1907
1908// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
1909// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
1910static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1911                             ISD::CondCode CC, unsigned &SPCC) {
1912  if (isNullConstant(RHS) &&
1913      CC == ISD::SETNE &&
1914      (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1915         LHS.getOpcode() == SPISD::SELECT_XCC) &&
1916        LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1917       (LHS.getOpcode() == SPISD::SELECT_FCC &&
1918        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1919      isOneConstant(LHS.getOperand(0)) &&
1920      isNullConstant(LHS.getOperand(1))) {
1921    SDValue CMPCC = LHS.getOperand(3);
1922    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1923    LHS = CMPCC.getOperand(0);
1924    RHS = CMPCC.getOperand(1);
1925  }
1926}
1927
1928// Convert to a target node and set target flags.
1929SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1930                                             SelectionDAG &DAG) const {
1931  if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1932    return DAG.getTargetGlobalAddress(GA->getGlobal(),
1933                                      SDLoc(GA),
1934                                      GA->getValueType(0),
1935                                      GA->getOffset(), TF);
1936
1937  if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1938    return DAG.getTargetConstantPool(CP->getConstVal(),
1939                                     CP->getValueType(0),
1940                                     CP->getAlignment(),
1941                                     CP->getOffset(), TF);
1942
1943  if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1944    return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1945                                     Op.getValueType(),
1946                                     0,
1947                                     TF);
1948
1949  if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1950    return DAG.getTargetExternalSymbol(ES->getSymbol(),
1951                                       ES->getValueType(0), TF);
1952
1953  llvm_unreachable("Unhandled address SDNode");
1954}
1955
1956// Split Op into high and low parts according to HiTF and LoTF.
1957// Return an ADD node combining the parts.
1958SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1959                                          unsigned HiTF, unsigned LoTF,
1960                                          SelectionDAG &DAG) const {
1961  SDLoc DL(Op);
1962  EVT VT = Op.getValueType();
1963  SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1964  SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1965  return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1966}
1967
1968// Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1969// or ExternalSymbol SDNode.
1970SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1971  SDLoc DL(Op);
1972  EVT VT = getPointerTy(DAG.getDataLayout());
1973
1974  // Handle PIC mode first. SPARC needs a got load for every variable!
1975  if (isPositionIndependent()) {
1976    // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1977    SDValue HiLo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22,
1978                                SparcMCExpr::VK_Sparc_GOT10, DAG);
1979    SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1980    SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1981    // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1982    // function has calls.
1983    MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1984    MFI->setHasCalls(true);
1985    return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1986                       MachinePointerInfo::getGOT(DAG.getMachineFunction()),
1987                       false, false, false, 0);
1988  }
1989
1990  // This is one of the absolute code models.
1991  switch(getTargetMachine().getCodeModel()) {
1992  default:
1993    llvm_unreachable("Unsupported absolute code model");
1994  case CodeModel::Small:
1995    // abs32.
1996    return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1997                        SparcMCExpr::VK_Sparc_LO, DAG);
1998  case CodeModel::Medium: {
1999    // abs44.
2000    SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44,
2001                               SparcMCExpr::VK_Sparc_M44, DAG);
2002    H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32));
2003    SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG);
2004    L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
2005    return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
2006  }
2007  case CodeModel::Large: {
2008    // abs64.
2009    SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH,
2010                              SparcMCExpr::VK_Sparc_HM, DAG);
2011    Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32));
2012    SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
2013                              SparcMCExpr::VK_Sparc_LO, DAG);
2014    return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
2015  }
2016  }
2017}
2018
2019SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
2020                                                SelectionDAG &DAG) const {
2021  return makeAddress(Op, DAG);
2022}
2023
2024SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
2025                                               SelectionDAG &DAG) const {
2026  return makeAddress(Op, DAG);
2027}
2028
2029SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
2030                                               SelectionDAG &DAG) const {
2031  return makeAddress(Op, DAG);
2032}
2033
2034SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2035                                                   SelectionDAG &DAG) const {
2036
2037  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2038  if (DAG.getTarget().Options.EmulatedTLS)
2039    return LowerToTLSEmulatedModel(GA, DAG);
2040
2041  SDLoc DL(GA);
2042  const GlobalValue *GV = GA->getGlobal();
2043  EVT PtrVT = getPointerTy(DAG.getDataLayout());
2044
2045  TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2046
2047  if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2048    unsigned HiTF = ((model == TLSModel::GeneralDynamic)
2049                     ? SparcMCExpr::VK_Sparc_TLS_GD_HI22
2050                     : SparcMCExpr::VK_Sparc_TLS_LDM_HI22);
2051    unsigned LoTF = ((model == TLSModel::GeneralDynamic)
2052                     ? SparcMCExpr::VK_Sparc_TLS_GD_LO10
2053                     : SparcMCExpr::VK_Sparc_TLS_LDM_LO10);
2054    unsigned addTF = ((model == TLSModel::GeneralDynamic)
2055                      ? SparcMCExpr::VK_Sparc_TLS_GD_ADD
2056                      : SparcMCExpr::VK_Sparc_TLS_LDM_ADD);
2057    unsigned callTF = ((model == TLSModel::GeneralDynamic)
2058                       ? SparcMCExpr::VK_Sparc_TLS_GD_CALL
2059                       : SparcMCExpr::VK_Sparc_TLS_LDM_CALL);
2060
2061    SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
2062    SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
2063    SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
2064                               withTargetFlags(Op, addTF, DAG));
2065
2066    SDValue Chain = DAG.getEntryNode();
2067    SDValue InFlag;
2068
2069    Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, DL, true), DL);
2070    Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
2071    InFlag = Chain.getValue(1);
2072    SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
2073    SDValue Symbol = withTargetFlags(Op, callTF, DAG);
2074
2075    SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2076    const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2077        DAG.getMachineFunction(), CallingConv::C);
2078    assert(Mask && "Missing call preserved mask for calling convention");
2079    SDValue Ops[] = {Chain,
2080                     Callee,
2081                     Symbol,
2082                     DAG.getRegister(SP::O0, PtrVT),
2083                     DAG.getRegisterMask(Mask),
2084                     InFlag};
2085    Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
2086    InFlag = Chain.getValue(1);
2087    Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, DL, true),
2088                               DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2089    InFlag = Chain.getValue(1);
2090    SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
2091
2092    if (model != TLSModel::LocalDynamic)
2093      return Ret;
2094
2095    SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2096                 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG));
2097    SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2098                 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG));
2099    HiLo =  DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2100    return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
2101                   withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG));
2102  }
2103
2104  if (model == TLSModel::InitialExec) {
2105    unsigned ldTF     = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX
2106                         : SparcMCExpr::VK_Sparc_TLS_IE_LD);
2107
2108    SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
2109
2110    // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2111    // function has calls.
2112    MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2113    MFI->setHasCalls(true);
2114
2115    SDValue TGA = makeHiLoPair(Op,
2116                               SparcMCExpr::VK_Sparc_TLS_IE_HI22,
2117                               SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG);
2118    SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
2119    SDValue Offset = DAG.getNode(SPISD::TLS_LD,
2120                                 DL, PtrVT, Ptr,
2121                                 withTargetFlags(Op, ldTF, DAG));
2122    return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
2123                       DAG.getRegister(SP::G7, PtrVT), Offset,
2124                       withTargetFlags(Op,
2125                                       SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG));
2126  }
2127
2128  assert(model == TLSModel::LocalExec);
2129  SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2130                  withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG));
2131  SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2132                  withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG));
2133  SDValue Offset =  DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2134
2135  return DAG.getNode(ISD::ADD, DL, PtrVT,
2136                     DAG.getRegister(SP::G7, PtrVT), Offset);
2137}
2138
2139SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
2140                                                  ArgListTy &Args, SDValue Arg,
2141                                                  const SDLoc &DL,
2142                                                  SelectionDAG &DAG) const {
2143  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2144  EVT ArgVT = Arg.getValueType();
2145  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2146
2147  ArgListEntry Entry;
2148  Entry.Node = Arg;
2149  Entry.Ty   = ArgTy;
2150
2151  if (ArgTy->isFP128Ty()) {
2152    // Create a stack object and pass the pointer to the library function.
2153    int FI = MFI->CreateStackObject(16, 8, false);
2154    SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2155    Chain = DAG.getStore(Chain,
2156                         DL,
2157                         Entry.Node,
2158                         FIPtr,
2159                         MachinePointerInfo(),
2160                         false,
2161                         false,
2162                         8);
2163
2164    Entry.Node = FIPtr;
2165    Entry.Ty   = PointerType::getUnqual(ArgTy);
2166  }
2167  Args.push_back(Entry);
2168  return Chain;
2169}
2170
2171SDValue
2172SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2173                                 const char *LibFuncName,
2174                                 unsigned numArgs) const {
2175
2176  ArgListTy Args;
2177
2178  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2179  auto PtrVT = getPointerTy(DAG.getDataLayout());
2180
2181  SDValue Callee = DAG.getExternalSymbol(LibFuncName, PtrVT);
2182  Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2183  Type *RetTyABI = RetTy;
2184  SDValue Chain = DAG.getEntryNode();
2185  SDValue RetPtr;
2186
2187  if (RetTy->isFP128Ty()) {
2188    // Create a Stack Object to receive the return value of type f128.
2189    ArgListEntry Entry;
2190    int RetFI = MFI->CreateStackObject(16, 8, false);
2191    RetPtr = DAG.getFrameIndex(RetFI, PtrVT);
2192    Entry.Node = RetPtr;
2193    Entry.Ty   = PointerType::getUnqual(RetTy);
2194    if (!Subtarget->is64Bit())
2195      Entry.isSRet = true;
2196    Entry.isReturned = false;
2197    Args.push_back(Entry);
2198    RetTyABI = Type::getVoidTy(*DAG.getContext());
2199  }
2200
2201  assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2202  for (unsigned i = 0, e = numArgs; i != e; ++i) {
2203    Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2204  }
2205  TargetLowering::CallLoweringInfo CLI(DAG);
2206  CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2207    .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args));
2208
2209  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2210
2211  // chain is in second result.
2212  if (RetTyABI == RetTy)
2213    return CallInfo.first;
2214
2215  assert (RetTy->isFP128Ty() && "Unexpected return type!");
2216
2217  Chain = CallInfo.second;
2218
2219  // Load RetPtr to get the return value.
2220  return DAG.getLoad(Op.getValueType(),
2221                     SDLoc(Op),
2222                     Chain,
2223                     RetPtr,
2224                     MachinePointerInfo(),
2225                     false, false, false, 8);
2226}
2227
2228SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2229                                              unsigned &SPCC, const SDLoc &DL,
2230                                              SelectionDAG &DAG) const {
2231
2232  const char *LibCall = nullptr;
2233  bool is64Bit = Subtarget->is64Bit();
2234  switch(SPCC) {
2235  default: llvm_unreachable("Unhandled conditional code!");
2236  case SPCC::FCC_E  : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2237  case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2238  case SPCC::FCC_L  : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2239  case SPCC::FCC_G  : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2240  case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2241  case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2242  case SPCC::FCC_UL :
2243  case SPCC::FCC_ULE:
2244  case SPCC::FCC_UG :
2245  case SPCC::FCC_UGE:
2246  case SPCC::FCC_U  :
2247  case SPCC::FCC_O  :
2248  case SPCC::FCC_LG :
2249  case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2250  }
2251
2252  auto PtrVT = getPointerTy(DAG.getDataLayout());
2253  SDValue Callee = DAG.getExternalSymbol(LibCall, PtrVT);
2254  Type *RetTy = Type::getInt32Ty(*DAG.getContext());
2255  ArgListTy Args;
2256  SDValue Chain = DAG.getEntryNode();
2257  Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2258  Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2259
2260  TargetLowering::CallLoweringInfo CLI(DAG);
2261  CLI.setDebugLoc(DL).setChain(Chain)
2262    .setCallee(CallingConv::C, RetTy, Callee, std::move(Args));
2263
2264  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2265
2266  // result is in first, and chain is in second result.
2267  SDValue Result =  CallInfo.first;
2268
2269  switch(SPCC) {
2270  default: {
2271    SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2272    SPCC = SPCC::ICC_NE;
2273    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2274  }
2275  case SPCC::FCC_UL : {
2276    SDValue Mask   = DAG.getTargetConstant(1, DL, Result.getValueType());
2277    Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2278    SDValue RHS    = DAG.getTargetConstant(0, DL, Result.getValueType());
2279    SPCC = SPCC::ICC_NE;
2280    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2281  }
2282  case SPCC::FCC_ULE: {
2283    SDValue RHS = DAG.getTargetConstant(2, DL, Result.getValueType());
2284    SPCC = SPCC::ICC_NE;
2285    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2286  }
2287  case SPCC::FCC_UG :  {
2288    SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
2289    SPCC = SPCC::ICC_G;
2290    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2291  }
2292  case SPCC::FCC_UGE: {
2293    SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
2294    SPCC = SPCC::ICC_NE;
2295    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2296  }
2297
2298  case SPCC::FCC_U  :  {
2299    SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
2300    SPCC = SPCC::ICC_E;
2301    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2302  }
2303  case SPCC::FCC_O  :  {
2304    SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
2305    SPCC = SPCC::ICC_NE;
2306    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2307  }
2308  case SPCC::FCC_LG :  {
2309    SDValue Mask   = DAG.getTargetConstant(3, DL, Result.getValueType());
2310    Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2311    SDValue RHS    = DAG.getTargetConstant(0, DL, Result.getValueType());
2312    SPCC = SPCC::ICC_NE;
2313    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2314  }
2315  case SPCC::FCC_UE : {
2316    SDValue Mask   = DAG.getTargetConstant(3, DL, Result.getValueType());
2317    Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2318    SDValue RHS    = DAG.getTargetConstant(0, DL, Result.getValueType());
2319    SPCC = SPCC::ICC_E;
2320    return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2321  }
2322  }
2323}
2324
2325static SDValue
2326LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2327                   const SparcTargetLowering &TLI) {
2328
2329  if (Op.getOperand(0).getValueType() == MVT::f64)
2330    return TLI.LowerF128Op(Op, DAG,
2331                           TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2332
2333  if (Op.getOperand(0).getValueType() == MVT::f32)
2334    return TLI.LowerF128Op(Op, DAG,
2335                           TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2336
2337  llvm_unreachable("fpextend with non-float operand!");
2338  return SDValue();
2339}
2340
2341static SDValue
2342LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2343                  const SparcTargetLowering &TLI) {
2344  // FP_ROUND on f64 and f32 are legal.
2345  if (Op.getOperand(0).getValueType() != MVT::f128)
2346    return Op;
2347
2348  if (Op.getValueType() == MVT::f64)
2349    return TLI.LowerF128Op(Op, DAG,
2350                           TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2351  if (Op.getValueType() == MVT::f32)
2352    return TLI.LowerF128Op(Op, DAG,
2353                           TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2354
2355  llvm_unreachable("fpround to non-float!");
2356  return SDValue();
2357}
2358
2359static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2360                               const SparcTargetLowering &TLI,
2361                               bool hasHardQuad) {
2362  SDLoc dl(Op);
2363  EVT VT = Op.getValueType();
2364  assert(VT == MVT::i32 || VT == MVT::i64);
2365
2366  // Expand f128 operations to fp128 abi calls.
2367  if (Op.getOperand(0).getValueType() == MVT::f128
2368      && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2369    const char *libName = TLI.getLibcallName(VT == MVT::i32
2370                                             ? RTLIB::FPTOSINT_F128_I32
2371                                             : RTLIB::FPTOSINT_F128_I64);
2372    return TLI.LowerF128Op(Op, DAG, libName, 1);
2373  }
2374
2375  // Expand if the resulting type is illegal.
2376  if (!TLI.isTypeLegal(VT))
2377    return SDValue();
2378
2379  // Otherwise, Convert the fp value to integer in an FP register.
2380  if (VT == MVT::i32)
2381    Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2382  else
2383    Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2384
2385  return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2386}
2387
2388static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2389                               const SparcTargetLowering &TLI,
2390                               bool hasHardQuad) {
2391  SDLoc dl(Op);
2392  EVT OpVT = Op.getOperand(0).getValueType();
2393  assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2394
2395  EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2396
2397  // Expand f128 operations to fp128 ABI calls.
2398  if (Op.getValueType() == MVT::f128
2399      && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2400    const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2401                                             ? RTLIB::SINTTOFP_I32_F128
2402                                             : RTLIB::SINTTOFP_I64_F128);
2403    return TLI.LowerF128Op(Op, DAG, libName, 1);
2404  }
2405
2406  // Expand if the operand type is illegal.
2407  if (!TLI.isTypeLegal(OpVT))
2408    return SDValue();
2409
2410  // Otherwise, Convert the int value to FP in an FP register.
2411  SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2412  unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2413  return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2414}
2415
2416static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2417                               const SparcTargetLowering &TLI,
2418                               bool hasHardQuad) {
2419  SDLoc dl(Op);
2420  EVT VT = Op.getValueType();
2421
2422  // Expand if it does not involve f128 or the target has support for
2423  // quad floating point instructions and the resulting type is legal.
2424  if (Op.getOperand(0).getValueType() != MVT::f128 ||
2425      (hasHardQuad && TLI.isTypeLegal(VT)))
2426    return SDValue();
2427
2428  assert(VT == MVT::i32 || VT == MVT::i64);
2429
2430  return TLI.LowerF128Op(Op, DAG,
2431                         TLI.getLibcallName(VT == MVT::i32
2432                                            ? RTLIB::FPTOUINT_F128_I32
2433                                            : RTLIB::FPTOUINT_F128_I64),
2434                         1);
2435}
2436
2437static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2438                               const SparcTargetLowering &TLI,
2439                               bool hasHardQuad) {
2440  SDLoc dl(Op);
2441  EVT OpVT = Op.getOperand(0).getValueType();
2442  assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2443
2444  // Expand if it does not involve f128 or the target has support for
2445  // quad floating point instructions and the operand type is legal.
2446  if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2447    return SDValue();
2448
2449  return TLI.LowerF128Op(Op, DAG,
2450                         TLI.getLibcallName(OpVT == MVT::i32
2451                                            ? RTLIB::UINTTOFP_I32_F128
2452                                            : RTLIB::UINTTOFP_I64_F128),
2453                         1);
2454}
2455
2456static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2457                          const SparcTargetLowering &TLI,
2458                          bool hasHardQuad) {
2459  SDValue Chain = Op.getOperand(0);
2460  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2461  SDValue LHS = Op.getOperand(2);
2462  SDValue RHS = Op.getOperand(3);
2463  SDValue Dest = Op.getOperand(4);
2464  SDLoc dl(Op);
2465  unsigned Opc, SPCC = ~0U;
2466
2467  // If this is a br_cc of a "setcc", and if the setcc got lowered into
2468  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2469  LookThroughSetCC(LHS, RHS, CC, SPCC);
2470
2471  // Get the condition flag.
2472  SDValue CompareFlag;
2473  if (LHS.getValueType().isInteger()) {
2474    CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2475    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2476    // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2477    Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
2478  } else {
2479    if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2480      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2481      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2482      Opc = SPISD::BRICC;
2483    } else {
2484      CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2485      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2486      Opc = SPISD::BRFCC;
2487    }
2488  }
2489  return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2490                     DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2491}
2492
2493static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2494                              const SparcTargetLowering &TLI,
2495                              bool hasHardQuad) {
2496  SDValue LHS = Op.getOperand(0);
2497  SDValue RHS = Op.getOperand(1);
2498  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2499  SDValue TrueVal = Op.getOperand(2);
2500  SDValue FalseVal = Op.getOperand(3);
2501  SDLoc dl(Op);
2502  unsigned Opc, SPCC = ~0U;
2503
2504  // If this is a select_cc of a "setcc", and if the setcc got lowered into
2505  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2506  LookThroughSetCC(LHS, RHS, CC, SPCC);
2507
2508  SDValue CompareFlag;
2509  if (LHS.getValueType().isInteger()) {
2510    CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2511    Opc = LHS.getValueType() == MVT::i32 ?
2512          SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2513    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2514  } else {
2515    if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2516      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2517      CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2518      Opc = SPISD::SELECT_ICC;
2519    } else {
2520      CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2521      Opc = SPISD::SELECT_FCC;
2522      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2523    }
2524  }
2525  return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2526                     DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2527}
2528
2529SDValue SparcTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG,
2530    const SparcTargetLowering &TLI) const {
2531  SDLoc DL(Op);
2532  return DAG.getNode(SPISD::EH_SJLJ_SETJMP, DL,
2533      DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0), Op.getOperand(1));
2534
2535}
2536
2537SDValue SparcTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG,
2538    const SparcTargetLowering &TLI) const {
2539  SDLoc DL(Op);
2540  return DAG.getNode(SPISD::EH_SJLJ_LONGJMP, DL, MVT::Other, Op.getOperand(0), Op.getOperand(1));
2541}
2542
2543static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2544                            const SparcTargetLowering &TLI) {
2545  MachineFunction &MF = DAG.getMachineFunction();
2546  SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2547  auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2548
2549  // Need frame address to find the address of VarArgsFrameIndex.
2550  MF.getFrameInfo()->setFrameAddressIsTaken(true);
2551
2552  // vastart just stores the address of the VarArgsFrameIndex slot into the
2553  // memory location argument.
2554  SDLoc DL(Op);
2555  SDValue Offset =
2556      DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT),
2557                  DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
2558  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2559  return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2560                      MachinePointerInfo(SV), false, false, 0);
2561}
2562
2563static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2564  SDNode *Node = Op.getNode();
2565  EVT VT = Node->getValueType(0);
2566  SDValue InChain = Node->getOperand(0);
2567  SDValue VAListPtr = Node->getOperand(1);
2568  EVT PtrVT = VAListPtr.getValueType();
2569  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2570  SDLoc DL(Node);
2571  SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
2572                               MachinePointerInfo(SV), false, false, false, 0);
2573  // Increment the pointer, VAList, to the next vaarg.
2574  SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2575                                DAG.getIntPtrConstant(VT.getSizeInBits()/8,
2576                                                      DL));
2577  // Store the incremented VAList to the legalized pointer.
2578  InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
2579                         VAListPtr, MachinePointerInfo(SV), false, false, 0);
2580  // Load the actual argument out of the pointer VAList.
2581  // We can't count on greater alignment than the word size.
2582  return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2583                     false, false, false,
2584                     std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
2585}
2586
2587static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2588                                       const SparcSubtarget *Subtarget) {
2589  SDValue Chain = Op.getOperand(0);  // Legalize the chain.
2590  SDValue Size  = Op.getOperand(1);  // Legalize the size.
2591  EVT VT = Size->getValueType(0);
2592  SDLoc dl(Op);
2593
2594  unsigned SPReg = SP::O6;
2595  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2596  SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2597  Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP);    // Output chain
2598
2599  // The resultant pointer is actually 16 words from the bottom of the stack,
2600  // to provide a register spill area.
2601  unsigned regSpillArea = Subtarget->is64Bit() ? 128 : 96;
2602  regSpillArea += Subtarget->getStackPointerBias();
2603
2604  SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2605                               DAG.getConstant(regSpillArea, dl, VT));
2606  SDValue Ops[2] = { NewVal, Chain };
2607  return DAG.getMergeValues(Ops, dl);
2608}
2609
2610
2611static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2612  SDLoc dl(Op);
2613  SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2614                              dl, MVT::Other, DAG.getEntryNode());
2615  return Chain;
2616}
2617
2618static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2619                            const SparcSubtarget *Subtarget) {
2620  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2621  MFI->setFrameAddressIsTaken(true);
2622
2623  EVT VT = Op.getValueType();
2624  SDLoc dl(Op);
2625  unsigned FrameReg = SP::I6;
2626  unsigned stackBias = Subtarget->getStackPointerBias();
2627
2628  SDValue FrameAddr;
2629
2630  if (depth == 0) {
2631    FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2632    if (Subtarget->is64Bit())
2633      FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2634                              DAG.getIntPtrConstant(stackBias, dl));
2635    return FrameAddr;
2636  }
2637
2638  // flush first to make sure the windowed registers' values are in stack
2639  SDValue Chain = getFLUSHW(Op, DAG);
2640  FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2641
2642  unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2643
2644  while (depth--) {
2645    SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2646                              DAG.getIntPtrConstant(Offset, dl));
2647    FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(),
2648                            false, false, false, 0);
2649  }
2650  if (Subtarget->is64Bit())
2651    FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2652                            DAG.getIntPtrConstant(stackBias, dl));
2653  return FrameAddr;
2654}
2655
2656
2657static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2658                              const SparcSubtarget *Subtarget) {
2659
2660  uint64_t depth = Op.getConstantOperandVal(0);
2661
2662  return getFRAMEADDR(depth, Op, DAG, Subtarget);
2663}
2664
2665static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2666                               const SparcTargetLowering &TLI,
2667                               const SparcSubtarget *Subtarget) {
2668  MachineFunction &MF = DAG.getMachineFunction();
2669  MachineFrameInfo *MFI = MF.getFrameInfo();
2670  MFI->setReturnAddressIsTaken(true);
2671
2672  if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
2673    return SDValue();
2674
2675  EVT VT = Op.getValueType();
2676  SDLoc dl(Op);
2677  uint64_t depth = Op.getConstantOperandVal(0);
2678
2679  SDValue RetAddr;
2680  if (depth == 0) {
2681    auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2682    unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
2683    RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2684    return RetAddr;
2685  }
2686
2687  // Need frame address to find return address of the caller.
2688  SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget);
2689
2690  unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2691  SDValue Ptr = DAG.getNode(ISD::ADD,
2692                            dl, VT,
2693                            FrameAddr,
2694                            DAG.getIntPtrConstant(Offset, dl));
2695  RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr,
2696                        MachinePointerInfo(), false, false, false, 0);
2697
2698  return RetAddr;
2699}
2700
2701static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG,
2702                          unsigned opcode) {
2703  assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2704  assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2705
2706  // Lower fneg/fabs on f64 to fneg/fabs on f32.
2707  // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2708  // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2709
2710  // Note: in little-endian, the floating-point value is stored in the
2711  // registers are in the opposite order, so the subreg with the sign
2712  // bit is the highest-numbered (odd), rather than the
2713  // lowest-numbered (even).
2714
2715  SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2716                                            SrcReg64);
2717  SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2718                                            SrcReg64);
2719
2720  if (DAG.getDataLayout().isLittleEndian())
2721    Lo32 = DAG.getNode(opcode, dl, MVT::f32, Lo32);
2722  else
2723    Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2724
2725  SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2726                                                dl, MVT::f64), 0);
2727  DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2728                                       DstReg64, Hi32);
2729  DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2730                                       DstReg64, Lo32);
2731  return DstReg64;
2732}
2733
2734// Lower a f128 load into two f64 loads.
2735static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2736{
2737  SDLoc dl(Op);
2738  LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2739  assert(LdNode && LdNode->getOffset().isUndef()
2740         && "Unexpected node type");
2741
2742  unsigned alignment = LdNode->getAlignment();
2743  if (alignment > 8)
2744    alignment = 8;
2745
2746  SDValue Hi64 = DAG.getLoad(MVT::f64,
2747                             dl,
2748                             LdNode->getChain(),
2749                             LdNode->getBasePtr(),
2750                             LdNode->getPointerInfo(),
2751                             false, false, false, alignment);
2752  EVT addrVT = LdNode->getBasePtr().getValueType();
2753  SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2754                              LdNode->getBasePtr(),
2755                              DAG.getConstant(8, dl, addrVT));
2756  SDValue Lo64 = DAG.getLoad(MVT::f64,
2757                             dl,
2758                             LdNode->getChain(),
2759                             LoPtr,
2760                             LdNode->getPointerInfo(),
2761                             false, false, false, alignment);
2762
2763  SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2764  SDValue SubRegOdd  = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2765
2766  SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2767                                       dl, MVT::f128);
2768  InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2769                               MVT::f128,
2770                               SDValue(InFP128, 0),
2771                               Hi64,
2772                               SubRegEven);
2773  InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2774                               MVT::f128,
2775                               SDValue(InFP128, 0),
2776                               Lo64,
2777                               SubRegOdd);
2778  SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2779                           SDValue(Lo64.getNode(), 1) };
2780  SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2781  SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2782  return DAG.getMergeValues(Ops, dl);
2783}
2784
2785static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
2786{
2787  LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
2788
2789  EVT MemVT = LdNode->getMemoryVT();
2790  if (MemVT == MVT::f128)
2791    return LowerF128Load(Op, DAG);
2792
2793  return Op;
2794}
2795
2796// Lower a f128 store into two f64 stores.
2797static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2798  SDLoc dl(Op);
2799  StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2800  assert(StNode && StNode->getOffset().isUndef()
2801         && "Unexpected node type");
2802  SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2803  SDValue SubRegOdd  = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2804
2805  SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2806                                    dl,
2807                                    MVT::f64,
2808                                    StNode->getValue(),
2809                                    SubRegEven);
2810  SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2811                                    dl,
2812                                    MVT::f64,
2813                                    StNode->getValue(),
2814                                    SubRegOdd);
2815
2816  unsigned alignment = StNode->getAlignment();
2817  if (alignment > 8)
2818    alignment = 8;
2819
2820  SDValue OutChains[2];
2821  OutChains[0] = DAG.getStore(StNode->getChain(),
2822                              dl,
2823                              SDValue(Hi64, 0),
2824                              StNode->getBasePtr(),
2825                              MachinePointerInfo(),
2826                              false, false, alignment);
2827  EVT addrVT = StNode->getBasePtr().getValueType();
2828  SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2829                              StNode->getBasePtr(),
2830                              DAG.getConstant(8, dl, addrVT));
2831  OutChains[1] = DAG.getStore(StNode->getChain(),
2832                             dl,
2833                             SDValue(Lo64, 0),
2834                             LoPtr,
2835                             MachinePointerInfo(),
2836                             false, false, alignment);
2837  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2838}
2839
2840static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
2841{
2842  SDLoc dl(Op);
2843  StoreSDNode *St = cast<StoreSDNode>(Op.getNode());
2844
2845  EVT MemVT = St->getMemoryVT();
2846  if (MemVT == MVT::f128)
2847    return LowerF128Store(Op, DAG);
2848
2849  if (MemVT == MVT::i64) {
2850    // Custom handling for i64 stores: turn it into a bitcast and a
2851    // v2i32 store.
2852    SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue());
2853    SDValue Chain = DAG.getStore(
2854        St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(),
2855        St->isVolatile(), St->isNonTemporal(), St->getAlignment(),
2856        St->getAAInfo());
2857    return Chain;
2858  }
2859
2860  return SDValue();
2861}
2862
2863static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2864  assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
2865         && "invalid opcode");
2866
2867  SDLoc dl(Op);
2868
2869  if (Op.getValueType() == MVT::f64)
2870    return LowerF64Op(Op.getOperand(0), dl, DAG, Op.getOpcode());
2871  if (Op.getValueType() != MVT::f128)
2872    return Op;
2873
2874  // Lower fabs/fneg on f128 to fabs/fneg on f64
2875  // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
2876  // (As with LowerF64Op, on little-endian, we need to negate the odd
2877  // subreg)
2878
2879  SDValue SrcReg128 = Op.getOperand(0);
2880  SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2881                                            SrcReg128);
2882  SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2883                                            SrcReg128);
2884
2885  if (DAG.getDataLayout().isLittleEndian()) {
2886    if (isV9)
2887      Lo64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Lo64);
2888    else
2889      Lo64 = LowerF64Op(Lo64, dl, DAG, Op.getOpcode());
2890  } else {
2891    if (isV9)
2892      Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2893    else
2894      Hi64 = LowerF64Op(Hi64, dl, DAG, Op.getOpcode());
2895  }
2896
2897  SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2898                                                 dl, MVT::f128), 0);
2899  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2900                                        DstReg128, Hi64);
2901  DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2902                                        DstReg128, Lo64);
2903  return DstReg128;
2904}
2905
2906static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
2907
2908  if (Op.getValueType() != MVT::i64)
2909    return Op;
2910
2911  SDLoc dl(Op);
2912  SDValue Src1 = Op.getOperand(0);
2913  SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2914  SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
2915                               DAG.getConstant(32, dl, MVT::i64));
2916  Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
2917
2918  SDValue Src2 = Op.getOperand(1);
2919  SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
2920  SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
2921                               DAG.getConstant(32, dl, MVT::i64));
2922  Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
2923
2924
2925  bool hasChain = false;
2926  unsigned hiOpc = Op.getOpcode();
2927  switch (Op.getOpcode()) {
2928  default: llvm_unreachable("Invalid opcode");
2929  case ISD::ADDC: hiOpc = ISD::ADDE; break;
2930  case ISD::ADDE: hasChain = true; break;
2931  case ISD::SUBC: hiOpc = ISD::SUBE; break;
2932  case ISD::SUBE: hasChain = true; break;
2933  }
2934  SDValue Lo;
2935  SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
2936  if (hasChain) {
2937    Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2938                     Op.getOperand(2));
2939  } else {
2940    Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2941  }
2942  SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2943  SDValue Carry = Hi.getValue(1);
2944
2945  Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2946  Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
2947  Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
2948                   DAG.getConstant(32, dl, MVT::i64));
2949
2950  SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
2951  SDValue Ops[2] = { Dst, Carry };
2952  return DAG.getMergeValues(Ops, dl);
2953}
2954
2955// Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2956// in LegalizeDAG.cpp except the order of arguments to the library function.
2957static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
2958                                const SparcTargetLowering &TLI)
2959{
2960  unsigned opcode = Op.getOpcode();
2961  assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
2962
2963  bool isSigned = (opcode == ISD::SMULO);
2964  EVT VT = MVT::i64;
2965  EVT WideVT = MVT::i128;
2966  SDLoc dl(Op);
2967  SDValue LHS = Op.getOperand(0);
2968
2969  if (LHS.getValueType() != VT)
2970    return Op;
2971
2972  SDValue ShiftAmt = DAG.getConstant(63, dl, VT);
2973
2974  SDValue RHS = Op.getOperand(1);
2975  SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
2976  SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
2977  SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
2978
2979  SDValue MulResult = TLI.makeLibCall(DAG,
2980                                      RTLIB::MUL_I128, WideVT,
2981                                      Args, isSigned, dl).first;
2982  SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2983                                   MulResult, DAG.getIntPtrConstant(0, dl));
2984  SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2985                                MulResult, DAG.getIntPtrConstant(1, dl));
2986  if (isSigned) {
2987    SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
2988    TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
2989  } else {
2990    TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT),
2991                           ISD::SETNE);
2992  }
2993  // MulResult is a node with an illegal type. Because such things are not
2994  // generally permitted during this phase of legalization, ensure that
2995  // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have
2996  // been folded.
2997  assert(MulResult->use_empty() && "Illegally typed node still in use!");
2998
2999  SDValue Ops[2] = { BottomHalf, TopHalf } ;
3000  return DAG.getMergeValues(Ops, dl);
3001}
3002
3003static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
3004  if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getOrdering()))
3005  // Expand with a fence.
3006  return SDValue();
3007
3008  // Monotonic load/stores are legal.
3009  return Op;
3010}
3011
3012SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3013                                                     SelectionDAG &DAG) const {
3014  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3015  SDLoc dl(Op);
3016  switch (IntNo) {
3017  default: return SDValue();    // Don't custom lower most intrinsics.
3018  case Intrinsic::thread_pointer: {
3019    EVT PtrVT = getPointerTy(DAG.getDataLayout());
3020    return DAG.getRegister(SP::G7, PtrVT);
3021  }
3022  }
3023}
3024
3025SDValue SparcTargetLowering::
3026LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3027
3028  bool hasHardQuad = Subtarget->hasHardQuad();
3029  bool isV9        = Subtarget->isV9();
3030
3031  switch (Op.getOpcode()) {
3032  default: llvm_unreachable("Should not custom lower this!");
3033
3034  case ISD::RETURNADDR:         return LowerRETURNADDR(Op, DAG, *this,
3035                                                       Subtarget);
3036  case ISD::FRAMEADDR:          return LowerFRAMEADDR(Op, DAG,
3037                                                      Subtarget);
3038  case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
3039  case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
3040  case ISD::BlockAddress:       return LowerBlockAddress(Op, DAG);
3041  case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
3042  case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG, *this,
3043                                                       hasHardQuad);
3044  case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG, *this,
3045                                                       hasHardQuad);
3046  case ISD::FP_TO_UINT:         return LowerFP_TO_UINT(Op, DAG, *this,
3047                                                       hasHardQuad);
3048  case ISD::UINT_TO_FP:         return LowerUINT_TO_FP(Op, DAG, *this,
3049                                                       hasHardQuad);
3050  case ISD::BR_CC:              return LowerBR_CC(Op, DAG, *this,
3051                                                  hasHardQuad);
3052  case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG, *this,
3053                                                      hasHardQuad);
3054  case ISD::EH_SJLJ_SETJMP:     return LowerEH_SJLJ_SETJMP(Op, DAG, *this);
3055  case ISD::EH_SJLJ_LONGJMP:    return LowerEH_SJLJ_LONGJMP(Op, DAG, *this);
3056  case ISD::VASTART:            return LowerVASTART(Op, DAG, *this);
3057  case ISD::VAARG:              return LowerVAARG(Op, DAG);
3058  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
3059                                                               Subtarget);
3060
3061  case ISD::LOAD:               return LowerLOAD(Op, DAG);
3062  case ISD::STORE:              return LowerSTORE(Op, DAG);
3063  case ISD::FADD:               return LowerF128Op(Op, DAG,
3064                                       getLibcallName(RTLIB::ADD_F128), 2);
3065  case ISD::FSUB:               return LowerF128Op(Op, DAG,
3066                                       getLibcallName(RTLIB::SUB_F128), 2);
3067  case ISD::FMUL:               return LowerF128Op(Op, DAG,
3068                                       getLibcallName(RTLIB::MUL_F128), 2);
3069  case ISD::FDIV:               return LowerF128Op(Op, DAG,
3070                                       getLibcallName(RTLIB::DIV_F128), 2);
3071  case ISD::FSQRT:              return LowerF128Op(Op, DAG,
3072                                       getLibcallName(RTLIB::SQRT_F128),1);
3073  case ISD::FABS:
3074  case ISD::FNEG:               return LowerFNEGorFABS(Op, DAG, isV9);
3075  case ISD::FP_EXTEND:          return LowerF128_FPEXTEND(Op, DAG, *this);
3076  case ISD::FP_ROUND:           return LowerF128_FPROUND(Op, DAG, *this);
3077  case ISD::ADDC:
3078  case ISD::ADDE:
3079  case ISD::SUBC:
3080  case ISD::SUBE:               return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
3081  case ISD::UMULO:
3082  case ISD::SMULO:              return LowerUMULO_SMULO(Op, DAG, *this);
3083  case ISD::ATOMIC_LOAD:
3084  case ISD::ATOMIC_STORE:       return LowerATOMIC_LOAD_STORE(Op, DAG);
3085  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3086  }
3087}
3088
3089MachineBasicBlock *
3090SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3091                                                 MachineBasicBlock *BB) const {
3092  switch (MI.getOpcode()) {
3093  default: llvm_unreachable("Unknown Custom Instruction!");
3094  case SP::SELECT_CC_Int_ICC:
3095  case SP::SELECT_CC_FP_ICC:
3096  case SP::SELECT_CC_DFP_ICC:
3097  case SP::SELECT_CC_QFP_ICC:
3098    return expandSelectCC(MI, BB, SP::BCOND);
3099  case SP::SELECT_CC_Int_FCC:
3100  case SP::SELECT_CC_FP_FCC:
3101  case SP::SELECT_CC_DFP_FCC:
3102  case SP::SELECT_CC_QFP_FCC:
3103    return expandSelectCC(MI, BB, SP::FBCOND);
3104  case SP::EH_SJLJ_SETJMP32ri:
3105  case SP::EH_SJLJ_SETJMP32rr:
3106    return emitEHSjLjSetJmp(MI, BB);
3107  case SP::EH_SJLJ_LONGJMP32rr:
3108  case SP::EH_SJLJ_LONGJMP32ri:
3109    return emitEHSjLjLongJmp(MI, BB);
3110  }
3111}
3112
3113MachineBasicBlock *
3114SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
3115                                    unsigned BROpcode) const {
3116  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3117  DebugLoc dl = MI.getDebugLoc();
3118  unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm();
3119
3120  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
3121  // control-flow pattern.  The incoming instruction knows the destination vreg
3122  // to set, the condition code register to branch on, the true/false values to
3123  // select between, and a branch opcode to use.
3124  const BasicBlock *LLVM_BB = BB->getBasicBlock();
3125  MachineFunction::iterator It = ++BB->getIterator();
3126
3127  //  thisMBB:
3128  //  ...
3129  //   TrueVal = ...
3130  //   [f]bCC copy1MBB
3131  //   fallthrough --> copy0MBB
3132  MachineBasicBlock *thisMBB = BB;
3133  MachineFunction *F = BB->getParent();
3134  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3135  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3136  F->insert(It, copy0MBB);
3137  F->insert(It, sinkMBB);
3138
3139  // Transfer the remainder of BB and its successor edges to sinkMBB.
3140  sinkMBB->splice(sinkMBB->begin(), BB,
3141                  std::next(MachineBasicBlock::iterator(MI)),
3142                  BB->end());
3143  sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3144
3145  // Add the true and fallthrough blocks as its successors.
3146  BB->addSuccessor(copy0MBB);
3147  BB->addSuccessor(sinkMBB);
3148
3149  BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
3150
3151  //  copy0MBB:
3152  //   %FalseValue = ...
3153  //   # fallthrough to sinkMBB
3154  BB = copy0MBB;
3155
3156  // Update machine-CFG edges
3157  BB->addSuccessor(sinkMBB);
3158
3159  //  sinkMBB:
3160  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3161  //  ...
3162  BB = sinkMBB;
3163  BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI.getOperand(0).getReg())
3164      .addReg(MI.getOperand(2).getReg())
3165      .addMBB(copy0MBB)
3166      .addReg(MI.getOperand(1).getReg())
3167      .addMBB(thisMBB);
3168
3169  MI.eraseFromParent(); // The pseudo instruction is gone now.
3170  return BB;
3171}
3172
3173MachineBasicBlock *
3174SparcTargetLowering::emitEHSjLjLongJmp(MachineInstr &MI,
3175                                       MachineBasicBlock *MBB) const {
3176  DebugLoc DL = MI.getDebugLoc();
3177  const TargetInstrInfo *TII = Subtarget->getInstrInfo();
3178
3179  MachineFunction *MF = MBB->getParent();
3180  MachineRegisterInfo &MRI = MF->getRegInfo();
3181  MachineInstrBuilder MIB;
3182
3183  MVT PVT = getPointerTy(MF->getDataLayout());
3184  unsigned RegSize = PVT.getStoreSize();
3185  assert(PVT == MVT::i32 && "Invalid Pointer Size!");
3186
3187  unsigned Buf = MI.getOperand(0).getReg();
3188  unsigned JmpLoc = MRI.createVirtualRegister(&SP::IntRegsRegClass);
3189
3190  // TO DO: If we do 64-bit handling, this perhaps should be FLUSHW, not TA 3
3191  MIB = BuildMI(*MBB, MI, DL, TII->get(SP::TRAPri), SP::G0).addImm(3).addImm(SPCC::ICC_A);
3192
3193  // Instruction to restore FP
3194  const unsigned FP  = SP::I6;
3195  MIB = BuildMI(*MBB, MI, DL, TII->get(SP::LDri))
3196            .addReg(FP)
3197            .addReg(Buf)
3198            .addImm(0);
3199
3200  // Instruction to load jmp location
3201  MIB = BuildMI(*MBB, MI, DL, TII->get(SP::LDri))
3202            .addReg(JmpLoc, RegState::Define)
3203            .addReg(Buf)
3204            .addImm(RegSize);
3205
3206  // Instruction to restore SP
3207  const unsigned SP  = SP::O6;
3208  MIB = BuildMI(*MBB, MI, DL, TII->get(SP::LDri))
3209            .addReg(SP)
3210            .addReg(Buf)
3211            .addImm(2 * RegSize);
3212
3213  // Instruction to restore I7
3214  MIB = BuildMI(*MBB, MI, DL, TII->get(SP::LDri))
3215            .addReg(SP::I7)
3216            .addReg(Buf, RegState::Kill)
3217            .addImm(3 * RegSize);
3218
3219  // Jump to JmpLoc
3220  BuildMI(*MBB, MI, DL, TII->get(SP::JMPLrr)).addReg(SP::G0).addReg(JmpLoc, RegState::Kill).addReg(SP::G0);
3221
3222  MI.eraseFromParent();
3223  return MBB;
3224}
3225
3226MachineBasicBlock *
3227SparcTargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
3228                                      MachineBasicBlock *MBB) const {
3229  DebugLoc DL = MI.getDebugLoc();
3230  const TargetInstrInfo *TII = Subtarget->getInstrInfo();
3231
3232  MachineFunction *MF = MBB->getParent();
3233  MachineRegisterInfo &MRI = MF->getRegInfo();
3234  MachineInstrBuilder MIB;
3235
3236  MVT PVT = getPointerTy(MF->getDataLayout());
3237  unsigned RegSize = PVT.getStoreSize();
3238  assert(PVT == MVT::i32 && "Invalid Pointer Size!");
3239
3240  unsigned DstReg = MI.getOperand(0).getReg();
3241  const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
3242  assert(RC->hasType(MVT::i32) && "Invalid destination!");
3243  unsigned mainDstReg = MRI.createVirtualRegister(RC);
3244  unsigned restoreDstReg = MRI.createVirtualRegister(RC);
3245
3246  // For v = setjmp(buf), we generate
3247  //
3248  // thisMBB:
3249  //  buf[0] = FP
3250  //  buf[RegSize] = restoreMBB <-- takes address of restoreMBB
3251  //  buf[RegSize * 2] = O6
3252  //  buf[RegSize * 3] = I7
3253  //  Ensure restoreMBB remains in the relocations list (done using a bn instruction)
3254  //  b mainMBB
3255  //
3256  // mainMBB:
3257  //  v_main = 0
3258  //  b sinkMBB
3259  //
3260  // restoreMBB:
3261  //  v_restore = 1
3262  //  --fall through--
3263  //
3264  // sinkMBB:
3265  //  v = phi(main, restore)
3266
3267  const BasicBlock *BB = MBB->getBasicBlock();
3268  MachineFunction::iterator It = ++MBB->getIterator();
3269  MachineBasicBlock *thisMBB = MBB;
3270  MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
3271  MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
3272  MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
3273
3274  MF->insert(It, mainMBB);
3275  MF->insert(It, restoreMBB);
3276  MF->insert(It, sinkMBB);
3277  restoreMBB->setHasAddressTaken();
3278
3279  // Transfer the remainder of BB and its successor edges to sinkMBB.
3280  sinkMBB->splice(sinkMBB->begin(), MBB,
3281                  std::next(MachineBasicBlock::iterator(MI)),
3282                  MBB->end());
3283  sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
3284
3285  unsigned LabelReg = MRI.createVirtualRegister(&SP::IntRegsRegClass);
3286  unsigned LabelReg2 = MRI.createVirtualRegister(&SP::IntRegsRegClass);
3287  unsigned BufReg = MI.getOperand(1).getReg();
3288
3289  // Instruction to store FP
3290  const unsigned FP  = SP::I6;
3291  MIB = BuildMI(thisMBB, DL, TII->get(SP::STri))
3292            .addReg(BufReg)
3293            .addImm(0)
3294            .addReg(FP);
3295
3296  // Instructions to store jmp location
3297  MIB = BuildMI(thisMBB, DL, TII->get(SP::SETHIi))
3298            .addReg(LabelReg, RegState::Define)
3299            .addMBB(restoreMBB, SparcMCExpr::VK_Sparc_HI);
3300
3301  MIB = BuildMI(thisMBB, DL, TII->get(SP::ORri))
3302            .addReg(LabelReg2, RegState::Define)
3303            .addReg(LabelReg, RegState::Kill)
3304            .addMBB(restoreMBB, SparcMCExpr::VK_Sparc_LO);
3305
3306  MIB = BuildMI(thisMBB, DL, TII->get(SP::STri))
3307            .addReg(BufReg)
3308            .addImm(RegSize)
3309            .addReg(LabelReg2, RegState::Kill);
3310
3311  // Instruction to store SP
3312  const unsigned SP  = SP::O6;
3313  MIB = BuildMI(thisMBB, DL, TII->get(SP::STri))
3314            .addReg(BufReg)
3315            .addImm(2 * RegSize)
3316            .addReg(SP);
3317
3318  // Instruction to store I7
3319  MIB = BuildMI(thisMBB, DL, TII->get(SP::STri))
3320            .addReg(BufReg)
3321            .addImm(3 * RegSize)
3322            .addReg(SP::I7);
3323
3324
3325  // FIX ME: This next instruction ensures that the restoreMBB block address remains
3326  // valid through optimization passes and serves no other purpose. The ICC_N ensures
3327  // that the branch is never taken. This commented-out code here was an alternative
3328  // attempt to achieve this which brought myriad problems.
3329  //MIB = BuildMI(thisMBB, DL, TII->get(SP::EH_SjLj_Setup)).addMBB(restoreMBB, SparcMCExpr::VK_Sparc_None);
3330  MIB = BuildMI(thisMBB, DL, TII->get(SP::BCOND))
3331              .addMBB(restoreMBB)
3332              .addImm(SPCC::ICC_N);
3333
3334  MIB = BuildMI(thisMBB, DL, TII->get(SP::BCOND))
3335              .addMBB(mainMBB)
3336              .addImm(SPCC::ICC_A);
3337
3338  thisMBB->addSuccessor(mainMBB);
3339  thisMBB->addSuccessor(restoreMBB);
3340
3341
3342  // mainMBB:
3343  MIB = BuildMI(mainMBB, DL, TII->get(SP::ORrr))
3344             .addReg(mainDstReg, RegState::Define)
3345             .addReg(SP::G0)
3346             .addReg(SP::G0);
3347  MIB = BuildMI(mainMBB, DL, TII->get(SP::BCOND)).addMBB(sinkMBB).addImm(SPCC::ICC_A);
3348
3349  mainMBB->addSuccessor(sinkMBB);
3350
3351
3352  // restoreMBB:
3353  MIB = BuildMI(restoreMBB, DL, TII->get(SP::ORri))
3354              .addReg(restoreDstReg, RegState::Define)
3355              .addReg(SP::G0)
3356              .addImm(1);
3357  //MIB = BuildMI(restoreMBB, DL, TII->get(SP::BCOND)).addMBB(sinkMBB).addImm(SPCC::ICC_A);
3358  restoreMBB->addSuccessor(sinkMBB);
3359
3360  // sinkMBB:
3361  MIB = BuildMI(*sinkMBB, sinkMBB->begin(), DL,
3362                TII->get(SP::PHI), DstReg)
3363             .addReg(mainDstReg).addMBB(mainMBB)
3364             .addReg(restoreDstReg).addMBB(restoreMBB);
3365
3366  MI.eraseFromParent();
3367  return sinkMBB;
3368}
3369
3370//===----------------------------------------------------------------------===//
3371//                         Sparc Inline Assembly Support
3372//===----------------------------------------------------------------------===//
3373
3374/// getConstraintType - Given a constraint letter, return the type of
3375/// constraint it is for this target.
3376SparcTargetLowering::ConstraintType
3377SparcTargetLowering::getConstraintType(StringRef Constraint) const {
3378  if (Constraint.size() == 1) {
3379    switch (Constraint[0]) {
3380    default:
3381      break;
3382    case 'f':
3383    case 'r':
3384      return C_RegisterClass;
3385    case 'I': // SIMM13
3386      return C_Other;
3387    }
3388  }
3389
3390  return TargetLowering::getConstraintType(Constraint);
3391}
3392
3393TargetLowering::ConstraintWeight SparcTargetLowering::
3394getSingleConstraintMatchWeight(AsmOperandInfo &info,
3395                               const char *constraint) const {
3396  ConstraintWeight weight = CW_Invalid;
3397  Value *CallOperandVal = info.CallOperandVal;
3398  // If we don't have a value, we can't do a match,
3399  // but allow it at the lowest weight.
3400  if (!CallOperandVal)
3401    return CW_Default;
3402
3403  // Look at the constraint type.
3404  switch (*constraint) {
3405  default:
3406    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3407    break;
3408  case 'I': // SIMM13
3409    if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3410      if (isInt<13>(C->getSExtValue()))
3411        weight = CW_Constant;
3412    }
3413    break;
3414  }
3415  return weight;
3416}
3417
3418/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3419/// vector.  If it is invalid, don't add anything to Ops.
3420void SparcTargetLowering::
3421LowerAsmOperandForConstraint(SDValue Op,
3422                             std::string &Constraint,
3423                             std::vector<SDValue> &Ops,
3424                             SelectionDAG &DAG) const {
3425  SDValue Result(nullptr, 0);
3426
3427  // Only support length 1 constraints for now.
3428  if (Constraint.length() > 1)
3429    return;
3430
3431  char ConstraintLetter = Constraint[0];
3432  switch (ConstraintLetter) {
3433  default: break;
3434  case 'I':
3435    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3436      if (isInt<13>(C->getSExtValue())) {
3437        Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
3438                                       Op.getValueType());
3439        break;
3440      }
3441      return;
3442    }
3443  }
3444
3445  if (Result.getNode()) {
3446    Ops.push_back(Result);
3447    return;
3448  }
3449  TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3450}
3451
3452std::pair<unsigned, const TargetRegisterClass *>
3453SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3454                                                  StringRef Constraint,
3455                                                  MVT VT) const {
3456  if (Constraint.size() == 1) {
3457    switch (Constraint[0]) {
3458    case 'f':
3459      return std::make_pair(0U, &SP::FPRegsRegClass);
3460
3461    case 'r':
3462      if (VT == MVT::v2i32)
3463        return std::make_pair(0U, &SP::IntPairRegClass);
3464      else
3465        return std::make_pair(0U, &SP::IntRegsRegClass);
3466    }
3467  } else if (!Constraint.empty() && Constraint.size() <= 5
3468              && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
3469    // constraint = '{r<d>}'
3470    // Remove the braces from around the name.
3471    StringRef name(Constraint.data()+1, Constraint.size()-2);
3472    // Handle register aliases:
3473    //       r0-r7   -> g0-g7
3474    //       r8-r15  -> o0-o7
3475    //       r16-r23 -> l0-l7
3476    //       r24-r31 -> i0-i7
3477    uint64_t intVal = 0;
3478    if (name.substr(0, 1).equals("r")
3479        && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3480      const char regTypes[] = { 'g', 'o', 'l', 'i' };
3481      char regType = regTypes[intVal/8];
3482      char regIdx = '0' + (intVal % 8);
3483      char tmp[] = { '{', regType, regIdx, '}', 0 };
3484      std::string newConstraint = std::string(tmp);
3485      return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint,
3486                                                          VT);
3487    }
3488  }
3489
3490  return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3491}
3492
3493bool
3494SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3495  // The Sparc target isn't yet aware of offsets.
3496  return false;
3497}
3498
3499void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3500                                             SmallVectorImpl<SDValue>& Results,
3501                                             SelectionDAG &DAG) const {
3502
3503  SDLoc dl(N);
3504
3505  RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3506
3507  switch (N->getOpcode()) {
3508  default:
3509    llvm_unreachable("Do not know how to custom type legalize this operation!");
3510
3511  case ISD::FP_TO_SINT:
3512  case ISD::FP_TO_UINT:
3513    // Custom lower only if it involves f128 or i64.
3514    if (N->getOperand(0).getValueType() != MVT::f128
3515        || N->getValueType(0) != MVT::i64)
3516      return;
3517    libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3518               ? RTLIB::FPTOSINT_F128_I64
3519               : RTLIB::FPTOUINT_F128_I64);
3520
3521    Results.push_back(LowerF128Op(SDValue(N, 0),
3522                                  DAG,
3523                                  getLibcallName(libCall),
3524                                  1));
3525    return;
3526
3527  case ISD::SINT_TO_FP:
3528  case ISD::UINT_TO_FP:
3529    // Custom lower only if it involves f128 or i64.
3530    if (N->getValueType(0) != MVT::f128
3531        || N->getOperand(0).getValueType() != MVT::i64)
3532      return;
3533
3534    libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3535               ? RTLIB::SINTTOFP_I64_F128
3536               : RTLIB::UINTTOFP_I64_F128);
3537
3538    Results.push_back(LowerF128Op(SDValue(N, 0),
3539                                  DAG,
3540                                  getLibcallName(libCall),
3541                                  1));
3542    return;
3543  case ISD::LOAD: {
3544    LoadSDNode *Ld = cast<LoadSDNode>(N);
3545    // Custom handling only for i64: turn i64 load into a v2i32 load,
3546    // and a bitcast.
3547    if (Ld->getValueType(0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64)
3548      return;
3549
3550    SDLoc dl(N);
3551    SDValue LoadRes = DAG.getExtLoad(
3552        Ld->getExtensionType(), dl, MVT::v2i32,
3553        Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3554        MVT::v2i32, Ld->isVolatile(), Ld->isNonTemporal(),
3555        Ld->isInvariant(), Ld->getAlignment(), Ld->getAAInfo());
3556
3557    SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes);
3558    Results.push_back(Res);
3559    Results.push_back(LoadRes.getValue(1));
3560    return;
3561  }
3562  }
3563}
3564
3565// Override to enable LOAD_STACK_GUARD lowering on Linux.
3566bool SparcTargetLowering::useLoadStackGuardNode() const {
3567  if (!Subtarget->isTargetLinux())
3568    return TargetLowering::useLoadStackGuardNode();
3569  return true;
3570}
3571
3572// Override to disable global variable loading on Linux.
3573void SparcTargetLowering::insertSSPDeclarations(Module &M) const {
3574  if (!Subtarget->isTargetLinux())
3575    return TargetLowering::insertSSPDeclarations(M);
3576}
3577