1; RUN: llc -march=amdgcn -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s
2; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s
3 ;
4; There is something about Tonga that causes this test to spend a lot of time
5; in the default register allocator.
6
7
8; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
9; is used to calculate the scratch load/store address. Make sure that this
10; mechanism works even when many spills happen.
11
12; Just test that it compiles successfully.
13; CHECK-LABEL: test
14define void @test(<1280 x i32> addrspace(1)* %out, <1280 x i32> addrspace(1)* %in) {
15entry:
16  %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
17  %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
18
19  %aptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %in, i32 %tid
20  %a = load <1280 x i32>, <1280 x i32> addrspace(1)* %aptr
21
22; mark most VGPR registers as used to increase register pressure
23  call void asm sideeffect "", "~{VGPR4},~{VGPR8},~{VGPR12},~{VGPR16},~{VGPR20},~{VGPR24},~{VGPR28},~{VGPR32}" ()
24  call void asm sideeffect "", "~{VGPR36},~{VGPR40},~{VGPR44},~{VGPR48},~{VGPR52},~{VGPR56},~{VGPR60},~{VGPR64}" ()
25  call void asm sideeffect "", "~{VGPR68},~{VGPR72},~{VGPR76},~{VGPR80},~{VGPR84},~{VGPR88},~{VGPR92},~{VGPR96}" ()
26  call void asm sideeffect "", "~{VGPR100},~{VGPR104},~{VGPR108},~{VGPR112},~{VGPR116},~{VGPR120},~{VGPR124},~{VGPR128}" ()
27  call void asm sideeffect "", "~{VGPR132},~{VGPR136},~{VGPR140},~{VGPR144},~{VGPR148},~{VGPR152},~{VGPR156},~{VGPR160}" ()
28  call void asm sideeffect "", "~{VGPR164},~{VGPR168},~{VGPR172},~{VGPR176},~{VGPR180},~{VGPR184},~{VGPR188},~{VGPR192}" ()
29  call void asm sideeffect "", "~{VGPR196},~{VGPR200},~{VGPR204},~{VGPR208},~{VGPR212},~{VGPR216},~{VGPR220},~{VGPR224}" ()
30
31  %outptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %out, i32 %tid
32  store <1280 x i32> %a, <1280 x i32> addrspace(1)* %outptr
33
34  ret void
35}
36
37declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
38declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1
39
40attributes #1 = { nounwind readnone }
41