1/* 2 * Copyright © 2016 Red Hat. 3 * Copyright © 2016 Bas Nieuwenhuizen 4 * 5 * Based on radeon_winsys.h which is: 6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 7 * Copyright 2010 Marek Olšák <maraeo@gmail.com> 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the next 17 * paragraph) shall be included in all copies or substantial portions of the 18 * Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 26 * IN THE SOFTWARE. 27 */ 28 29#ifndef RADV_RADEON_WINSYS_H 30#define RADV_RADEON_WINSYS_H 31 32#include <stdint.h> 33#include <stdbool.h> 34#include <stdlib.h> 35#include "main/macros.h" 36#include "amd_family.h" 37 38#define FREE(x) free(x) 39 40enum radeon_bo_domain { /* bitfield */ 41 RADEON_DOMAIN_GTT = 2, 42 RADEON_DOMAIN_VRAM = 4, 43 RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT 44}; 45 46enum radeon_bo_flag { /* bitfield */ 47 RADEON_FLAG_GTT_WC = (1 << 0), 48 RADEON_FLAG_CPU_ACCESS = (1 << 1), 49 RADEON_FLAG_NO_CPU_ACCESS = (1 << 2), 50}; 51 52enum radeon_bo_usage { /* bitfield */ 53 RADEON_USAGE_READ = 2, 54 RADEON_USAGE_WRITE = 4, 55 RADEON_USAGE_READWRITE = RADEON_USAGE_READ | RADEON_USAGE_WRITE 56}; 57 58enum ring_type { 59 RING_GFX = 0, 60 RING_COMPUTE, 61 RING_DMA, 62 RING_UVD, 63 RING_VCE, 64 RING_LAST, 65}; 66 67struct radeon_winsys_cs { 68 unsigned cdw; /* Number of used dwords. */ 69 unsigned max_dw; /* Maximum number of dwords. */ 70 uint32_t *buf; /* The base pointer of the chunk. */ 71}; 72 73struct radeon_info { 74 /* PCI info: domain:bus:dev:func */ 75 uint32_t pci_domain; 76 uint32_t pci_bus; 77 uint32_t pci_dev; 78 uint32_t pci_func; 79 80 /* Device info. */ 81 uint32_t pci_id; 82 enum radeon_family family; 83 const char *name; 84 enum chip_class chip_class; 85 uint32_t gart_page_size; 86 uint64_t gart_size; 87 uint64_t vram_size; 88 uint64_t visible_vram_size; 89 bool has_dedicated_vram; 90 bool has_virtual_memory; 91 bool gfx_ib_pad_with_type2; 92 bool has_uvd; 93 uint32_t sdma_rings; 94 uint32_t compute_rings; 95 uint32_t vce_fw_version; 96 uint32_t vce_harvest_config; 97 uint32_t clock_crystal_freq; 98 99 /* Kernel info. */ 100 uint32_t drm_major; /* version */ 101 uint32_t drm_minor; 102 uint32_t drm_patchlevel; 103 bool has_userptr; 104 105 /* Shader cores. */ 106 uint32_t r600_max_quad_pipes; /* wave size / 16 */ 107 uint32_t max_shader_clock; 108 uint32_t num_good_compute_units; 109 uint32_t max_se; /* shader engines */ 110 uint32_t max_sh_per_se; /* shader arrays per shader engine */ 111 112 /* Render backends (color + depth blocks). */ 113 uint32_t r300_num_gb_pipes; 114 uint32_t r300_num_z_pipes; 115 uint32_t r600_gb_backend_map; /* R600 harvest config */ 116 bool r600_gb_backend_map_valid; 117 uint32_t r600_num_banks; 118 uint32_t num_render_backends; 119 uint32_t num_tile_pipes; /* pipe count from PIPE_CONFIG */ 120 uint32_t pipe_interleave_bytes; 121 uint32_t enabled_rb_mask; /* GCN harvest config */ 122 123 /* Tile modes. */ 124 uint32_t si_tile_mode_array[32]; 125 uint32_t cik_macrotile_mode_array[16]; 126}; 127 128#define RADEON_SURF_MAX_LEVEL 32 129 130#define RADEON_SURF_TYPE_MASK 0xFF 131#define RADEON_SURF_TYPE_SHIFT 0 132#define RADEON_SURF_TYPE_1D 0 133#define RADEON_SURF_TYPE_2D 1 134#define RADEON_SURF_TYPE_3D 2 135#define RADEON_SURF_TYPE_CUBEMAP 3 136#define RADEON_SURF_TYPE_1D_ARRAY 4 137#define RADEON_SURF_TYPE_2D_ARRAY 5 138#define RADEON_SURF_MODE_MASK 0xFF 139#define RADEON_SURF_MODE_SHIFT 8 140#define RADEON_SURF_MODE_LINEAR_ALIGNED 1 141#define RADEON_SURF_MODE_1D 2 142#define RADEON_SURF_MODE_2D 3 143#define RADEON_SURF_SCANOUT (1 << 16) 144#define RADEON_SURF_ZBUFFER (1 << 17) 145#define RADEON_SURF_SBUFFER (1 << 18) 146#define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) 147#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19) 148#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20) 149#define RADEON_SURF_FMASK (1 << 21) 150#define RADEON_SURF_DISABLE_DCC (1 << 22) 151 152#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) 153#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) 154#define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT)) 155 156struct radeon_surf_level { 157 uint64_t offset; 158 uint64_t slice_size; 159 uint32_t npix_x; 160 uint32_t npix_y; 161 uint32_t npix_z; 162 uint32_t nblk_x; 163 uint32_t nblk_y; 164 uint32_t nblk_z; 165 uint32_t pitch_bytes; 166 uint32_t mode; 167 uint64_t dcc_offset; 168 uint64_t dcc_fast_clear_size; 169 bool dcc_enabled; 170}; 171 172 173/* surface defintions from the winsys */ 174struct radeon_surf { 175 /* These are inputs to the calculator. */ 176 uint32_t npix_x; 177 uint32_t npix_y; 178 uint32_t npix_z; 179 uint32_t blk_w; 180 uint32_t blk_h; 181 uint32_t blk_d; 182 uint32_t array_size; 183 uint32_t last_level; 184 uint32_t bpe; 185 uint32_t nsamples; 186 uint32_t flags; 187 188 /* These are return values. Some of them can be set by the caller, but 189 * they will be treated as hints (e.g. bankw, bankh) and might be 190 * changed by the calculator. 191 */ 192 uint64_t bo_size; 193 uint64_t bo_alignment; 194 /* This applies to EG and later. */ 195 uint32_t bankw; 196 uint32_t bankh; 197 uint32_t mtilea; 198 uint32_t tile_split; 199 uint32_t stencil_tile_split; 200 uint64_t stencil_offset; 201 struct radeon_surf_level level[RADEON_SURF_MAX_LEVEL]; 202 struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL]; 203 uint32_t tiling_index[RADEON_SURF_MAX_LEVEL]; 204 uint32_t stencil_tiling_index[RADEON_SURF_MAX_LEVEL]; 205 uint32_t pipe_config; 206 uint32_t num_banks; 207 uint32_t macro_tile_index; 208 uint32_t micro_tile_mode; /* displayable, thin, depth, rotated */ 209 210 /* Whether the depth miptree or stencil miptree as used by the DB are 211 * adjusted from their TC compatible form to ensure depth/stencil 212 * compatibility. If either is true, the corresponding plane cannot be 213 * sampled from. 214 */ 215 bool depth_adjusted; 216 bool stencil_adjusted; 217 218 uint64_t dcc_size; 219 uint64_t dcc_alignment; 220}; 221 222enum radeon_bo_layout { 223 RADEON_LAYOUT_LINEAR = 0, 224 RADEON_LAYOUT_TILED, 225 RADEON_LAYOUT_SQUARETILED, 226 227 RADEON_LAYOUT_UNKNOWN 228}; 229 230/* Tiling info for display code, DRI sharing, and other data. */ 231struct radeon_bo_metadata { 232 /* Tiling flags describing the texture layout for display code 233 * and DRI sharing. 234 */ 235 enum radeon_bo_layout microtile; 236 enum radeon_bo_layout macrotile; 237 unsigned pipe_config; 238 unsigned bankw; 239 unsigned bankh; 240 unsigned tile_split; 241 unsigned mtilea; 242 unsigned num_banks; 243 unsigned stride; 244 bool scanout; 245 246 /* Additional metadata associated with the buffer, in bytes. 247 * The maximum size is 64 * 4. This is opaque for the winsys & kernel. 248 * Supported by amdgpu only. 249 */ 250 uint32_t size_metadata; 251 uint32_t metadata[64]; 252}; 253 254struct radeon_winsys_bo; 255struct radeon_winsys_fence; 256struct radeon_winsys_sem; 257 258struct radeon_winsys { 259 void (*destroy)(struct radeon_winsys *ws); 260 261 void (*query_info)(struct radeon_winsys *ws, 262 struct radeon_info *info); 263 264 struct radeon_winsys_bo *(*buffer_create)(struct radeon_winsys *ws, 265 uint64_t size, 266 unsigned alignment, 267 enum radeon_bo_domain domain, 268 enum radeon_bo_flag flags); 269 270 void (*buffer_destroy)(struct radeon_winsys_bo *bo); 271 void *(*buffer_map)(struct radeon_winsys_bo *bo); 272 273 struct radeon_winsys_bo *(*buffer_from_fd)(struct radeon_winsys *ws, 274 int fd, 275 unsigned *stride, unsigned *offset); 276 277 bool (*buffer_get_fd)(struct radeon_winsys *ws, 278 struct radeon_winsys_bo *bo, 279 int *fd); 280 281 void (*buffer_unmap)(struct radeon_winsys_bo *bo); 282 283 uint64_t (*buffer_get_va)(struct radeon_winsys_bo *bo); 284 285 void (*buffer_set_metadata)(struct radeon_winsys_bo *bo, 286 struct radeon_bo_metadata *md); 287 struct radeon_winsys_ctx *(*ctx_create)(struct radeon_winsys *ws); 288 void (*ctx_destroy)(struct radeon_winsys_ctx *ctx); 289 290 bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, 291 enum ring_type ring_type, int ring_index); 292 293 struct radeon_winsys_cs *(*cs_create)(struct radeon_winsys *ws, 294 enum ring_type ring_type); 295 296 void (*cs_destroy)(struct radeon_winsys_cs *cs); 297 298 void (*cs_reset)(struct radeon_winsys_cs *cs); 299 300 bool (*cs_finalize)(struct radeon_winsys_cs *cs); 301 302 void (*cs_grow)(struct radeon_winsys_cs * cs, size_t min_size); 303 304 int (*cs_submit)(struct radeon_winsys_ctx *ctx, 305 int queue_index, 306 struct radeon_winsys_cs **cs_array, 307 unsigned cs_count, 308 struct radeon_winsys_sem **wait_sem, 309 unsigned wait_sem_count, 310 struct radeon_winsys_sem **signal_sem, 311 unsigned signal_sem_count, 312 bool can_patch, 313 struct radeon_winsys_fence *fence); 314 315 void (*cs_add_buffer)(struct radeon_winsys_cs *cs, 316 struct radeon_winsys_bo *bo, 317 uint8_t priority); 318 319 void (*cs_execute_secondary)(struct radeon_winsys_cs *parent, 320 struct radeon_winsys_cs *child); 321 322 void (*cs_dump)(struct radeon_winsys_cs *cs, FILE* file, uint32_t trace_id); 323 324 int (*surface_init)(struct radeon_winsys *ws, 325 struct radeon_surf *surf); 326 327 int (*surface_best)(struct radeon_winsys *ws, 328 struct radeon_surf *surf); 329 330 struct radeon_winsys_fence *(*create_fence)(); 331 void (*destroy_fence)(struct radeon_winsys_fence *fence); 332 bool (*fence_wait)(struct radeon_winsys *ws, 333 struct radeon_winsys_fence *fence, 334 bool absolute, 335 uint64_t timeout); 336 337 struct radeon_winsys_sem *(*create_sem)(struct radeon_winsys *ws); 338 void (*destroy_sem)(struct radeon_winsys_sem *sem); 339 340}; 341 342static inline void radeon_emit(struct radeon_winsys_cs *cs, uint32_t value) 343{ 344 cs->buf[cs->cdw++] = value; 345} 346 347static inline void radeon_emit_array(struct radeon_winsys_cs *cs, 348 const uint32_t *values, unsigned count) 349{ 350 memcpy(cs->buf + cs->cdw, values, count * 4); 351 cs->cdw += count; 352} 353 354#endif /* RADV_RADEON_WINSYS_H */ 355