si_state.c revision 603c073ec2b0ae4be82326992f11d39be45f54c8
1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Christian König <christian.koenig@amd.com> 25 */ 26 27#include "si_pipe.h" 28#include "si_shader.h" 29#include "sid.h" 30#include "radeon/r600_cs.h" 31 32#include "util/u_dual_blend.h" 33#include "util/u_format.h" 34#include "util/u_format_s3tc.h" 35#include "util/u_memory.h" 36#include "util/u_pstipple.h" 37#include "util/u_resource.h" 38 39/* Initialize an external atom (owned by ../radeon). */ 40static void 41si_init_external_atom(struct si_context *sctx, struct r600_atom *atom, 42 struct r600_atom **list_elem) 43{ 44 atom->id = list_elem - sctx->atoms.array + 1; 45 *list_elem = atom; 46} 47 48/* Initialize an atom owned by radeonsi. */ 49void si_init_atom(struct si_context *sctx, struct r600_atom *atom, 50 struct r600_atom **list_elem, 51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state)) 52{ 53 atom->emit = (void*)emit_func; 54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */ 55 *list_elem = atom; 56} 57 58static unsigned si_map_swizzle(unsigned swizzle) 59{ 60 switch (swizzle) { 61 case PIPE_SWIZZLE_Y: 62 return V_008F0C_SQ_SEL_Y; 63 case PIPE_SWIZZLE_Z: 64 return V_008F0C_SQ_SEL_Z; 65 case PIPE_SWIZZLE_W: 66 return V_008F0C_SQ_SEL_W; 67 case PIPE_SWIZZLE_0: 68 return V_008F0C_SQ_SEL_0; 69 case PIPE_SWIZZLE_1: 70 return V_008F0C_SQ_SEL_1; 71 default: /* PIPE_SWIZZLE_X */ 72 return V_008F0C_SQ_SEL_X; 73 } 74} 75 76static uint32_t S_FIXED(float value, uint32_t frac_bits) 77{ 78 return value * (1 << frac_bits); 79} 80 81/* 12.4 fixed-point */ 82static unsigned si_pack_float_12p4(float x) 83{ 84 return x <= 0 ? 0 : 85 x >= 4096 ? 0xffff : x * 16; 86} 87 88/* 89 * Inferred framebuffer and blender state. 90 * 91 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state 92 * is that: 93 * - The blend state mask is 0xf most of the time. 94 * - The COLOR1 format isn't INVALID because of possible dual-source blending, 95 * so COLOR1 is enabled pretty much all the time. 96 * So CB_TARGET_MASK is the only register that can disable COLOR1. 97 * 98 * Another reason is to avoid a hang with dual source blending. 99 */ 100static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom) 101{ 102 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 103 struct si_state_blend *blend = sctx->queued.named.blend; 104 uint32_t cb_target_mask = 0, i; 105 106 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) 107 if (sctx->framebuffer.state.cbufs[i]) 108 cb_target_mask |= 0xf << (4*i); 109 110 if (blend) 111 cb_target_mask &= blend->cb_target_mask; 112 113 /* Avoid a hang that happens when dual source blending is enabled 114 * but there is not enough color outputs. This is undefined behavior, 115 * so disable color writes completely. 116 * 117 * Reproducible with Unigine Heaven 4.0 and drirc missing. 118 */ 119 if (blend && blend->dual_src_blend && 120 sctx->ps_shader.cso && 121 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3) 122 cb_target_mask = 0; 123 124 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask); 125 126 /* STONEY-specific register settings. */ 127 if (sctx->b.family == CHIP_STONEY) { 128 unsigned spi_shader_col_format = 129 sctx->ps_shader.cso ? 130 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0; 131 unsigned sx_ps_downconvert = 0; 132 unsigned sx_blend_opt_epsilon = 0; 133 unsigned sx_blend_opt_control = 0; 134 135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) { 136 struct r600_surface *surf = 137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i]; 138 unsigned format, swap, spi_format, colormask; 139 bool has_alpha, has_rgb; 140 141 if (!surf) 142 continue; 143 144 format = G_028C70_FORMAT(surf->cb_color_info); 145 swap = G_028C70_COMP_SWAP(surf->cb_color_info); 146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf; 147 colormask = (cb_target_mask >> (i * 4)) & 0xf; 148 149 /* Set if RGB and A are present. */ 150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib); 151 152 if (format == V_028C70_COLOR_8 || 153 format == V_028C70_COLOR_16 || 154 format == V_028C70_COLOR_32) 155 has_rgb = !has_alpha; 156 else 157 has_rgb = true; 158 159 /* Check the colormask and export format. */ 160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A))) 161 has_rgb = false; 162 if (!(colormask & PIPE_MASK_A)) 163 has_alpha = false; 164 165 if (spi_format == V_028714_SPI_SHADER_ZERO) { 166 has_rgb = false; 167 has_alpha = false; 168 } 169 170 /* Disable value checking for disabled channels. */ 171 if (!has_rgb) 172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4); 173 if (!has_alpha) 174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4); 175 176 /* Enable down-conversion for 32bpp and smaller formats. */ 177 switch (format) { 178 case V_028C70_COLOR_8: 179 case V_028C70_COLOR_8_8: 180 case V_028C70_COLOR_8_8_8_8: 181 /* For 1 and 2-channel formats, use the superset thereof. */ 182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR || 183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR || 184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) { 185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4); 186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4); 187 } 188 break; 189 190 case V_028C70_COLOR_5_6_5: 191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) { 192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4); 193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4); 194 } 195 break; 196 197 case V_028C70_COLOR_1_5_5_5: 198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) { 199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4); 200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4); 201 } 202 break; 203 204 case V_028C70_COLOR_4_4_4_4: 205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) { 206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4); 207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4); 208 } 209 break; 210 211 case V_028C70_COLOR_32: 212 if (swap == V_0280A0_SWAP_STD && 213 spi_format == V_028714_SPI_SHADER_32_R) 214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4); 215 else if (swap == V_0280A0_SWAP_ALT_REV && 216 spi_format == V_028714_SPI_SHADER_32_AR) 217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4); 218 break; 219 220 case V_028C70_COLOR_16: 221 case V_028C70_COLOR_16_16: 222 /* For 1-channel formats, use the superset thereof. */ 223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR || 224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR || 225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR || 226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) { 227 if (swap == V_0280A0_SWAP_STD || 228 swap == V_0280A0_SWAP_STD_REV) 229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4); 230 else 231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4); 232 } 233 break; 234 235 case V_028C70_COLOR_10_11_11: 236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) { 237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4); 238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4); 239 } 240 break; 241 242 case V_028C70_COLOR_2_10_10_10: 243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) { 244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4); 245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4); 246 } 247 break; 248 } 249 } 250 251 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) { 252 sx_ps_downconvert = 0; 253 sx_blend_opt_epsilon = 0; 254 sx_blend_opt_control = 0; 255 } 256 257 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3); 258 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */ 259 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */ 260 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */ 261 } 262} 263 264/* 265 * Blender functions 266 */ 267 268static uint32_t si_translate_blend_function(int blend_func) 269{ 270 switch (blend_func) { 271 case PIPE_BLEND_ADD: 272 return V_028780_COMB_DST_PLUS_SRC; 273 case PIPE_BLEND_SUBTRACT: 274 return V_028780_COMB_SRC_MINUS_DST; 275 case PIPE_BLEND_REVERSE_SUBTRACT: 276 return V_028780_COMB_DST_MINUS_SRC; 277 case PIPE_BLEND_MIN: 278 return V_028780_COMB_MIN_DST_SRC; 279 case PIPE_BLEND_MAX: 280 return V_028780_COMB_MAX_DST_SRC; 281 default: 282 R600_ERR("Unknown blend function %d\n", blend_func); 283 assert(0); 284 break; 285 } 286 return 0; 287} 288 289static uint32_t si_translate_blend_factor(int blend_fact) 290{ 291 switch (blend_fact) { 292 case PIPE_BLENDFACTOR_ONE: 293 return V_028780_BLEND_ONE; 294 case PIPE_BLENDFACTOR_SRC_COLOR: 295 return V_028780_BLEND_SRC_COLOR; 296 case PIPE_BLENDFACTOR_SRC_ALPHA: 297 return V_028780_BLEND_SRC_ALPHA; 298 case PIPE_BLENDFACTOR_DST_ALPHA: 299 return V_028780_BLEND_DST_ALPHA; 300 case PIPE_BLENDFACTOR_DST_COLOR: 301 return V_028780_BLEND_DST_COLOR; 302 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 303 return V_028780_BLEND_SRC_ALPHA_SATURATE; 304 case PIPE_BLENDFACTOR_CONST_COLOR: 305 return V_028780_BLEND_CONSTANT_COLOR; 306 case PIPE_BLENDFACTOR_CONST_ALPHA: 307 return V_028780_BLEND_CONSTANT_ALPHA; 308 case PIPE_BLENDFACTOR_ZERO: 309 return V_028780_BLEND_ZERO; 310 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 311 return V_028780_BLEND_ONE_MINUS_SRC_COLOR; 312 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 313 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; 314 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 315 return V_028780_BLEND_ONE_MINUS_DST_ALPHA; 316 case PIPE_BLENDFACTOR_INV_DST_COLOR: 317 return V_028780_BLEND_ONE_MINUS_DST_COLOR; 318 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 319 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; 320 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 321 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; 322 case PIPE_BLENDFACTOR_SRC1_COLOR: 323 return V_028780_BLEND_SRC1_COLOR; 324 case PIPE_BLENDFACTOR_SRC1_ALPHA: 325 return V_028780_BLEND_SRC1_ALPHA; 326 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 327 return V_028780_BLEND_INV_SRC1_COLOR; 328 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 329 return V_028780_BLEND_INV_SRC1_ALPHA; 330 default: 331 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 332 assert(0); 333 break; 334 } 335 return 0; 336} 337 338static uint32_t si_translate_blend_opt_function(int blend_func) 339{ 340 switch (blend_func) { 341 case PIPE_BLEND_ADD: 342 return V_028760_OPT_COMB_ADD; 343 case PIPE_BLEND_SUBTRACT: 344 return V_028760_OPT_COMB_SUBTRACT; 345 case PIPE_BLEND_REVERSE_SUBTRACT: 346 return V_028760_OPT_COMB_REVSUBTRACT; 347 case PIPE_BLEND_MIN: 348 return V_028760_OPT_COMB_MIN; 349 case PIPE_BLEND_MAX: 350 return V_028760_OPT_COMB_MAX; 351 default: 352 return V_028760_OPT_COMB_BLEND_DISABLED; 353 } 354} 355 356static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha) 357{ 358 switch (blend_fact) { 359 case PIPE_BLENDFACTOR_ZERO: 360 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL; 361 case PIPE_BLENDFACTOR_ONE: 362 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE; 363 case PIPE_BLENDFACTOR_SRC_COLOR: 364 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0 365 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0; 366 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1 368 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1; 369 case PIPE_BLENDFACTOR_SRC_ALPHA: 370 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0; 371 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 372 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1; 373 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 374 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE 375 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0; 376 default: 377 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; 378 } 379} 380 381/** 382 * Get rid of DST in the blend factors by commuting the operands: 383 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC) 384 */ 385static void si_blend_remove_dst(unsigned *func, unsigned *src_factor, 386 unsigned *dst_factor, unsigned expected_dst, 387 unsigned replacement_src) 388{ 389 if (*src_factor == expected_dst && 390 *dst_factor == PIPE_BLENDFACTOR_ZERO) { 391 *src_factor = PIPE_BLENDFACTOR_ZERO; 392 *dst_factor = replacement_src; 393 394 /* Commuting the operands requires reversing subtractions. */ 395 if (*func == PIPE_BLEND_SUBTRACT) 396 *func = PIPE_BLEND_REVERSE_SUBTRACT; 397 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT) 398 *func = PIPE_BLEND_SUBTRACT; 399 } 400} 401 402static bool si_blend_factor_uses_dst(unsigned factor) 403{ 404 return factor == PIPE_BLENDFACTOR_DST_COLOR || 405 factor == PIPE_BLENDFACTOR_DST_ALPHA || 406 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 407 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA || 408 factor == PIPE_BLENDFACTOR_INV_DST_COLOR; 409} 410 411static void *si_create_blend_state_mode(struct pipe_context *ctx, 412 const struct pipe_blend_state *state, 413 unsigned mode) 414{ 415 struct si_context *sctx = (struct si_context*)ctx; 416 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend); 417 struct si_pm4_state *pm4 = &blend->pm4; 418 uint32_t sx_mrt_blend_opt[8] = {0}; 419 uint32_t color_control = 0; 420 421 if (!blend) 422 return NULL; 423 424 blend->alpha_to_coverage = state->alpha_to_coverage; 425 blend->alpha_to_one = state->alpha_to_one; 426 blend->dual_src_blend = util_blend_state_is_dual(state, 0); 427 428 if (state->logicop_enable) { 429 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4)); 430 } else { 431 color_control |= S_028808_ROP3(0xcc); 432 } 433 434 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 435 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) | 436 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | 437 S_028B70_ALPHA_TO_MASK_OFFSET1(2) | 438 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | 439 S_028B70_ALPHA_TO_MASK_OFFSET3(2)); 440 441 if (state->alpha_to_coverage) 442 blend->need_src_alpha_4bit |= 0xf; 443 444 blend->cb_target_mask = 0; 445 for (int i = 0; i < 8; i++) { 446 /* state->rt entries > 0 only written if independent blending */ 447 const int j = state->independent_blend_enable ? i : 0; 448 449 unsigned eqRGB = state->rt[j].rgb_func; 450 unsigned srcRGB = state->rt[j].rgb_src_factor; 451 unsigned dstRGB = state->rt[j].rgb_dst_factor; 452 unsigned eqA = state->rt[j].alpha_func; 453 unsigned srcA = state->rt[j].alpha_src_factor; 454 unsigned dstA = state->rt[j].alpha_dst_factor; 455 456 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt; 457 unsigned blend_cntl = 0; 458 459 sx_mrt_blend_opt[i] = 460 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | 461 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED); 462 463 if (!state->rt[j].colormask) 464 continue; 465 466 /* cb_render_state will disable unused ones */ 467 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i); 468 469 if (!state->rt[j].blend_enable) { 470 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 471 continue; 472 } 473 474 /* Blending optimizations for Stoney. 475 * These transformations don't change the behavior. 476 * 477 * First, get rid of DST in the blend factors: 478 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC) 479 */ 480 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB, 481 PIPE_BLENDFACTOR_DST_COLOR, 482 PIPE_BLENDFACTOR_SRC_COLOR); 483 si_blend_remove_dst(&eqA, &srcA, &dstA, 484 PIPE_BLENDFACTOR_DST_COLOR, 485 PIPE_BLENDFACTOR_SRC_COLOR); 486 si_blend_remove_dst(&eqA, &srcA, &dstA, 487 PIPE_BLENDFACTOR_DST_ALPHA, 488 PIPE_BLENDFACTOR_SRC_ALPHA); 489 490 /* Look up the ideal settings from tables. */ 491 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false); 492 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false); 493 srcA_opt = si_translate_blend_opt_factor(srcA, true); 494 dstA_opt = si_translate_blend_opt_factor(dstA, true); 495 496 /* Handle interdependencies. */ 497 if (si_blend_factor_uses_dst(srcRGB)) 498 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; 499 if (si_blend_factor_uses_dst(srcA)) 500 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; 501 502 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE && 503 (dstRGB == PIPE_BLENDFACTOR_ZERO || 504 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 505 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE)) 506 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0; 507 508 /* Set the final value. */ 509 sx_mrt_blend_opt[i] = 510 S_028760_COLOR_SRC_OPT(srcRGB_opt) | 511 S_028760_COLOR_DST_OPT(dstRGB_opt) | 512 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) | 513 S_028760_ALPHA_SRC_OPT(srcA_opt) | 514 S_028760_ALPHA_DST_OPT(dstA_opt) | 515 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA)); 516 517 /* Set blend state. */ 518 blend_cntl |= S_028780_ENABLE(1); 519 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); 520 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); 521 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); 522 523 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 524 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); 525 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); 526 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); 527 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); 528 } 529 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 530 531 blend->blend_enable_4bit |= 0xfu << (i * 4); 532 533 /* This is only important for formats without alpha. */ 534 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 535 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 536 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 537 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 538 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 539 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA) 540 blend->need_src_alpha_4bit |= 0xfu << (i * 4); 541 } 542 543 if (blend->cb_target_mask) { 544 color_control |= S_028808_MODE(mode); 545 } else { 546 color_control |= S_028808_MODE(V_028808_CB_DISABLE); 547 } 548 549 if (sctx->b.family == CHIP_STONEY) { 550 for (int i = 0; i < 8; i++) 551 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, 552 sx_mrt_blend_opt[i]); 553 554 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */ 555 if (blend->dual_src_blend || state->logicop_enable || 556 mode == V_028808_CB_RESOLVE) 557 color_control |= S_028808_DISABLE_DUAL_QUAD(1); 558 } 559 560 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); 561 return blend; 562} 563 564static void *si_create_blend_state(struct pipe_context *ctx, 565 const struct pipe_blend_state *state) 566{ 567 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL); 568} 569 570static void si_bind_blend_state(struct pipe_context *ctx, void *state) 571{ 572 struct si_context *sctx = (struct si_context *)ctx; 573 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state); 574 si_mark_atom_dirty(sctx, &sctx->cb_render_state); 575} 576 577static void si_delete_blend_state(struct pipe_context *ctx, void *state) 578{ 579 struct si_context *sctx = (struct si_context *)ctx; 580 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state); 581} 582 583static void si_set_blend_color(struct pipe_context *ctx, 584 const struct pipe_blend_color *state) 585{ 586 struct si_context *sctx = (struct si_context *)ctx; 587 588 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0) 589 return; 590 591 sctx->blend_color.state = *state; 592 si_mark_atom_dirty(sctx, &sctx->blend_color.atom); 593} 594 595static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom) 596{ 597 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 598 599 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4); 600 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4); 601} 602 603/* 604 * Clipping 605 */ 606 607static void si_set_clip_state(struct pipe_context *ctx, 608 const struct pipe_clip_state *state) 609{ 610 struct si_context *sctx = (struct si_context *)ctx; 611 struct pipe_constant_buffer cb; 612 613 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0) 614 return; 615 616 sctx->clip_state.state = *state; 617 si_mark_atom_dirty(sctx, &sctx->clip_state.atom); 618 619 cb.buffer = NULL; 620 cb.user_buffer = state->ucp; 621 cb.buffer_offset = 0; 622 cb.buffer_size = 4*4*8; 623 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb); 624 pipe_resource_reference(&cb.buffer, NULL); 625} 626 627static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom) 628{ 629 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 630 631 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4); 632 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4); 633} 634 635#define SIX_BITS 0x3F 636 637static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom) 638{ 639 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 640 struct tgsi_shader_info *info = si_get_vs_info(sctx); 641 unsigned window_space = 642 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION]; 643 unsigned clipdist_mask = 644 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask; 645 646 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL, 647 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) | 648 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) | 649 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) | 650 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) | 651 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) | 652 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) | 653 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize || 654 info->writes_edgeflag || 655 info->writes_layer || 656 info->writes_viewport_index) | 657 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) | 658 (sctx->queued.named.rasterizer->clip_plane_enable & 659 clipdist_mask)); 660 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, 661 sctx->queued.named.rasterizer->pa_cl_clip_cntl | 662 (clipdist_mask ? 0 : 663 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) | 664 S_028810_CLIP_DISABLE(window_space)); 665 666 /* reuse needs to be set off if we write oViewport */ 667 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF, 668 S_028AB4_REUSE_OFF(info->writes_viewport_index)); 669} 670 671/* 672 * inferred state between framebuffer and rasterizer 673 */ 674static void si_update_poly_offset_state(struct si_context *sctx) 675{ 676 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 677 678 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) 679 return; 680 681 switch (sctx->framebuffer.state.zsbuf->texture->format) { 682 case PIPE_FORMAT_Z16_UNORM: 683 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]); 684 break; 685 default: /* 24-bit */ 686 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]); 687 break; 688 case PIPE_FORMAT_Z32_FLOAT: 689 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 690 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]); 691 break; 692 } 693} 694 695/* 696 * Rasterizer 697 */ 698 699static uint32_t si_translate_fill(uint32_t func) 700{ 701 switch(func) { 702 case PIPE_POLYGON_MODE_FILL: 703 return V_028814_X_DRAW_TRIANGLES; 704 case PIPE_POLYGON_MODE_LINE: 705 return V_028814_X_DRAW_LINES; 706 case PIPE_POLYGON_MODE_POINT: 707 return V_028814_X_DRAW_POINTS; 708 default: 709 assert(0); 710 return V_028814_X_DRAW_POINTS; 711 } 712} 713 714static void *si_create_rs_state(struct pipe_context *ctx, 715 const struct pipe_rasterizer_state *state) 716{ 717 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer); 718 struct si_pm4_state *pm4 = &rs->pm4; 719 unsigned tmp, i; 720 float psize_min, psize_max; 721 722 if (!rs) { 723 return NULL; 724 } 725 726 rs->scissor_enable = state->scissor; 727 rs->two_side = state->light_twoside; 728 rs->multisample_enable = state->multisample; 729 rs->force_persample_interp = state->force_persample_interp; 730 rs->clip_plane_enable = state->clip_plane_enable; 731 rs->line_stipple_enable = state->line_stipple_enable; 732 rs->poly_stipple_enable = state->poly_stipple_enable; 733 rs->line_smooth = state->line_smooth; 734 rs->poly_smooth = state->poly_smooth; 735 rs->uses_poly_offset = state->offset_point || state->offset_line || 736 state->offset_tri; 737 rs->clamp_fragment_color = state->clamp_fragment_color; 738 rs->flatshade = state->flatshade; 739 rs->sprite_coord_enable = state->sprite_coord_enable; 740 rs->rasterizer_discard = state->rasterizer_discard; 741 rs->pa_sc_line_stipple = state->line_stipple_enable ? 742 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 743 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 744 rs->pa_cl_clip_cntl = 745 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) | 746 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 747 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 748 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) | 749 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 750 751 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, 752 S_0286D4_FLAT_SHADE_ENA(1) | 753 S_0286D4_PNT_SPRITE_ENA(1) | 754 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | 755 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | 756 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | 757 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) | 758 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT)); 759 760 /* point size 12.4 fixed point */ 761 tmp = (unsigned)(state->point_size * 8.0); 762 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 763 764 if (state->point_size_per_vertex) { 765 psize_min = util_get_min_point_size(state); 766 psize_max = 8192; 767 } else { 768 /* Force the point size to be as if the vertex output was disabled. */ 769 psize_min = state->point_size; 770 psize_max = state->point_size; 771 } 772 /* Divide by two, because 0.5 = 1 pixel. */ 773 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX, 774 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) | 775 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2))); 776 777 tmp = (unsigned)state->line_width * 8; 778 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); 779 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0, 780 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) | 781 S_028A48_MSAA_ENABLE(state->multisample || 782 state->poly_smooth || 783 state->line_smooth) | 784 S_028A48_VPORT_SCISSOR_ENABLE(1)); 785 786 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL, 787 S_028BE4_PIX_CENTER(state->half_pixel_center) | 788 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH)); 789 790 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 791 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, 792 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) | 793 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 794 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 795 S_028814_FACE(!state->front_ccw) | 796 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) | 797 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) | 798 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) | 799 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL || 800 state->fill_back != PIPE_POLYGON_MODE_FILL) | 801 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | 802 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back))); 803 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + 804 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color); 805 806 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */ 807 for (i = 0; i < 3; i++) { 808 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i]; 809 float offset_units = state->offset_units; 810 float offset_scale = state->offset_scale * 16.0f; 811 812 switch (i) { 813 case 0: /* 16-bit zbuffer */ 814 offset_units *= 4.0f; 815 break; 816 case 1: /* 24-bit zbuffer */ 817 offset_units *= 2.0f; 818 break; 819 case 2: /* 32-bit zbuffer */ 820 offset_units *= 1.0f; 821 break; 822 } 823 824 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 825 fui(offset_scale)); 826 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 827 fui(offset_units)); 828 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 829 fui(offset_scale)); 830 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 831 fui(offset_units)); 832 } 833 834 return rs; 835} 836 837static void si_bind_rs_state(struct pipe_context *ctx, void *state) 838{ 839 struct si_context *sctx = (struct si_context *)ctx; 840 struct si_state_rasterizer *old_rs = 841 (struct si_state_rasterizer*)sctx->queued.named.rasterizer; 842 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state; 843 844 if (!state) 845 return; 846 847 if (sctx->framebuffer.nr_samples > 1 && 848 (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) 849 si_mark_atom_dirty(sctx, &sctx->db_render_state); 850 851 r600_set_scissor_enable(&sctx->b, rs->scissor_enable); 852 853 si_pm4_bind_state(sctx, rasterizer, rs); 854 si_update_poly_offset_state(sctx); 855 856 si_mark_atom_dirty(sctx, &sctx->clip_regs); 857} 858 859static void si_delete_rs_state(struct pipe_context *ctx, void *state) 860{ 861 struct si_context *sctx = (struct si_context *)ctx; 862 863 if (sctx->queued.named.rasterizer == state) 864 si_pm4_bind_state(sctx, poly_offset, NULL); 865 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state); 866} 867 868/* 869 * infeered state between dsa and stencil ref 870 */ 871static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom) 872{ 873 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 874 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state; 875 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part; 876 877 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2); 878 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) | 879 S_028430_STENCILMASK(dsa->valuemask[0]) | 880 S_028430_STENCILWRITEMASK(dsa->writemask[0]) | 881 S_028430_STENCILOPVAL(1)); 882 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) | 883 S_028434_STENCILMASK_BF(dsa->valuemask[1]) | 884 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) | 885 S_028434_STENCILOPVAL_BF(1)); 886} 887 888static void si_set_stencil_ref(struct pipe_context *ctx, 889 const struct pipe_stencil_ref *state) 890{ 891 struct si_context *sctx = (struct si_context *)ctx; 892 893 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0) 894 return; 895 896 sctx->stencil_ref.state = *state; 897 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom); 898} 899 900 901/* 902 * DSA 903 */ 904 905static uint32_t si_translate_stencil_op(int s_op) 906{ 907 switch (s_op) { 908 case PIPE_STENCIL_OP_KEEP: 909 return V_02842C_STENCIL_KEEP; 910 case PIPE_STENCIL_OP_ZERO: 911 return V_02842C_STENCIL_ZERO; 912 case PIPE_STENCIL_OP_REPLACE: 913 return V_02842C_STENCIL_REPLACE_TEST; 914 case PIPE_STENCIL_OP_INCR: 915 return V_02842C_STENCIL_ADD_CLAMP; 916 case PIPE_STENCIL_OP_DECR: 917 return V_02842C_STENCIL_SUB_CLAMP; 918 case PIPE_STENCIL_OP_INCR_WRAP: 919 return V_02842C_STENCIL_ADD_WRAP; 920 case PIPE_STENCIL_OP_DECR_WRAP: 921 return V_02842C_STENCIL_SUB_WRAP; 922 case PIPE_STENCIL_OP_INVERT: 923 return V_02842C_STENCIL_INVERT; 924 default: 925 R600_ERR("Unknown stencil op %d", s_op); 926 assert(0); 927 break; 928 } 929 return 0; 930} 931 932static void *si_create_dsa_state(struct pipe_context *ctx, 933 const struct pipe_depth_stencil_alpha_state *state) 934{ 935 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa); 936 struct si_pm4_state *pm4 = &dsa->pm4; 937 unsigned db_depth_control; 938 uint32_t db_stencil_control = 0; 939 940 if (!dsa) { 941 return NULL; 942 } 943 944 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask; 945 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask; 946 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask; 947 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask; 948 949 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 950 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 951 S_028800_ZFUNC(state->depth.func) | 952 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test); 953 954 /* stencil */ 955 if (state->stencil[0].enabled) { 956 db_depth_control |= S_028800_STENCIL_ENABLE(1); 957 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); 958 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op)); 959 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op)); 960 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op)); 961 962 if (state->stencil[1].enabled) { 963 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 964 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); 965 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op)); 966 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op)); 967 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op)); 968 } 969 } 970 971 /* alpha */ 972 if (state->alpha.enabled) { 973 dsa->alpha_func = state->alpha.func; 974 975 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 + 976 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value)); 977 } else { 978 dsa->alpha_func = PIPE_FUNC_ALWAYS; 979 } 980 981 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); 982 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); 983 if (state->depth.bounds_test) { 984 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min)); 985 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max)); 986 } 987 988 return dsa; 989} 990 991static void si_bind_dsa_state(struct pipe_context *ctx, void *state) 992{ 993 struct si_context *sctx = (struct si_context *)ctx; 994 struct si_state_dsa *dsa = state; 995 996 if (!state) 997 return; 998 999 si_pm4_bind_state(sctx, dsa, dsa); 1000 1001 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part, 1002 sizeof(struct si_dsa_stencil_ref_part)) != 0) { 1003 sctx->stencil_ref.dsa_part = dsa->stencil_ref; 1004 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom); 1005 } 1006} 1007 1008static void si_delete_dsa_state(struct pipe_context *ctx, void *state) 1009{ 1010 struct si_context *sctx = (struct si_context *)ctx; 1011 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state); 1012} 1013 1014static void *si_create_db_flush_dsa(struct si_context *sctx) 1015{ 1016 struct pipe_depth_stencil_alpha_state dsa = {}; 1017 1018 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa); 1019} 1020 1021/* DB RENDER STATE */ 1022 1023static void si_set_active_query_state(struct pipe_context *ctx, boolean enable) 1024{ 1025 struct si_context *sctx = (struct si_context*)ctx; 1026 1027 /* Pipeline stat & streamout queries. */ 1028 if (enable) { 1029 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS; 1030 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS; 1031 } else { 1032 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS; 1033 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS; 1034 } 1035 1036 /* Occlusion queries. */ 1037 if (sctx->occlusion_queries_disabled != !enable) { 1038 sctx->occlusion_queries_disabled = !enable; 1039 si_mark_atom_dirty(sctx, &sctx->db_render_state); 1040 } 1041} 1042 1043static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable) 1044{ 1045 struct si_context *sctx = (struct si_context*)ctx; 1046 1047 si_mark_atom_dirty(sctx, &sctx->db_render_state); 1048} 1049 1050static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state) 1051{ 1052 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 1053 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 1054 unsigned db_shader_control; 1055 1056 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2); 1057 1058 /* DB_RENDER_CONTROL */ 1059 if (sctx->dbcb_depth_copy_enabled || 1060 sctx->dbcb_stencil_copy_enabled) { 1061 radeon_emit(cs, 1062 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) | 1063 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) | 1064 S_028000_COPY_CENTROID(1) | 1065 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample)); 1066 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) { 1067 radeon_emit(cs, 1068 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) | 1069 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace)); 1070 } else { 1071 radeon_emit(cs, 1072 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) | 1073 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear)); 1074 } 1075 1076 /* DB_COUNT_CONTROL (occlusion queries) */ 1077 if (sctx->b.num_occlusion_queries > 0 && 1078 !sctx->occlusion_queries_disabled) { 1079 bool perfect = sctx->b.num_perfect_occlusion_queries > 0; 1080 1081 if (sctx->b.chip_class >= CIK) { 1082 radeon_emit(cs, 1083 S_028004_PERFECT_ZPASS_COUNTS(perfect) | 1084 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) | 1085 S_028004_ZPASS_ENABLE(1) | 1086 S_028004_SLICE_EVEN_ENABLE(1) | 1087 S_028004_SLICE_ODD_ENABLE(1)); 1088 } else { 1089 radeon_emit(cs, 1090 S_028004_PERFECT_ZPASS_COUNTS(perfect) | 1091 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples)); 1092 } 1093 } else { 1094 /* Disable occlusion queries. */ 1095 if (sctx->b.chip_class >= CIK) { 1096 radeon_emit(cs, 0); 1097 } else { 1098 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1)); 1099 } 1100 } 1101 1102 /* DB_RENDER_OVERRIDE2 */ 1103 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 1104 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) | 1105 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) | 1106 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4)); 1107 1108 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) | 1109 sctx->ps_db_shader_control; 1110 1111 /* Bug workaround for smoothing (overrasterization) on SI. */ 1112 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) { 1113 db_shader_control &= C_02880C_Z_ORDER; 1114 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z); 1115 } 1116 1117 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */ 1118 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable)) 1119 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE; 1120 1121 if (sctx->b.family == CHIP_STONEY && 1122 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) 1123 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1); 1124 1125 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, 1126 db_shader_control); 1127} 1128 1129/* 1130 * format translation 1131 */ 1132static uint32_t si_translate_colorformat(enum pipe_format format) 1133{ 1134 const struct util_format_description *desc = util_format_description(format); 1135 1136#define HAS_SIZE(x,y,z,w) \ 1137 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \ 1138 desc->channel[2].size == (z) && desc->channel[3].size == (w)) 1139 1140 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ 1141 return V_028C70_COLOR_10_11_11; 1142 1143 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) 1144 return V_028C70_COLOR_INVALID; 1145 1146 /* hw cannot support mixed formats (except depth/stencil, since 1147 * stencil is not written to). */ 1148 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) 1149 return V_028C70_COLOR_INVALID; 1150 1151 switch (desc->nr_channels) { 1152 case 1: 1153 switch (desc->channel[0].size) { 1154 case 8: 1155 return V_028C70_COLOR_8; 1156 case 16: 1157 return V_028C70_COLOR_16; 1158 case 32: 1159 return V_028C70_COLOR_32; 1160 } 1161 break; 1162 case 2: 1163 if (desc->channel[0].size == desc->channel[1].size) { 1164 switch (desc->channel[0].size) { 1165 case 8: 1166 return V_028C70_COLOR_8_8; 1167 case 16: 1168 return V_028C70_COLOR_16_16; 1169 case 32: 1170 return V_028C70_COLOR_32_32; 1171 } 1172 } else if (HAS_SIZE(8,24,0,0)) { 1173 return V_028C70_COLOR_24_8; 1174 } else if (HAS_SIZE(24,8,0,0)) { 1175 return V_028C70_COLOR_8_24; 1176 } 1177 break; 1178 case 3: 1179 if (HAS_SIZE(5,6,5,0)) { 1180 return V_028C70_COLOR_5_6_5; 1181 } else if (HAS_SIZE(32,8,24,0)) { 1182 return V_028C70_COLOR_X24_8_32_FLOAT; 1183 } 1184 break; 1185 case 4: 1186 if (desc->channel[0].size == desc->channel[1].size && 1187 desc->channel[0].size == desc->channel[2].size && 1188 desc->channel[0].size == desc->channel[3].size) { 1189 switch (desc->channel[0].size) { 1190 case 4: 1191 return V_028C70_COLOR_4_4_4_4; 1192 case 8: 1193 return V_028C70_COLOR_8_8_8_8; 1194 case 16: 1195 return V_028C70_COLOR_16_16_16_16; 1196 case 32: 1197 return V_028C70_COLOR_32_32_32_32; 1198 } 1199 } else if (HAS_SIZE(5,5,5,1)) { 1200 return V_028C70_COLOR_1_5_5_5; 1201 } else if (HAS_SIZE(10,10,10,2)) { 1202 return V_028C70_COLOR_2_10_10_10; 1203 } 1204 break; 1205 } 1206 return V_028C70_COLOR_INVALID; 1207} 1208 1209static uint32_t si_colorformat_endian_swap(uint32_t colorformat) 1210{ 1211 if (SI_BIG_ENDIAN) { 1212 switch(colorformat) { 1213 /* 8-bit buffers. */ 1214 case V_028C70_COLOR_8: 1215 return V_028C70_ENDIAN_NONE; 1216 1217 /* 16-bit buffers. */ 1218 case V_028C70_COLOR_5_6_5: 1219 case V_028C70_COLOR_1_5_5_5: 1220 case V_028C70_COLOR_4_4_4_4: 1221 case V_028C70_COLOR_16: 1222 case V_028C70_COLOR_8_8: 1223 return V_028C70_ENDIAN_8IN16; 1224 1225 /* 32-bit buffers. */ 1226 case V_028C70_COLOR_8_8_8_8: 1227 case V_028C70_COLOR_2_10_10_10: 1228 case V_028C70_COLOR_8_24: 1229 case V_028C70_COLOR_24_8: 1230 case V_028C70_COLOR_16_16: 1231 return V_028C70_ENDIAN_8IN32; 1232 1233 /* 64-bit buffers. */ 1234 case V_028C70_COLOR_16_16_16_16: 1235 return V_028C70_ENDIAN_8IN16; 1236 1237 case V_028C70_COLOR_32_32: 1238 return V_028C70_ENDIAN_8IN32; 1239 1240 /* 128-bit buffers. */ 1241 case V_028C70_COLOR_32_32_32_32: 1242 return V_028C70_ENDIAN_8IN32; 1243 default: 1244 return V_028C70_ENDIAN_NONE; /* Unsupported. */ 1245 } 1246 } else { 1247 return V_028C70_ENDIAN_NONE; 1248 } 1249} 1250 1251static uint32_t si_translate_dbformat(enum pipe_format format) 1252{ 1253 switch (format) { 1254 case PIPE_FORMAT_Z16_UNORM: 1255 return V_028040_Z_16; 1256 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1257 case PIPE_FORMAT_X8Z24_UNORM: 1258 case PIPE_FORMAT_Z24X8_UNORM: 1259 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1260 return V_028040_Z_24; /* deprecated on SI */ 1261 case PIPE_FORMAT_Z32_FLOAT: 1262 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1263 return V_028040_Z_32_FLOAT; 1264 default: 1265 return V_028040_Z_INVALID; 1266 } 1267} 1268 1269/* 1270 * Texture translation 1271 */ 1272 1273static uint32_t si_translate_texformat(struct pipe_screen *screen, 1274 enum pipe_format format, 1275 const struct util_format_description *desc, 1276 int first_non_void) 1277{ 1278 struct si_screen *sscreen = (struct si_screen*)screen; 1279 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 && 1280 sscreen->b.info.drm_minor >= 31) || 1281 sscreen->b.info.drm_major == 3; 1282 boolean uniform = TRUE; 1283 int i; 1284 1285 /* Colorspace (return non-RGB formats directly). */ 1286 switch (desc->colorspace) { 1287 /* Depth stencil formats */ 1288 case UTIL_FORMAT_COLORSPACE_ZS: 1289 switch (format) { 1290 case PIPE_FORMAT_Z16_UNORM: 1291 return V_008F14_IMG_DATA_FORMAT_16; 1292 case PIPE_FORMAT_X24S8_UINT: 1293 case PIPE_FORMAT_Z24X8_UNORM: 1294 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1295 return V_008F14_IMG_DATA_FORMAT_8_24; 1296 case PIPE_FORMAT_X8Z24_UNORM: 1297 case PIPE_FORMAT_S8X24_UINT: 1298 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1299 return V_008F14_IMG_DATA_FORMAT_24_8; 1300 case PIPE_FORMAT_S8_UINT: 1301 return V_008F14_IMG_DATA_FORMAT_8; 1302 case PIPE_FORMAT_Z32_FLOAT: 1303 return V_008F14_IMG_DATA_FORMAT_32; 1304 case PIPE_FORMAT_X32_S8X24_UINT: 1305 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1306 return V_008F14_IMG_DATA_FORMAT_X24_8_32; 1307 default: 1308 goto out_unknown; 1309 } 1310 1311 case UTIL_FORMAT_COLORSPACE_YUV: 1312 goto out_unknown; /* TODO */ 1313 1314 case UTIL_FORMAT_COLORSPACE_SRGB: 1315 if (desc->nr_channels != 4 && desc->nr_channels != 1) 1316 goto out_unknown; 1317 break; 1318 1319 default: 1320 break; 1321 } 1322 1323 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 1324 if (!enable_compressed_formats) 1325 goto out_unknown; 1326 1327 switch (format) { 1328 case PIPE_FORMAT_RGTC1_SNORM: 1329 case PIPE_FORMAT_LATC1_SNORM: 1330 case PIPE_FORMAT_RGTC1_UNORM: 1331 case PIPE_FORMAT_LATC1_UNORM: 1332 return V_008F14_IMG_DATA_FORMAT_BC4; 1333 case PIPE_FORMAT_RGTC2_SNORM: 1334 case PIPE_FORMAT_LATC2_SNORM: 1335 case PIPE_FORMAT_RGTC2_UNORM: 1336 case PIPE_FORMAT_LATC2_UNORM: 1337 return V_008F14_IMG_DATA_FORMAT_BC5; 1338 default: 1339 goto out_unknown; 1340 } 1341 } 1342 1343 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC && 1344 sscreen->b.family == CHIP_STONEY) { 1345 switch (format) { 1346 case PIPE_FORMAT_ETC1_RGB8: 1347 case PIPE_FORMAT_ETC2_RGB8: 1348 case PIPE_FORMAT_ETC2_SRGB8: 1349 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB; 1350 case PIPE_FORMAT_ETC2_RGB8A1: 1351 case PIPE_FORMAT_ETC2_SRGB8A1: 1352 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1; 1353 case PIPE_FORMAT_ETC2_RGBA8: 1354 case PIPE_FORMAT_ETC2_SRGBA8: 1355 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA; 1356 case PIPE_FORMAT_ETC2_R11_UNORM: 1357 case PIPE_FORMAT_ETC2_R11_SNORM: 1358 return V_008F14_IMG_DATA_FORMAT_ETC2_R; 1359 case PIPE_FORMAT_ETC2_RG11_UNORM: 1360 case PIPE_FORMAT_ETC2_RG11_SNORM: 1361 return V_008F14_IMG_DATA_FORMAT_ETC2_RG; 1362 default: 1363 goto out_unknown; 1364 } 1365 } 1366 1367 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) { 1368 if (!enable_compressed_formats) 1369 goto out_unknown; 1370 1371 switch (format) { 1372 case PIPE_FORMAT_BPTC_RGBA_UNORM: 1373 case PIPE_FORMAT_BPTC_SRGBA: 1374 return V_008F14_IMG_DATA_FORMAT_BC7; 1375 case PIPE_FORMAT_BPTC_RGB_FLOAT: 1376 case PIPE_FORMAT_BPTC_RGB_UFLOAT: 1377 return V_008F14_IMG_DATA_FORMAT_BC6; 1378 default: 1379 goto out_unknown; 1380 } 1381 } 1382 1383 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) { 1384 switch (format) { 1385 case PIPE_FORMAT_R8G8_B8G8_UNORM: 1386 case PIPE_FORMAT_G8R8_B8R8_UNORM: 1387 return V_008F14_IMG_DATA_FORMAT_GB_GR; 1388 case PIPE_FORMAT_G8R8_G8B8_UNORM: 1389 case PIPE_FORMAT_R8G8_R8B8_UNORM: 1390 return V_008F14_IMG_DATA_FORMAT_BG_RG; 1391 default: 1392 goto out_unknown; 1393 } 1394 } 1395 1396 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 1397 if (!enable_compressed_formats) 1398 goto out_unknown; 1399 1400 if (!util_format_s3tc_enabled) { 1401 goto out_unknown; 1402 } 1403 1404 switch (format) { 1405 case PIPE_FORMAT_DXT1_RGB: 1406 case PIPE_FORMAT_DXT1_RGBA: 1407 case PIPE_FORMAT_DXT1_SRGB: 1408 case PIPE_FORMAT_DXT1_SRGBA: 1409 return V_008F14_IMG_DATA_FORMAT_BC1; 1410 case PIPE_FORMAT_DXT3_RGBA: 1411 case PIPE_FORMAT_DXT3_SRGBA: 1412 return V_008F14_IMG_DATA_FORMAT_BC2; 1413 case PIPE_FORMAT_DXT5_RGBA: 1414 case PIPE_FORMAT_DXT5_SRGBA: 1415 return V_008F14_IMG_DATA_FORMAT_BC3; 1416 default: 1417 goto out_unknown; 1418 } 1419 } 1420 1421 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 1422 return V_008F14_IMG_DATA_FORMAT_5_9_9_9; 1423 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 1424 return V_008F14_IMG_DATA_FORMAT_10_11_11; 1425 } 1426 1427 /* R8G8Bx_SNORM - TODO CxV8U8 */ 1428 1429 /* hw cannot support mixed formats (except depth/stencil, since only 1430 * depth is read).*/ 1431 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS) 1432 goto out_unknown; 1433 1434 /* See whether the components are of the same size. */ 1435 for (i = 1; i < desc->nr_channels; i++) { 1436 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1437 } 1438 1439 /* Non-uniform formats. */ 1440 if (!uniform) { 1441 switch(desc->nr_channels) { 1442 case 3: 1443 if (desc->channel[0].size == 5 && 1444 desc->channel[1].size == 6 && 1445 desc->channel[2].size == 5) { 1446 return V_008F14_IMG_DATA_FORMAT_5_6_5; 1447 } 1448 goto out_unknown; 1449 case 4: 1450 if (desc->channel[0].size == 5 && 1451 desc->channel[1].size == 5 && 1452 desc->channel[2].size == 5 && 1453 desc->channel[3].size == 1) { 1454 return V_008F14_IMG_DATA_FORMAT_1_5_5_5; 1455 } 1456 if (desc->channel[0].size == 10 && 1457 desc->channel[1].size == 10 && 1458 desc->channel[2].size == 10 && 1459 desc->channel[3].size == 2) { 1460 return V_008F14_IMG_DATA_FORMAT_2_10_10_10; 1461 } 1462 goto out_unknown; 1463 } 1464 goto out_unknown; 1465 } 1466 1467 if (first_non_void < 0 || first_non_void > 3) 1468 goto out_unknown; 1469 1470 /* uniform formats */ 1471 switch (desc->channel[first_non_void].size) { 1472 case 4: 1473 switch (desc->nr_channels) { 1474#if 0 /* Not supported for render targets */ 1475 case 2: 1476 return V_008F14_IMG_DATA_FORMAT_4_4; 1477#endif 1478 case 4: 1479 return V_008F14_IMG_DATA_FORMAT_4_4_4_4; 1480 } 1481 break; 1482 case 8: 1483 switch (desc->nr_channels) { 1484 case 1: 1485 return V_008F14_IMG_DATA_FORMAT_8; 1486 case 2: 1487 return V_008F14_IMG_DATA_FORMAT_8_8; 1488 case 4: 1489 return V_008F14_IMG_DATA_FORMAT_8_8_8_8; 1490 } 1491 break; 1492 case 16: 1493 switch (desc->nr_channels) { 1494 case 1: 1495 return V_008F14_IMG_DATA_FORMAT_16; 1496 case 2: 1497 return V_008F14_IMG_DATA_FORMAT_16_16; 1498 case 4: 1499 return V_008F14_IMG_DATA_FORMAT_16_16_16_16; 1500 } 1501 break; 1502 case 32: 1503 switch (desc->nr_channels) { 1504 case 1: 1505 return V_008F14_IMG_DATA_FORMAT_32; 1506 case 2: 1507 return V_008F14_IMG_DATA_FORMAT_32_32; 1508#if 0 /* Not supported for render targets */ 1509 case 3: 1510 return V_008F14_IMG_DATA_FORMAT_32_32_32; 1511#endif 1512 case 4: 1513 return V_008F14_IMG_DATA_FORMAT_32_32_32_32; 1514 } 1515 } 1516 1517out_unknown: 1518 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1519 return ~0; 1520} 1521 1522static unsigned si_tex_wrap(unsigned wrap) 1523{ 1524 switch (wrap) { 1525 default: 1526 case PIPE_TEX_WRAP_REPEAT: 1527 return V_008F30_SQ_TEX_WRAP; 1528 case PIPE_TEX_WRAP_CLAMP: 1529 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER; 1530 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 1531 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL; 1532 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 1533 return V_008F30_SQ_TEX_CLAMP_BORDER; 1534 case PIPE_TEX_WRAP_MIRROR_REPEAT: 1535 return V_008F30_SQ_TEX_MIRROR; 1536 case PIPE_TEX_WRAP_MIRROR_CLAMP: 1537 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 1538 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 1539 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 1540 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 1541 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER; 1542 } 1543} 1544 1545static unsigned si_tex_mipfilter(unsigned filter) 1546{ 1547 switch (filter) { 1548 case PIPE_TEX_MIPFILTER_NEAREST: 1549 return V_008F38_SQ_TEX_Z_FILTER_POINT; 1550 case PIPE_TEX_MIPFILTER_LINEAR: 1551 return V_008F38_SQ_TEX_Z_FILTER_LINEAR; 1552 default: 1553 case PIPE_TEX_MIPFILTER_NONE: 1554 return V_008F38_SQ_TEX_Z_FILTER_NONE; 1555 } 1556} 1557 1558static unsigned si_tex_compare(unsigned compare) 1559{ 1560 switch (compare) { 1561 default: 1562 case PIPE_FUNC_NEVER: 1563 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER; 1564 case PIPE_FUNC_LESS: 1565 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS; 1566 case PIPE_FUNC_EQUAL: 1567 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL; 1568 case PIPE_FUNC_LEQUAL: 1569 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 1570 case PIPE_FUNC_GREATER: 1571 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER; 1572 case PIPE_FUNC_NOTEQUAL: 1573 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 1574 case PIPE_FUNC_GEQUAL: 1575 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 1576 case PIPE_FUNC_ALWAYS: 1577 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS; 1578 } 1579} 1580 1581static unsigned si_tex_dim(unsigned res_target, unsigned view_target, 1582 unsigned nr_samples) 1583{ 1584 if (view_target == PIPE_TEXTURE_CUBE || 1585 view_target == PIPE_TEXTURE_CUBE_ARRAY) 1586 res_target = view_target; 1587 1588 switch (res_target) { 1589 default: 1590 case PIPE_TEXTURE_1D: 1591 return V_008F1C_SQ_RSRC_IMG_1D; 1592 case PIPE_TEXTURE_1D_ARRAY: 1593 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY; 1594 case PIPE_TEXTURE_2D: 1595 case PIPE_TEXTURE_RECT: 1596 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA : 1597 V_008F1C_SQ_RSRC_IMG_2D; 1598 case PIPE_TEXTURE_2D_ARRAY: 1599 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : 1600 V_008F1C_SQ_RSRC_IMG_2D_ARRAY; 1601 case PIPE_TEXTURE_3D: 1602 return V_008F1C_SQ_RSRC_IMG_3D; 1603 case PIPE_TEXTURE_CUBE: 1604 case PIPE_TEXTURE_CUBE_ARRAY: 1605 return V_008F1C_SQ_RSRC_IMG_CUBE; 1606 } 1607} 1608 1609/* 1610 * Format support testing 1611 */ 1612 1613static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 1614{ 1615 return si_translate_texformat(screen, format, util_format_description(format), 1616 util_format_get_first_non_void_channel(format)) != ~0U; 1617} 1618 1619static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen, 1620 const struct util_format_description *desc, 1621 int first_non_void) 1622{ 1623 unsigned type; 1624 int i; 1625 1626 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT) 1627 return V_008F0C_BUF_DATA_FORMAT_10_11_11; 1628 1629 assert(first_non_void >= 0); 1630 type = desc->channel[first_non_void].type; 1631 1632 if (type == UTIL_FORMAT_TYPE_FIXED) 1633 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1634 1635 if (desc->nr_channels == 4 && 1636 desc->channel[0].size == 10 && 1637 desc->channel[1].size == 10 && 1638 desc->channel[2].size == 10 && 1639 desc->channel[3].size == 2) 1640 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10; 1641 1642 /* See whether the components are of the same size. */ 1643 for (i = 0; i < desc->nr_channels; i++) { 1644 if (desc->channel[first_non_void].size != desc->channel[i].size) 1645 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1646 } 1647 1648 switch (desc->channel[first_non_void].size) { 1649 case 8: 1650 switch (desc->nr_channels) { 1651 case 1: 1652 return V_008F0C_BUF_DATA_FORMAT_8; 1653 case 2: 1654 return V_008F0C_BUF_DATA_FORMAT_8_8; 1655 case 3: 1656 case 4: 1657 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8; 1658 } 1659 break; 1660 case 16: 1661 switch (desc->nr_channels) { 1662 case 1: 1663 return V_008F0C_BUF_DATA_FORMAT_16; 1664 case 2: 1665 return V_008F0C_BUF_DATA_FORMAT_16_16; 1666 case 3: 1667 case 4: 1668 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16; 1669 } 1670 break; 1671 case 32: 1672 /* From the Southern Islands ISA documentation about MTBUF: 1673 * 'Memory reads of data in memory that is 32 or 64 bits do not 1674 * undergo any format conversion.' 1675 */ 1676 if (type != UTIL_FORMAT_TYPE_FLOAT && 1677 !desc->channel[first_non_void].pure_integer) 1678 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1679 1680 switch (desc->nr_channels) { 1681 case 1: 1682 return V_008F0C_BUF_DATA_FORMAT_32; 1683 case 2: 1684 return V_008F0C_BUF_DATA_FORMAT_32_32; 1685 case 3: 1686 return V_008F0C_BUF_DATA_FORMAT_32_32_32; 1687 case 4: 1688 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32; 1689 } 1690 break; 1691 } 1692 1693 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1694} 1695 1696static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen, 1697 const struct util_format_description *desc, 1698 int first_non_void) 1699{ 1700 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT) 1701 return V_008F0C_BUF_NUM_FORMAT_FLOAT; 1702 1703 assert(first_non_void >= 0); 1704 1705 switch (desc->channel[first_non_void].type) { 1706 case UTIL_FORMAT_TYPE_SIGNED: 1707 if (desc->channel[first_non_void].normalized) 1708 return V_008F0C_BUF_NUM_FORMAT_SNORM; 1709 else if (desc->channel[first_non_void].pure_integer) 1710 return V_008F0C_BUF_NUM_FORMAT_SINT; 1711 else 1712 return V_008F0C_BUF_NUM_FORMAT_SSCALED; 1713 break; 1714 case UTIL_FORMAT_TYPE_UNSIGNED: 1715 if (desc->channel[first_non_void].normalized) 1716 return V_008F0C_BUF_NUM_FORMAT_UNORM; 1717 else if (desc->channel[first_non_void].pure_integer) 1718 return V_008F0C_BUF_NUM_FORMAT_UINT; 1719 else 1720 return V_008F0C_BUF_NUM_FORMAT_USCALED; 1721 break; 1722 case UTIL_FORMAT_TYPE_FLOAT: 1723 default: 1724 return V_008F0C_BUF_NUM_FORMAT_FLOAT; 1725 } 1726} 1727 1728static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format) 1729{ 1730 const struct util_format_description *desc; 1731 int first_non_void; 1732 unsigned data_format; 1733 1734 desc = util_format_description(format); 1735 first_non_void = util_format_get_first_non_void_channel(format); 1736 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void); 1737 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID; 1738} 1739 1740static bool si_is_colorbuffer_format_supported(enum pipe_format format) 1741{ 1742 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID && 1743 r600_translate_colorswap(format, FALSE) != ~0U; 1744} 1745 1746static bool si_is_zs_format_supported(enum pipe_format format) 1747{ 1748 return si_translate_dbformat(format) != V_028040_Z_INVALID; 1749} 1750 1751boolean si_is_format_supported(struct pipe_screen *screen, 1752 enum pipe_format format, 1753 enum pipe_texture_target target, 1754 unsigned sample_count, 1755 unsigned usage) 1756{ 1757 unsigned retval = 0; 1758 1759 if (target >= PIPE_MAX_TEXTURE_TYPES) { 1760 R600_ERR("r600: unsupported texture type %d\n", target); 1761 return FALSE; 1762 } 1763 1764 if (!util_format_is_supported(format, usage)) 1765 return FALSE; 1766 1767 if (sample_count > 1) { 1768 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE)) 1769 return FALSE; 1770 1771 switch (sample_count) { 1772 case 2: 1773 case 4: 1774 case 8: 1775 break; 1776 case 16: 1777 if (format == PIPE_FORMAT_NONE) 1778 return TRUE; 1779 else 1780 return FALSE; 1781 default: 1782 return FALSE; 1783 } 1784 } 1785 1786 if (usage & (PIPE_BIND_SAMPLER_VIEW | 1787 PIPE_BIND_SHADER_IMAGE)) { 1788 if (target == PIPE_BUFFER) { 1789 if (si_is_vertex_format_supported(screen, format)) 1790 retval |= usage & (PIPE_BIND_SAMPLER_VIEW | 1791 PIPE_BIND_SHADER_IMAGE); 1792 } else { 1793 if (si_is_sampler_format_supported(screen, format)) 1794 retval |= usage & (PIPE_BIND_SAMPLER_VIEW | 1795 PIPE_BIND_SHADER_IMAGE); 1796 } 1797 } 1798 1799 if ((usage & (PIPE_BIND_RENDER_TARGET | 1800 PIPE_BIND_DISPLAY_TARGET | 1801 PIPE_BIND_SCANOUT | 1802 PIPE_BIND_SHARED | 1803 PIPE_BIND_BLENDABLE)) && 1804 si_is_colorbuffer_format_supported(format)) { 1805 retval |= usage & 1806 (PIPE_BIND_RENDER_TARGET | 1807 PIPE_BIND_DISPLAY_TARGET | 1808 PIPE_BIND_SCANOUT | 1809 PIPE_BIND_SHARED); 1810 if (!util_format_is_pure_integer(format) && 1811 !util_format_is_depth_or_stencil(format)) 1812 retval |= usage & PIPE_BIND_BLENDABLE; 1813 } 1814 1815 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 1816 si_is_zs_format_supported(format)) { 1817 retval |= PIPE_BIND_DEPTH_STENCIL; 1818 } 1819 1820 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 1821 si_is_vertex_format_supported(screen, format)) { 1822 retval |= PIPE_BIND_VERTEX_BUFFER; 1823 } 1824 1825 if (usage & PIPE_BIND_TRANSFER_READ) 1826 retval |= PIPE_BIND_TRANSFER_READ; 1827 if (usage & PIPE_BIND_TRANSFER_WRITE) 1828 retval |= PIPE_BIND_TRANSFER_WRITE; 1829 1830 if ((usage & PIPE_BIND_LINEAR) && 1831 !util_format_is_compressed(format) && 1832 !(usage & PIPE_BIND_DEPTH_STENCIL)) 1833 retval |= PIPE_BIND_LINEAR; 1834 1835 return retval == usage; 1836} 1837 1838/* 1839 * framebuffer handling 1840 */ 1841 1842static void si_choose_spi_color_formats(struct r600_surface *surf, 1843 unsigned format, unsigned swap, 1844 unsigned ntype, bool is_depth) 1845{ 1846 /* Alpha is needed for alpha-to-coverage. 1847 * Blending may be with or without alpha. 1848 */ 1849 unsigned normal = 0; /* most optimal, may not support blending or export alpha */ 1850 unsigned alpha = 0; /* exports alpha, but may not support blending */ 1851 unsigned blend = 0; /* supports blending, but may not export alpha */ 1852 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */ 1853 1854 /* Choose the SPI color formats. These are required values for Stoney/RB+. 1855 * Other chips have multiple choices, though they are not necessarily better. 1856 */ 1857 switch (format) { 1858 case V_028C70_COLOR_5_6_5: 1859 case V_028C70_COLOR_1_5_5_5: 1860 case V_028C70_COLOR_5_5_5_1: 1861 case V_028C70_COLOR_4_4_4_4: 1862 case V_028C70_COLOR_10_11_11: 1863 case V_028C70_COLOR_11_11_10: 1864 case V_028C70_COLOR_8: 1865 case V_028C70_COLOR_8_8: 1866 case V_028C70_COLOR_8_8_8_8: 1867 case V_028C70_COLOR_10_10_10_2: 1868 case V_028C70_COLOR_2_10_10_10: 1869 if (ntype == V_028C70_NUMBER_UINT) 1870 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR; 1871 else if (ntype == V_028C70_NUMBER_SINT) 1872 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR; 1873 else 1874 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR; 1875 break; 1876 1877 case V_028C70_COLOR_16: 1878 case V_028C70_COLOR_16_16: 1879 case V_028C70_COLOR_16_16_16_16: 1880 if (ntype == V_028C70_NUMBER_UNORM || 1881 ntype == V_028C70_NUMBER_SNORM) { 1882 /* UNORM16 and SNORM16 don't support blending */ 1883 if (ntype == V_028C70_NUMBER_UNORM) 1884 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR; 1885 else 1886 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR; 1887 1888 /* Use 32 bits per channel for blending. */ 1889 if (format == V_028C70_COLOR_16) { 1890 if (swap == V_028C70_SWAP_STD) { /* R */ 1891 blend = V_028714_SPI_SHADER_32_R; 1892 blend_alpha = V_028714_SPI_SHADER_32_AR; 1893 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */ 1894 blend = blend_alpha = V_028714_SPI_SHADER_32_AR; 1895 else 1896 assert(0); 1897 } else if (format == V_028C70_COLOR_16_16) { 1898 if (swap == V_028C70_SWAP_STD) { /* RG */ 1899 blend = V_028714_SPI_SHADER_32_GR; 1900 blend_alpha = V_028714_SPI_SHADER_32_ABGR; 1901 } else if (swap == V_028C70_SWAP_ALT) /* RA */ 1902 blend = blend_alpha = V_028714_SPI_SHADER_32_AR; 1903 else 1904 assert(0); 1905 } else /* 16_16_16_16 */ 1906 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR; 1907 } else if (ntype == V_028C70_NUMBER_UINT) 1908 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR; 1909 else if (ntype == V_028C70_NUMBER_SINT) 1910 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR; 1911 else if (ntype == V_028C70_NUMBER_FLOAT) 1912 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR; 1913 else 1914 assert(0); 1915 break; 1916 1917 case V_028C70_COLOR_32: 1918 if (swap == V_028C70_SWAP_STD) { /* R */ 1919 blend = normal = V_028714_SPI_SHADER_32_R; 1920 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR; 1921 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */ 1922 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR; 1923 else 1924 assert(0); 1925 break; 1926 1927 case V_028C70_COLOR_32_32: 1928 if (swap == V_028C70_SWAP_STD) { /* RG */ 1929 blend = normal = V_028714_SPI_SHADER_32_GR; 1930 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR; 1931 } else if (swap == V_028C70_SWAP_ALT) /* RA */ 1932 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR; 1933 else 1934 assert(0); 1935 break; 1936 1937 case V_028C70_COLOR_32_32_32_32: 1938 case V_028C70_COLOR_8_24: 1939 case V_028C70_COLOR_24_8: 1940 case V_028C70_COLOR_X24_8_32_FLOAT: 1941 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR; 1942 break; 1943 1944 default: 1945 assert(0); 1946 return; 1947 } 1948 1949 /* The DB->CB copy needs 32_ABGR. */ 1950 if (is_depth) 1951 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR; 1952 1953 surf->spi_shader_col_format = normal; 1954 surf->spi_shader_col_format_alpha = alpha; 1955 surf->spi_shader_col_format_blend = blend; 1956 surf->spi_shader_col_format_blend_alpha = blend_alpha; 1957} 1958 1959static void si_initialize_color_surface(struct si_context *sctx, 1960 struct r600_surface *surf) 1961{ 1962 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; 1963 unsigned color_info, color_attrib, color_view; 1964 unsigned format, swap, ntype, endian; 1965 const struct util_format_description *desc; 1966 int i; 1967 unsigned blend_clamp = 0, blend_bypass = 0; 1968 1969 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | 1970 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); 1971 1972 desc = util_format_description(surf->base.format); 1973 for (i = 0; i < 4; i++) { 1974 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1975 break; 1976 } 1977 } 1978 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { 1979 ntype = V_028C70_NUMBER_FLOAT; 1980 } else { 1981 ntype = V_028C70_NUMBER_UNORM; 1982 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1983 ntype = V_028C70_NUMBER_SRGB; 1984 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1985 if (desc->channel[i].pure_integer) { 1986 ntype = V_028C70_NUMBER_SINT; 1987 } else { 1988 assert(desc->channel[i].normalized); 1989 ntype = V_028C70_NUMBER_SNORM; 1990 } 1991 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1992 if (desc->channel[i].pure_integer) { 1993 ntype = V_028C70_NUMBER_UINT; 1994 } else { 1995 assert(desc->channel[i].normalized); 1996 ntype = V_028C70_NUMBER_UNORM; 1997 } 1998 } 1999 } 2000 2001 format = si_translate_colorformat(surf->base.format); 2002 if (format == V_028C70_COLOR_INVALID) { 2003 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format); 2004 } 2005 assert(format != V_028C70_COLOR_INVALID); 2006 swap = r600_translate_colorswap(surf->base.format, FALSE); 2007 endian = si_colorformat_endian_swap(format); 2008 2009 /* blend clamp should be set for all NORM/SRGB types */ 2010 if (ntype == V_028C70_NUMBER_UNORM || 2011 ntype == V_028C70_NUMBER_SNORM || 2012 ntype == V_028C70_NUMBER_SRGB) 2013 blend_clamp = 1; 2014 2015 /* set blend bypass according to docs if SINT/UINT or 2016 8/24 COLOR variants */ 2017 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT || 2018 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 || 2019 format == V_028C70_COLOR_X24_8_32_FLOAT) { 2020 blend_clamp = 0; 2021 blend_bypass = 1; 2022 } 2023 2024 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) && 2025 (format == V_028C70_COLOR_8 || 2026 format == V_028C70_COLOR_8_8 || 2027 format == V_028C70_COLOR_8_8_8_8)) 2028 surf->color_is_int8 = true; 2029 2030 color_info = S_028C70_FORMAT(format) | 2031 S_028C70_COMP_SWAP(swap) | 2032 S_028C70_BLEND_CLAMP(blend_clamp) | 2033 S_028C70_BLEND_BYPASS(blend_bypass) | 2034 S_028C70_NUMBER_TYPE(ntype) | 2035 S_028C70_ENDIAN(endian); 2036 2037 /* Intensity is implemented as Red, so treat it that way. */ 2038 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 || 2039 util_format_is_intensity(surf->base.format)); 2040 2041 if (rtex->resource.b.b.nr_samples > 1) { 2042 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples); 2043 2044 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | 2045 S_028C74_NUM_FRAGMENTS(log_samples); 2046 2047 if (rtex->fmask.size) { 2048 color_info |= S_028C70_COMPRESSION(1); 2049 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height); 2050 2051 if (sctx->b.chip_class == SI) { 2052 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */ 2053 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); 2054 } 2055 } 2056 } 2057 2058 surf->cb_color_view = color_view; 2059 surf->cb_color_info = color_info; 2060 surf->cb_color_attrib = color_attrib; 2061 2062 if (sctx->b.chip_class >= VI) { 2063 unsigned max_uncompressed_block_size = 2; 2064 2065 if (rtex->surface.nsamples > 1) { 2066 if (rtex->surface.bpe == 1) 2067 max_uncompressed_block_size = 0; 2068 else if (rtex->surface.bpe == 2) 2069 max_uncompressed_block_size = 1; 2070 } 2071 2072 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) | 2073 S_028C78_INDEPENDENT_64B_BLOCKS(1); 2074 } 2075 2076 /* This must be set for fast clear to work without FMASK. */ 2077 if (!rtex->fmask.size && sctx->b.chip_class == SI) { 2078 unsigned bankh = util_logbase2(rtex->surface.bankh); 2079 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh); 2080 } 2081 2082 /* Determine pixel shader export format */ 2083 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth); 2084 2085 surf->color_initialized = true; 2086} 2087 2088static void si_init_depth_surface(struct si_context *sctx, 2089 struct r600_surface *surf) 2090{ 2091 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; 2092 unsigned level = surf->base.u.tex.level; 2093 struct radeon_surf_level *levelinfo = &rtex->surface.level[level]; 2094 unsigned format; 2095 uint32_t z_info, s_info, db_depth_info; 2096 uint64_t z_offs, s_offs; 2097 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0; 2098 2099 switch (sctx->framebuffer.state.zsbuf->texture->format) { 2100 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2101 case PIPE_FORMAT_X8Z24_UNORM: 2102 case PIPE_FORMAT_Z24X8_UNORM: 2103 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 2104 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24); 2105 break; 2106 case PIPE_FORMAT_Z32_FLOAT: 2107 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 2108 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | 2109 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 2110 break; 2111 case PIPE_FORMAT_Z16_UNORM: 2112 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16); 2113 break; 2114 default: 2115 assert(0); 2116 } 2117 2118 format = si_translate_dbformat(rtex->resource.b.b.format); 2119 2120 if (format == V_028040_Z_INVALID) { 2121 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format); 2122 } 2123 assert(format != V_028040_Z_INVALID); 2124 2125 s_offs = z_offs = rtex->resource.gpu_address; 2126 z_offs += rtex->surface.level[level].offset; 2127 s_offs += rtex->surface.stencil_level[level].offset; 2128 2129 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1); 2130 2131 z_info = S_028040_FORMAT(format); 2132 if (rtex->resource.b.b.nr_samples > 1) { 2133 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)); 2134 } 2135 2136 if (rtex->surface.flags & RADEON_SURF_SBUFFER) 2137 s_info = S_028044_FORMAT(V_028044_STENCIL_8); 2138 else 2139 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID); 2140 2141 if (sctx->b.chip_class >= CIK) { 2142 struct radeon_info *info = &sctx->screen->b.info; 2143 unsigned index = rtex->surface.tiling_index[level]; 2144 unsigned stencil_index = rtex->surface.stencil_tiling_index[level]; 2145 unsigned macro_index = rtex->surface.macro_tile_index; 2146 unsigned tile_mode = info->si_tile_mode_array[index]; 2147 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index]; 2148 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index]; 2149 2150 db_depth_info |= 2151 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) | 2152 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) | 2153 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) | 2154 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) | 2155 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) | 2156 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode)); 2157 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode)); 2158 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode)); 2159 } else { 2160 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false); 2161 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); 2162 tile_mode_index = si_tile_mode_index(rtex, level, true); 2163 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index); 2164 } 2165 2166 /* HiZ aka depth buffer htile */ 2167 /* use htile only for first level */ 2168 if (rtex->htile_buffer && !level) { 2169 z_info |= S_028040_TILE_SURFACE_ENABLE(1) | 2170 S_028040_ALLOW_EXPCLEAR(1); 2171 2172 if (rtex->surface.flags & RADEON_SURF_SBUFFER) { 2173 /* Workaround: For a not yet understood reason, the 2174 * combination of MSAA, fast stencil clear and stencil 2175 * decompress messes with subsequent stencil buffer 2176 * uses. Problem was reproduced on Verde, Bonaire, 2177 * Tonga, and Carrizo. 2178 * 2179 * Disabling EXPCLEAR works around the problem. 2180 * 2181 * Check piglit's arb_texture_multisample-stencil-clear 2182 * test if you want to try changing this. 2183 */ 2184 if (rtex->resource.b.b.nr_samples <= 1) 2185 s_info |= S_028044_ALLOW_EXPCLEAR(1); 2186 } else 2187 /* Use all of the htile_buffer for depth if there's no stencil. */ 2188 s_info |= S_028044_TILE_STENCIL_DISABLE(1); 2189 2190 uint64_t va = rtex->htile_buffer->gpu_address; 2191 db_htile_data_base = va >> 8; 2192 db_htile_surface = S_028ABC_FULL_CACHE(1); 2193 } else { 2194 db_htile_data_base = 0; 2195 db_htile_surface = 0; 2196 } 2197 2198 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); 2199 2200 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) | 2201 S_028008_SLICE_MAX(surf->base.u.tex.last_layer); 2202 surf->db_htile_data_base = db_htile_data_base; 2203 surf->db_depth_info = db_depth_info; 2204 surf->db_z_info = z_info; 2205 surf->db_stencil_info = s_info; 2206 surf->db_depth_base = z_offs >> 8; 2207 surf->db_stencil_base = s_offs >> 8; 2208 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) | 2209 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1); 2210 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x * 2211 levelinfo->nblk_y) / 64 - 1); 2212 surf->db_htile_surface = db_htile_surface; 2213 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl; 2214 2215 surf->depth_initialized = true; 2216} 2217 2218void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state) 2219{ 2220 for (int i = 0; i < state->nr_cbufs; ++i) { 2221 struct r600_surface *surf = NULL; 2222 struct r600_texture *rtex; 2223 2224 if (!state->cbufs[i]) 2225 continue; 2226 surf = (struct r600_surface*)state->cbufs[i]; 2227 rtex = (struct r600_texture*)surf->base.texture; 2228 2229 p_atomic_dec(&rtex->framebuffers_bound); 2230 } 2231} 2232 2233static void si_set_framebuffer_state(struct pipe_context *ctx, 2234 const struct pipe_framebuffer_state *state) 2235{ 2236 struct si_context *sctx = (struct si_context *)ctx; 2237 struct pipe_constant_buffer constbuf = {0}; 2238 struct r600_surface *surf = NULL; 2239 struct r600_texture *rtex; 2240 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer; 2241 unsigned old_nr_samples = sctx->framebuffer.nr_samples; 2242 int i; 2243 2244 /* Only flush TC when changing the framebuffer state, because 2245 * the only client not using TC that can change textures is 2246 * the framebuffer. 2247 * 2248 * Flush all CB and DB caches here because all buffers can be used 2249 * for write by both TC (with shader image stores) and CB/DB. 2250 */ 2251 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 | 2252 SI_CONTEXT_INV_GLOBAL_L2 | 2253 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER | 2254 SI_CONTEXT_CS_PARTIAL_FLUSH; 2255 2256 /* Take the maximum of the old and new count. If the new count is lower, 2257 * dirtying is needed to disable the unbound colorbuffers. 2258 */ 2259 sctx->framebuffer.dirty_cbufs |= 2260 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1; 2261 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf; 2262 2263 si_dec_framebuffer_counters(&sctx->framebuffer.state); 2264 util_copy_framebuffer_state(&sctx->framebuffer.state, state); 2265 2266 sctx->framebuffer.spi_shader_col_format = 0; 2267 sctx->framebuffer.spi_shader_col_format_alpha = 0; 2268 sctx->framebuffer.spi_shader_col_format_blend = 0; 2269 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0; 2270 sctx->framebuffer.color_is_int8 = 0; 2271 2272 sctx->framebuffer.compressed_cb_mask = 0; 2273 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state); 2274 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples); 2275 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] && 2276 util_format_is_pure_integer(state->cbufs[0]->format); 2277 2278 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer) 2279 si_mark_atom_dirty(sctx, &sctx->db_render_state); 2280 2281 for (i = 0; i < state->nr_cbufs; i++) { 2282 if (!state->cbufs[i]) 2283 continue; 2284 2285 surf = (struct r600_surface*)state->cbufs[i]; 2286 rtex = (struct r600_texture*)surf->base.texture; 2287 2288 if (!surf->color_initialized) { 2289 si_initialize_color_surface(sctx, surf); 2290 } 2291 2292 sctx->framebuffer.spi_shader_col_format |= 2293 surf->spi_shader_col_format << (i * 4); 2294 sctx->framebuffer.spi_shader_col_format_alpha |= 2295 surf->spi_shader_col_format_alpha << (i * 4); 2296 sctx->framebuffer.spi_shader_col_format_blend |= 2297 surf->spi_shader_col_format_blend << (i * 4); 2298 sctx->framebuffer.spi_shader_col_format_blend_alpha |= 2299 surf->spi_shader_col_format_blend_alpha << (i * 4); 2300 2301 if (surf->color_is_int8) 2302 sctx->framebuffer.color_is_int8 |= 1 << i; 2303 2304 if (rtex->fmask.size && rtex->cmask.size) { 2305 sctx->framebuffer.compressed_cb_mask |= 1 << i; 2306 } 2307 r600_context_add_resource_size(ctx, surf->base.texture); 2308 2309 p_atomic_inc(&rtex->framebuffers_bound); 2310 } 2311 /* Set the second SPI format for possible dual-src blending. */ 2312 if (i == 1 && surf) { 2313 sctx->framebuffer.spi_shader_col_format |= 2314 surf->spi_shader_col_format << (i * 4); 2315 sctx->framebuffer.spi_shader_col_format_alpha |= 2316 surf->spi_shader_col_format_alpha << (i * 4); 2317 sctx->framebuffer.spi_shader_col_format_blend |= 2318 surf->spi_shader_col_format_blend << (i * 4); 2319 sctx->framebuffer.spi_shader_col_format_blend_alpha |= 2320 surf->spi_shader_col_format_blend_alpha << (i * 4); 2321 } 2322 2323 if (state->zsbuf) { 2324 surf = (struct r600_surface*)state->zsbuf; 2325 2326 if (!surf->depth_initialized) { 2327 si_init_depth_surface(sctx, surf); 2328 } 2329 r600_context_add_resource_size(ctx, surf->base.texture); 2330 } 2331 2332 si_update_poly_offset_state(sctx); 2333 si_mark_atom_dirty(sctx, &sctx->cb_render_state); 2334 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); 2335 2336 if (sctx->framebuffer.nr_samples != old_nr_samples) { 2337 si_mark_atom_dirty(sctx, &sctx->msaa_config); 2338 si_mark_atom_dirty(sctx, &sctx->db_render_state); 2339 2340 /* Set sample locations as fragment shader constants. */ 2341 switch (sctx->framebuffer.nr_samples) { 2342 case 1: 2343 constbuf.user_buffer = sctx->b.sample_locations_1x; 2344 break; 2345 case 2: 2346 constbuf.user_buffer = sctx->b.sample_locations_2x; 2347 break; 2348 case 4: 2349 constbuf.user_buffer = sctx->b.sample_locations_4x; 2350 break; 2351 case 8: 2352 constbuf.user_buffer = sctx->b.sample_locations_8x; 2353 break; 2354 case 16: 2355 constbuf.user_buffer = sctx->b.sample_locations_16x; 2356 break; 2357 default: 2358 R600_ERR("Requested an invalid number of samples %i.\n", 2359 sctx->framebuffer.nr_samples); 2360 assert(0); 2361 } 2362 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4; 2363 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf); 2364 2365 /* Smoothing (only possible with nr_samples == 1) uses the same 2366 * sample locations as the MSAA it simulates. 2367 * 2368 * Therefore, don't update the sample locations when 2369 * transitioning from no AA to smoothing-equivalent AA, and 2370 * vice versa. 2371 */ 2372 if ((sctx->framebuffer.nr_samples != 1 || 2373 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) && 2374 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES || 2375 old_nr_samples != 1)) 2376 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs); 2377 } 2378 2379 sctx->need_check_render_feedback = true; 2380} 2381 2382static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom) 2383{ 2384 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 2385 struct pipe_framebuffer_state *state = &sctx->framebuffer.state; 2386 unsigned i, nr_cbufs = state->nr_cbufs; 2387 struct r600_texture *tex = NULL; 2388 struct r600_surface *cb = NULL; 2389 unsigned cb_color_info = 0; 2390 2391 /* Colorbuffers. */ 2392 for (i = 0; i < nr_cbufs; i++) { 2393 unsigned pitch_tile_max, slice_tile_max, tile_mode_index; 2394 unsigned cb_color_base, cb_color_fmask, cb_color_attrib; 2395 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice; 2396 2397 if (!(sctx->framebuffer.dirty_cbufs & (1 << i))) 2398 continue; 2399 2400 cb = (struct r600_surface*)state->cbufs[i]; 2401 if (!cb) { 2402 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 2403 S_028C70_FORMAT(V_028C70_COLOR_INVALID)); 2404 continue; 2405 } 2406 2407 tex = (struct r600_texture *)cb->base.texture; 2408 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, 2409 &tex->resource, RADEON_USAGE_READWRITE, 2410 tex->surface.nsamples > 1 ? 2411 RADEON_PRIO_COLOR_BUFFER_MSAA : 2412 RADEON_PRIO_COLOR_BUFFER); 2413 2414 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) { 2415 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, 2416 tex->cmask_buffer, RADEON_USAGE_READWRITE, 2417 RADEON_PRIO_CMASK); 2418 } 2419 2420 /* Compute mutable surface parameters. */ 2421 pitch_tile_max = cb->level_info->nblk_x / 8 - 1; 2422 slice_tile_max = cb->level_info->nblk_x * 2423 cb->level_info->nblk_y / 64 - 1; 2424 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false); 2425 2426 cb_color_base = (tex->resource.gpu_address + cb->level_info->offset) >> 8; 2427 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max); 2428 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max); 2429 cb_color_attrib = cb->cb_color_attrib | 2430 S_028C74_TILE_MODE_INDEX(tile_mode_index); 2431 2432 if (tex->fmask.size) { 2433 if (sctx->b.chip_class >= CIK) 2434 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1); 2435 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index); 2436 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8; 2437 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max); 2438 } else { 2439 /* This must be set for fast clear to work without FMASK. */ 2440 if (sctx->b.chip_class >= CIK) 2441 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max); 2442 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index); 2443 cb_color_fmask = cb_color_base; 2444 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max); 2445 } 2446 2447 cb_color_info = cb->cb_color_info | tex->cb_color_info; 2448 2449 if (tex->dcc_offset && cb->level_info->dcc_enabled) { 2450 bool is_msaa_resolve_dst = state->cbufs[0] && 2451 state->cbufs[0]->texture->nr_samples > 1 && 2452 state->cbufs[1] == &cb->base && 2453 state->cbufs[1]->texture->nr_samples <= 1; 2454 2455 if (!is_msaa_resolve_dst) 2456 cb_color_info |= S_028C70_DCC_ENABLE(1); 2457 } 2458 2459 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 2460 sctx->b.chip_class >= VI ? 14 : 13); 2461 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */ 2462 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */ 2463 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */ 2464 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */ 2465 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */ 2466 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */ 2467 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */ 2468 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */ 2469 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */ 2470 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */ 2471 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */ 2472 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */ 2473 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */ 2474 2475 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */ 2476 radeon_emit(cs, (tex->resource.gpu_address + 2477 tex->dcc_offset + 2478 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8); 2479 } 2480 /* set CB_COLOR1_INFO for possible dual-src blending */ 2481 if (i == 1 && state->cbufs[0] && 2482 sctx->framebuffer.dirty_cbufs & (1 << 0)) { 2483 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, 2484 cb_color_info); 2485 i++; 2486 } 2487 for (; i < 8 ; i++) 2488 if (sctx->framebuffer.dirty_cbufs & (1 << i)) 2489 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); 2490 2491 /* ZS buffer. */ 2492 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) { 2493 struct r600_surface *zb = (struct r600_surface*)state->zsbuf; 2494 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture; 2495 2496 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, 2497 &rtex->resource, RADEON_USAGE_READWRITE, 2498 zb->base.texture->nr_samples > 1 ? 2499 RADEON_PRIO_DEPTH_BUFFER_MSAA : 2500 RADEON_PRIO_DEPTH_BUFFER); 2501 2502 if (zb->db_htile_data_base) { 2503 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, 2504 rtex->htile_buffer, RADEON_USAGE_READWRITE, 2505 RADEON_PRIO_HTILE); 2506 } 2507 2508 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); 2509 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base); 2510 2511 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9); 2512 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */ 2513 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */ 2514 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0)); 2515 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */ 2516 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */ 2517 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */ 2518 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */ 2519 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */ 2520 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */ 2521 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */ 2522 2523 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2); 2524 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */ 2525 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */ 2526 2527 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface); 2528 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2529 zb->pa_su_poly_offset_db_fmt_cntl); 2530 } else if (sctx->framebuffer.dirty_zsbuf) { 2531 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2); 2532 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */ 2533 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */ 2534 } 2535 2536 /* Framebuffer dimensions. */ 2537 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */ 2538 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR, 2539 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height)); 2540 2541 sctx->framebuffer.dirty_cbufs = 0; 2542 sctx->framebuffer.dirty_zsbuf = false; 2543} 2544 2545static void si_emit_msaa_sample_locs(struct si_context *sctx, 2546 struct r600_atom *atom) 2547{ 2548 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 2549 unsigned nr_samples = sctx->framebuffer.nr_samples; 2550 2551 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples : 2552 SI_NUM_SMOOTH_AA_SAMPLES); 2553} 2554 2555static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom) 2556{ 2557 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 2558 unsigned sc_mode_cntl_1 = 2559 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | 2560 S_028A4C_FORCE_EOV_REZ_ENABLE(1); 2561 2562 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples, 2563 sctx->ps_iter_samples, 2564 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0, 2565 sc_mode_cntl_1); 2566} 2567 2568 2569static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples) 2570{ 2571 struct si_context *sctx = (struct si_context *)ctx; 2572 2573 if (sctx->ps_iter_samples == min_samples) 2574 return; 2575 2576 sctx->ps_iter_samples = min_samples; 2577 2578 if (sctx->framebuffer.nr_samples > 1) 2579 si_mark_atom_dirty(sctx, &sctx->msaa_config); 2580} 2581 2582/* 2583 * Samplers 2584 */ 2585 2586/** 2587 * Build the sampler view descriptor for a buffer texture. 2588 * @param state 256-bit descriptor; only the high 128 bits are filled in 2589 */ 2590void 2591si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf, 2592 enum pipe_format format, 2593 unsigned first_element, unsigned last_element, 2594 uint32_t *state) 2595{ 2596 const struct util_format_description *desc; 2597 int first_non_void; 2598 uint64_t va; 2599 unsigned stride; 2600 unsigned num_records; 2601 unsigned num_format, data_format; 2602 2603 desc = util_format_description(format); 2604 first_non_void = util_format_get_first_non_void_channel(format); 2605 stride = desc->block.bits / 8; 2606 va = buf->gpu_address + first_element * stride; 2607 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void); 2608 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void); 2609 2610 num_records = last_element + 1 - first_element; 2611 num_records = MIN2(num_records, buf->b.b.width0 / stride); 2612 2613 if (screen->b.chip_class >= VI) 2614 num_records *= stride; 2615 2616 state[4] = va; 2617 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) | 2618 S_008F04_STRIDE(stride); 2619 state[6] = num_records; 2620 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | 2621 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | 2622 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | 2623 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | 2624 S_008F0C_NUM_FORMAT(num_format) | 2625 S_008F0C_DATA_FORMAT(data_format); 2626} 2627 2628/** 2629 * Build the sampler view descriptor for a texture. 2630 */ 2631void 2632si_make_texture_descriptor(struct si_screen *screen, 2633 struct r600_texture *tex, 2634 bool sampler, 2635 enum pipe_texture_target target, 2636 enum pipe_format pipe_format, 2637 const unsigned char state_swizzle[4], 2638 unsigned first_level, unsigned last_level, 2639 unsigned first_layer, unsigned last_layer, 2640 unsigned width, unsigned height, unsigned depth, 2641 uint32_t *state, 2642 uint32_t *fmask_state) 2643{ 2644 struct pipe_resource *res = &tex->resource.b.b; 2645 const struct util_format_description *desc; 2646 unsigned char swizzle[4]; 2647 int first_non_void; 2648 unsigned num_format, data_format, type; 2649 uint64_t va; 2650 2651 desc = util_format_description(pipe_format); 2652 2653 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) { 2654 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0}; 2655 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1}; 2656 2657 switch (pipe_format) { 2658 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2659 case PIPE_FORMAT_X24S8_UINT: 2660 case PIPE_FORMAT_X32_S8X24_UINT: 2661 case PIPE_FORMAT_X8Z24_UNORM: 2662 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle); 2663 break; 2664 default: 2665 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle); 2666 } 2667 } else { 2668 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle); 2669 } 2670 2671 first_non_void = util_format_get_first_non_void_channel(pipe_format); 2672 2673 switch (pipe_format) { 2674 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2675 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2676 break; 2677 default: 2678 if (first_non_void < 0) { 2679 if (util_format_is_compressed(pipe_format)) { 2680 switch (pipe_format) { 2681 case PIPE_FORMAT_DXT1_SRGB: 2682 case PIPE_FORMAT_DXT1_SRGBA: 2683 case PIPE_FORMAT_DXT3_SRGBA: 2684 case PIPE_FORMAT_DXT5_SRGBA: 2685 case PIPE_FORMAT_BPTC_SRGBA: 2686 case PIPE_FORMAT_ETC2_SRGB8: 2687 case PIPE_FORMAT_ETC2_SRGB8A1: 2688 case PIPE_FORMAT_ETC2_SRGBA8: 2689 num_format = V_008F14_IMG_NUM_FORMAT_SRGB; 2690 break; 2691 case PIPE_FORMAT_RGTC1_SNORM: 2692 case PIPE_FORMAT_LATC1_SNORM: 2693 case PIPE_FORMAT_RGTC2_SNORM: 2694 case PIPE_FORMAT_LATC2_SNORM: 2695 case PIPE_FORMAT_ETC2_R11_SNORM: 2696 case PIPE_FORMAT_ETC2_RG11_SNORM: 2697 /* implies float, so use SNORM/UNORM to determine 2698 whether data is signed or not */ 2699 case PIPE_FORMAT_BPTC_RGB_FLOAT: 2700 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 2701 break; 2702 default: 2703 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2704 break; 2705 } 2706 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) { 2707 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2708 } else { 2709 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2710 } 2711 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) { 2712 num_format = V_008F14_IMG_NUM_FORMAT_SRGB; 2713 } else { 2714 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2715 2716 switch (desc->channel[first_non_void].type) { 2717 case UTIL_FORMAT_TYPE_FLOAT: 2718 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2719 break; 2720 case UTIL_FORMAT_TYPE_SIGNED: 2721 if (desc->channel[first_non_void].normalized) 2722 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 2723 else if (desc->channel[first_non_void].pure_integer) 2724 num_format = V_008F14_IMG_NUM_FORMAT_SINT; 2725 else 2726 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED; 2727 break; 2728 case UTIL_FORMAT_TYPE_UNSIGNED: 2729 if (desc->channel[first_non_void].normalized) 2730 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2731 else if (desc->channel[first_non_void].pure_integer) 2732 num_format = V_008F14_IMG_NUM_FORMAT_UINT; 2733 else 2734 num_format = V_008F14_IMG_NUM_FORMAT_USCALED; 2735 } 2736 } 2737 } 2738 2739 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void); 2740 if (data_format == ~0) { 2741 data_format = 0; 2742 } 2743 2744 if (!sampler && 2745 (res->target == PIPE_TEXTURE_CUBE || 2746 res->target == PIPE_TEXTURE_CUBE_ARRAY || 2747 res->target == PIPE_TEXTURE_3D)) { 2748 /* For the purpose of shader images, treat cube maps and 3D 2749 * textures as 2D arrays. For 3D textures, the address 2750 * calculations for mipmaps are different, so we rely on the 2751 * caller to effectively disable mipmaps. 2752 */ 2753 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY; 2754 2755 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0)); 2756 } else { 2757 type = si_tex_dim(res->target, target, res->nr_samples); 2758 } 2759 2760 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) { 2761 height = 1; 2762 depth = res->array_size; 2763 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY || 2764 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) { 2765 if (sampler || res->target != PIPE_TEXTURE_3D) 2766 depth = res->array_size; 2767 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE) 2768 depth = res->array_size / 6; 2769 2770 state[0] = 0; 2771 state[1] = (S_008F14_DATA_FORMAT(data_format) | 2772 S_008F14_NUM_FORMAT(num_format)); 2773 state[2] = (S_008F18_WIDTH(width - 1) | 2774 S_008F18_HEIGHT(height - 1)); 2775 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) | 2776 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | 2777 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | 2778 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | 2779 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ? 2780 0 : first_level) | 2781 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ? 2782 util_logbase2(res->nr_samples) : 2783 last_level) | 2784 S_008F1C_POW2_PAD(res->last_level > 0) | 2785 S_008F1C_TYPE(type)); 2786 state[4] = S_008F20_DEPTH(depth - 1); 2787 state[5] = (S_008F24_BASE_ARRAY(first_layer) | 2788 S_008F24_LAST_ARRAY(last_layer)); 2789 state[6] = 0; 2790 state[7] = 0; 2791 2792 if (tex->dcc_offset) { 2793 unsigned swap = r600_translate_colorswap(pipe_format, FALSE); 2794 2795 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1); 2796 } else { 2797 /* The last dword is unused by hw. The shader uses it to clear 2798 * bits in the first dword of sampler state. 2799 */ 2800 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) { 2801 if (first_level == last_level) 2802 state[7] = C_008F30_MAX_ANISO_RATIO; 2803 else 2804 state[7] = 0xffffffff; 2805 } 2806 } 2807 2808 /* Initialize the sampler view for FMASK. */ 2809 if (tex->fmask.size) { 2810 uint32_t fmask_format; 2811 2812 va = tex->resource.gpu_address + tex->fmask.offset; 2813 2814 switch (res->nr_samples) { 2815 case 2: 2816 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2; 2817 break; 2818 case 4: 2819 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4; 2820 break; 2821 case 8: 2822 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8; 2823 break; 2824 default: 2825 assert(0); 2826 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID; 2827 } 2828 2829 fmask_state[0] = va >> 8; 2830 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) | 2831 S_008F14_DATA_FORMAT(fmask_format) | 2832 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT); 2833 fmask_state[2] = S_008F18_WIDTH(width - 1) | 2834 S_008F18_HEIGHT(height - 1); 2835 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) | 2836 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) | 2837 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | 2838 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) | 2839 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) | 2840 S_008F1C_TYPE(si_tex_dim(res->target, target, 0)); 2841 fmask_state[4] = S_008F20_DEPTH(depth - 1) | 2842 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1); 2843 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) | 2844 S_008F24_LAST_ARRAY(last_layer); 2845 fmask_state[6] = 0; 2846 fmask_state[7] = 0; 2847 } 2848} 2849 2850/** 2851 * Create a sampler view. 2852 * 2853 * @param ctx context 2854 * @param texture texture 2855 * @param state sampler view template 2856 * @param width0 width0 override (for compressed textures as int) 2857 * @param height0 height0 override (for compressed textures as int) 2858 * @param force_level set the base address to the level (for compressed textures) 2859 */ 2860struct pipe_sampler_view * 2861si_create_sampler_view_custom(struct pipe_context *ctx, 2862 struct pipe_resource *texture, 2863 const struct pipe_sampler_view *state, 2864 unsigned width0, unsigned height0, 2865 unsigned force_level) 2866{ 2867 struct si_context *sctx = (struct si_context*)ctx; 2868 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view); 2869 struct r600_texture *tmp = (struct r600_texture*)texture; 2870 unsigned base_level, first_level, last_level; 2871 unsigned char state_swizzle[4]; 2872 unsigned height, depth, width; 2873 unsigned last_layer = state->u.tex.last_layer; 2874 enum pipe_format pipe_format; 2875 const struct radeon_surf_level *surflevel; 2876 2877 if (!view) 2878 return NULL; 2879 2880 /* initialize base object */ 2881 view->base = *state; 2882 view->base.texture = NULL; 2883 view->base.reference.count = 1; 2884 view->base.context = ctx; 2885 2886 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */ 2887 if (!texture) { 2888 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) | 2889 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) | 2890 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) | 2891 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) | 2892 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D); 2893 return &view->base; 2894 } 2895 2896 pipe_resource_reference(&view->base.texture, texture); 2897 2898 if (state->format == PIPE_FORMAT_X24S8_UINT || 2899 state->format == PIPE_FORMAT_S8X24_UINT || 2900 state->format == PIPE_FORMAT_X32_S8X24_UINT || 2901 state->format == PIPE_FORMAT_S8_UINT) 2902 view->is_stencil_sampler = true; 2903 2904 /* Buffer resource. */ 2905 if (texture->target == PIPE_BUFFER) { 2906 si_make_buffer_descriptor(sctx->screen, 2907 (struct r600_resource *)texture, 2908 state->format, 2909 state->u.buf.first_element, 2910 state->u.buf.last_element, 2911 view->state); 2912 2913 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers); 2914 return &view->base; 2915 } 2916 2917 state_swizzle[0] = state->swizzle_r; 2918 state_swizzle[1] = state->swizzle_g; 2919 state_swizzle[2] = state->swizzle_b; 2920 state_swizzle[3] = state->swizzle_a; 2921 2922 base_level = 0; 2923 first_level = state->u.tex.first_level; 2924 last_level = state->u.tex.last_level; 2925 width = width0; 2926 height = height0; 2927 depth = texture->depth0; 2928 2929 if (force_level) { 2930 assert(force_level == first_level && 2931 force_level == last_level); 2932 base_level = force_level; 2933 first_level = 0; 2934 last_level = 0; 2935 width = u_minify(width, force_level); 2936 height = u_minify(height, force_level); 2937 depth = u_minify(depth, force_level); 2938 } 2939 2940 /* This is not needed if state trackers set last_layer correctly. */ 2941 if (state->target == PIPE_TEXTURE_1D || 2942 state->target == PIPE_TEXTURE_2D || 2943 state->target == PIPE_TEXTURE_RECT || 2944 state->target == PIPE_TEXTURE_CUBE) 2945 last_layer = state->u.tex.first_layer; 2946 2947 /* Texturing with separate depth and stencil. */ 2948 pipe_format = state->format; 2949 surflevel = tmp->surface.level; 2950 2951 if (tmp->is_depth && !tmp->is_flushing_texture) { 2952 switch (pipe_format) { 2953 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 2954 pipe_format = PIPE_FORMAT_Z32_FLOAT; 2955 break; 2956 case PIPE_FORMAT_X8Z24_UNORM: 2957 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2958 /* Z24 is always stored like this. */ 2959 pipe_format = PIPE_FORMAT_Z24X8_UNORM; 2960 break; 2961 case PIPE_FORMAT_X24S8_UINT: 2962 case PIPE_FORMAT_S8X24_UINT: 2963 case PIPE_FORMAT_X32_S8X24_UINT: 2964 pipe_format = PIPE_FORMAT_S8_UINT; 2965 surflevel = tmp->surface.stencil_level; 2966 break; 2967 default:; 2968 } 2969 } 2970 2971 si_make_texture_descriptor(sctx->screen, tmp, true, 2972 state->target, pipe_format, state_swizzle, 2973 first_level, last_level, 2974 state->u.tex.first_layer, last_layer, 2975 width, height, depth, 2976 view->state, view->fmask_state); 2977 2978 view->base_level_info = &surflevel[base_level]; 2979 view->base_level = base_level; 2980 view->block_width = util_format_get_blockwidth(pipe_format); 2981 return &view->base; 2982} 2983 2984static struct pipe_sampler_view * 2985si_create_sampler_view(struct pipe_context *ctx, 2986 struct pipe_resource *texture, 2987 const struct pipe_sampler_view *state) 2988{ 2989 return si_create_sampler_view_custom(ctx, texture, state, 2990 texture ? texture->width0 : 0, 2991 texture ? texture->height0 : 0, 0); 2992} 2993 2994static void si_sampler_view_destroy(struct pipe_context *ctx, 2995 struct pipe_sampler_view *state) 2996{ 2997 struct si_sampler_view *view = (struct si_sampler_view *)state; 2998 2999 if (state->texture && state->texture->target == PIPE_BUFFER) 3000 LIST_DELINIT(&view->list); 3001 3002 pipe_resource_reference(&state->texture, NULL); 3003 FREE(view); 3004} 3005 3006static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter) 3007{ 3008 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER || 3009 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER || 3010 (linear_filter && 3011 (wrap == PIPE_TEX_WRAP_CLAMP || 3012 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP)); 3013} 3014 3015static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state) 3016{ 3017 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST || 3018 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST; 3019 3020 return (state->border_color.ui[0] || state->border_color.ui[1] || 3021 state->border_color.ui[2] || state->border_color.ui[3]) && 3022 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) || 3023 wrap_mode_uses_border_color(state->wrap_t, linear_filter) || 3024 wrap_mode_uses_border_color(state->wrap_r, linear_filter)); 3025} 3026 3027static void *si_create_sampler_state(struct pipe_context *ctx, 3028 const struct pipe_sampler_state *state) 3029{ 3030 struct si_context *sctx = (struct si_context *)ctx; 3031 struct r600_common_screen *rscreen = sctx->b.screen; 3032 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state); 3033 unsigned border_color_type, border_color_index = 0; 3034 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso 3035 : state->max_anisotropy; 3036 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso); 3037 3038 if (!rstate) { 3039 return NULL; 3040 } 3041 3042 if (!sampler_state_needs_border_color(state)) 3043 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; 3044 else if (state->border_color.f[0] == 0 && 3045 state->border_color.f[1] == 0 && 3046 state->border_color.f[2] == 0 && 3047 state->border_color.f[3] == 0) 3048 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; 3049 else if (state->border_color.f[0] == 0 && 3050 state->border_color.f[1] == 0 && 3051 state->border_color.f[2] == 0 && 3052 state->border_color.f[3] == 1) 3053 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK; 3054 else if (state->border_color.f[0] == 1 && 3055 state->border_color.f[1] == 1 && 3056 state->border_color.f[2] == 1 && 3057 state->border_color.f[3] == 1) 3058 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE; 3059 else { 3060 int i; 3061 3062 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER; 3063 3064 /* Check if the border has been uploaded already. */ 3065 for (i = 0; i < sctx->border_color_count; i++) 3066 if (memcmp(&sctx->border_color_table[i], &state->border_color, 3067 sizeof(state->border_color)) == 0) 3068 break; 3069 3070 if (i >= SI_MAX_BORDER_COLORS) { 3071 /* Getting 4096 unique border colors is very unlikely. */ 3072 fprintf(stderr, "radeonsi: The border color table is full. " 3073 "Any new border colors will be just black. " 3074 "Please file a bug.\n"); 3075 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; 3076 } else { 3077 if (i == sctx->border_color_count) { 3078 /* Upload a new border color. */ 3079 memcpy(&sctx->border_color_table[i], &state->border_color, 3080 sizeof(state->border_color)); 3081 util_memcpy_cpu_to_le32(&sctx->border_color_map[i], 3082 &state->border_color, 3083 sizeof(state->border_color)); 3084 sctx->border_color_count++; 3085 } 3086 3087 border_color_index = i; 3088 } 3089 } 3090 3091 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | 3092 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) | 3093 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) | 3094 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) | 3095 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) | 3096 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) | 3097 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) | 3098 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI)); 3099 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | 3100 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8))); 3101 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) | 3102 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) | 3103 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) | 3104 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) | 3105 S_008F38_MIP_POINT_PRECLAMP(1) | 3106 S_008F38_DISABLE_LSB_CEIL(1) | 3107 S_008F38_FILTER_PREC_FIX(1) | 3108 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI)); 3109 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) | 3110 S_008F3C_BORDER_COLOR_TYPE(border_color_type); 3111 return rstate; 3112} 3113 3114static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask) 3115{ 3116 struct si_context *sctx = (struct si_context *)ctx; 3117 3118 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask) 3119 return; 3120 3121 sctx->sample_mask.sample_mask = sample_mask; 3122 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom); 3123} 3124 3125static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom) 3126{ 3127 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 3128 unsigned mask = sctx->sample_mask.sample_mask; 3129 3130 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2); 3131 radeon_emit(cs, mask | (mask << 16)); 3132 radeon_emit(cs, mask | (mask << 16)); 3133} 3134 3135static void si_delete_sampler_state(struct pipe_context *ctx, void *state) 3136{ 3137 free(state); 3138} 3139 3140/* 3141 * Vertex elements & buffers 3142 */ 3143 3144static void *si_create_vertex_elements(struct pipe_context *ctx, 3145 unsigned count, 3146 const struct pipe_vertex_element *elements) 3147{ 3148 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element); 3149 int i; 3150 3151 assert(count <= SI_MAX_ATTRIBS); 3152 if (!v) 3153 return NULL; 3154 3155 v->count = count; 3156 for (i = 0; i < count; ++i) { 3157 const struct util_format_description *desc; 3158 unsigned data_format, num_format; 3159 int first_non_void; 3160 3161 desc = util_format_description(elements[i].src_format); 3162 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format); 3163 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void); 3164 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void); 3165 3166 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | 3167 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | 3168 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | 3169 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | 3170 S_008F0C_NUM_FORMAT(num_format) | 3171 S_008F0C_DATA_FORMAT(data_format); 3172 v->format_size[i] = desc->block.bits / 8; 3173 } 3174 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); 3175 3176 return v; 3177} 3178 3179static void si_bind_vertex_elements(struct pipe_context *ctx, void *state) 3180{ 3181 struct si_context *sctx = (struct si_context *)ctx; 3182 struct si_vertex_element *v = (struct si_vertex_element*)state; 3183 3184 sctx->vertex_elements = v; 3185 sctx->vertex_buffers_dirty = true; 3186} 3187 3188static void si_delete_vertex_element(struct pipe_context *ctx, void *state) 3189{ 3190 struct si_context *sctx = (struct si_context *)ctx; 3191 3192 if (sctx->vertex_elements == state) 3193 sctx->vertex_elements = NULL; 3194 FREE(state); 3195} 3196 3197static void si_set_vertex_buffers(struct pipe_context *ctx, 3198 unsigned start_slot, unsigned count, 3199 const struct pipe_vertex_buffer *buffers) 3200{ 3201 struct si_context *sctx = (struct si_context *)ctx; 3202 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot; 3203 int i; 3204 3205 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer)); 3206 3207 if (buffers) { 3208 for (i = 0; i < count; i++) { 3209 const struct pipe_vertex_buffer *src = buffers + i; 3210 struct pipe_vertex_buffer *dsti = dst + i; 3211 3212 pipe_resource_reference(&dsti->buffer, src->buffer); 3213 dsti->buffer_offset = src->buffer_offset; 3214 dsti->stride = src->stride; 3215 r600_context_add_resource_size(ctx, src->buffer); 3216 } 3217 } else { 3218 for (i = 0; i < count; i++) { 3219 pipe_resource_reference(&dst[i].buffer, NULL); 3220 } 3221 } 3222 sctx->vertex_buffers_dirty = true; 3223} 3224 3225static void si_set_index_buffer(struct pipe_context *ctx, 3226 const struct pipe_index_buffer *ib) 3227{ 3228 struct si_context *sctx = (struct si_context *)ctx; 3229 3230 if (ib) { 3231 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer); 3232 memcpy(&sctx->index_buffer, ib, sizeof(*ib)); 3233 r600_context_add_resource_size(ctx, ib->buffer); 3234 } else { 3235 pipe_resource_reference(&sctx->index_buffer.buffer, NULL); 3236 } 3237} 3238 3239/* 3240 * Misc 3241 */ 3242 3243static void si_set_tess_state(struct pipe_context *ctx, 3244 const float default_outer_level[4], 3245 const float default_inner_level[2]) 3246{ 3247 struct si_context *sctx = (struct si_context *)ctx; 3248 struct pipe_constant_buffer cb; 3249 float array[8]; 3250 3251 memcpy(array, default_outer_level, sizeof(float) * 4); 3252 memcpy(array+4, default_inner_level, sizeof(float) * 2); 3253 3254 cb.buffer = NULL; 3255 cb.user_buffer = NULL; 3256 cb.buffer_size = sizeof(array); 3257 3258 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer, 3259 (void*)array, sizeof(array), 3260 &cb.buffer_offset); 3261 3262 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb); 3263 pipe_resource_reference(&cb.buffer, NULL); 3264} 3265 3266static void si_texture_barrier(struct pipe_context *ctx) 3267{ 3268 struct si_context *sctx = (struct si_context *)ctx; 3269 3270 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 | 3271 SI_CONTEXT_INV_GLOBAL_L2 | 3272 SI_CONTEXT_FLUSH_AND_INV_CB | 3273 SI_CONTEXT_CS_PARTIAL_FLUSH; 3274} 3275 3276static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) 3277{ 3278 struct si_context *sctx = (struct si_context *)ctx; 3279 3280 /* Subsequent commands must wait for all shader invocations to 3281 * complete. */ 3282 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | 3283 SI_CONTEXT_CS_PARTIAL_FLUSH; 3284 3285 if (flags & PIPE_BARRIER_CONSTANT_BUFFER) 3286 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 | 3287 SI_CONTEXT_INV_VMEM_L1; 3288 3289 if (flags & (PIPE_BARRIER_VERTEX_BUFFER | 3290 PIPE_BARRIER_SHADER_BUFFER | 3291 PIPE_BARRIER_TEXTURE | 3292 PIPE_BARRIER_IMAGE | 3293 PIPE_BARRIER_STREAMOUT_BUFFER | 3294 PIPE_BARRIER_GLOBAL_BUFFER)) { 3295 /* As far as I can tell, L1 contents are written back to L2 3296 * automatically at end of shader, but the contents of other 3297 * L1 caches might still be stale. */ 3298 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1; 3299 } 3300 3301 if (flags & PIPE_BARRIER_INDEX_BUFFER) { 3302 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1; 3303 3304 /* Indices are read through TC L2 since VI. */ 3305 if (sctx->screen->b.chip_class <= CIK) 3306 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2; 3307 } 3308 3309 if (flags & PIPE_BARRIER_FRAMEBUFFER) 3310 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER; 3311 3312 if (flags & (PIPE_BARRIER_MAPPED_BUFFER | 3313 PIPE_BARRIER_FRAMEBUFFER | 3314 PIPE_BARRIER_INDIRECT_BUFFER)) { 3315 /* Not sure if INV_GLOBAL_L2 is the best thing here. 3316 * 3317 * We need to make sure that TC L1 & L2 are written back to 3318 * memory, because neither CPU accesses nor CB fetches consider 3319 * TC, but there's no need to invalidate any TC cache lines. */ 3320 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2; 3321 } 3322} 3323 3324static void *si_create_blend_custom(struct si_context *sctx, unsigned mode) 3325{ 3326 struct pipe_blend_state blend; 3327 3328 memset(&blend, 0, sizeof(blend)); 3329 blend.independent_blend_enable = true; 3330 blend.rt[0].colormask = 0xf; 3331 return si_create_blend_state_mode(&sctx->b.b, &blend, mode); 3332} 3333 3334static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw, 3335 bool include_draw_vbo) 3336{ 3337 si_need_cs_space((struct si_context*)ctx); 3338} 3339 3340static void si_init_config(struct si_context *sctx); 3341 3342void si_init_state_functions(struct si_context *sctx) 3343{ 3344 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond); 3345 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin); 3346 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable); 3347 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors); 3348 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports); 3349 3350 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush); 3351 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state); 3352 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs); 3353 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state); 3354 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config); 3355 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask); 3356 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state); 3357 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color); 3358 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs); 3359 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state); 3360 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref); 3361 3362 sctx->b.b.create_blend_state = si_create_blend_state; 3363 sctx->b.b.bind_blend_state = si_bind_blend_state; 3364 sctx->b.b.delete_blend_state = si_delete_blend_state; 3365 sctx->b.b.set_blend_color = si_set_blend_color; 3366 3367 sctx->b.b.create_rasterizer_state = si_create_rs_state; 3368 sctx->b.b.bind_rasterizer_state = si_bind_rs_state; 3369 sctx->b.b.delete_rasterizer_state = si_delete_rs_state; 3370 3371 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state; 3372 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state; 3373 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state; 3374 3375 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx); 3376 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE); 3377 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS); 3378 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR); 3379 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS); 3380 3381 sctx->b.b.set_clip_state = si_set_clip_state; 3382 sctx->b.b.set_stencil_ref = si_set_stencil_ref; 3383 3384 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state; 3385 sctx->b.b.get_sample_position = cayman_get_sample_position; 3386 3387 sctx->b.b.create_sampler_state = si_create_sampler_state; 3388 sctx->b.b.delete_sampler_state = si_delete_sampler_state; 3389 3390 sctx->b.b.create_sampler_view = si_create_sampler_view; 3391 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy; 3392 3393 sctx->b.b.set_sample_mask = si_set_sample_mask; 3394 3395 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements; 3396 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements; 3397 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element; 3398 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers; 3399 sctx->b.b.set_index_buffer = si_set_index_buffer; 3400 3401 sctx->b.b.texture_barrier = si_texture_barrier; 3402 sctx->b.b.memory_barrier = si_memory_barrier; 3403 sctx->b.b.set_min_samples = si_set_min_samples; 3404 sctx->b.b.set_tess_state = si_set_tess_state; 3405 3406 sctx->b.b.set_active_query_state = si_set_active_query_state; 3407 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state; 3408 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space; 3409 3410 sctx->b.b.draw_vbo = si_draw_vbo; 3411 3412 si_init_config(sctx); 3413} 3414 3415static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen) 3416{ 3417 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id; 3418} 3419 3420static void si_query_opaque_metadata(struct r600_common_screen *rscreen, 3421 struct r600_texture *rtex, 3422 struct radeon_bo_metadata *md) 3423{ 3424 struct si_screen *sscreen = (struct si_screen*)rscreen; 3425 struct pipe_resource *res = &rtex->resource.b.b; 3426 static const unsigned char swizzle[] = { 3427 PIPE_SWIZZLE_X, 3428 PIPE_SWIZZLE_Y, 3429 PIPE_SWIZZLE_Z, 3430 PIPE_SWIZZLE_W 3431 }; 3432 uint32_t desc[8], i; 3433 bool is_array = util_resource_is_array_texture(res); 3434 3435 /* DRM 2.x.x doesn't support this. */ 3436 if (rscreen->info.drm_major != 3) 3437 return; 3438 3439 assert(rtex->fmask.size == 0); 3440 3441 /* Metadata image format format version 1: 3442 * [0] = 1 (metadata format identifier) 3443 * [1] = (VENDOR_ID << 16) | PCI_ID 3444 * [2:9] = image descriptor for the whole resource 3445 * [2] is always 0, because the base address is cleared 3446 * [9] is the DCC offset bits [39:8] from the beginning of 3447 * the buffer 3448 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level 3449 */ 3450 3451 md->metadata[0] = 1; /* metadata image format version 1 */ 3452 3453 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */ 3454 md->metadata[1] = si_get_bo_metadata_word1(rscreen); 3455 3456 si_make_texture_descriptor(sscreen, rtex, true, 3457 res->target, res->format, 3458 swizzle, 0, res->last_level, 0, 3459 is_array ? res->array_size - 1 : 0, 3460 res->width0, res->height0, res->depth0, 3461 desc, NULL); 3462 3463 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0, 3464 rtex->surface.blk_w, false, desc); 3465 3466 /* Clear the base address and set the relative DCC offset. */ 3467 desc[0] = 0; 3468 desc[1] &= C_008F14_BASE_ADDRESS_HI; 3469 desc[7] = rtex->dcc_offset >> 8; 3470 3471 /* Dwords [2:9] contain the image descriptor. */ 3472 memcpy(&md->metadata[2], desc, sizeof(desc)); 3473 3474 /* Dwords [10:..] contain the mipmap level offsets. */ 3475 for (i = 0; i <= res->last_level; i++) 3476 md->metadata[10+i] = rtex->surface.level[i].offset >> 8; 3477 3478 md->size_metadata = (11 + res->last_level) * 4; 3479} 3480 3481static void si_apply_opaque_metadata(struct r600_common_screen *rscreen, 3482 struct r600_texture *rtex, 3483 struct radeon_bo_metadata *md) 3484{ 3485 uint32_t *desc = &md->metadata[2]; 3486 3487 if (rscreen->chip_class < VI) 3488 return; 3489 3490 /* Return if DCC is enabled. The texture should be set up with it 3491 * already. 3492 */ 3493 if (md->size_metadata >= 11 * 4 && 3494 md->metadata[0] != 0 && 3495 md->metadata[1] == si_get_bo_metadata_word1(rscreen) && 3496 G_008F28_COMPRESSION_EN(desc[6])) { 3497 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8)); 3498 return; 3499 } 3500 3501 /* Disable DCC. These are always set by texture_from_handle and must 3502 * be cleared here. 3503 */ 3504 rtex->dcc_offset = 0; 3505} 3506 3507void si_init_screen_state_functions(struct si_screen *sscreen) 3508{ 3509 sscreen->b.query_opaque_metadata = si_query_opaque_metadata; 3510 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata; 3511} 3512 3513static void 3514si_write_harvested_raster_configs(struct si_context *sctx, 3515 struct si_pm4_state *pm4, 3516 unsigned raster_config, 3517 unsigned raster_config_1) 3518{ 3519 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1); 3520 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1); 3521 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask; 3522 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16); 3523 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2); 3524 unsigned rb_per_se = num_rb / num_se; 3525 unsigned se_mask[4]; 3526 unsigned se; 3527 3528 se_mask[0] = ((1 << rb_per_se) - 1); 3529 se_mask[1] = (se_mask[0] << rb_per_se); 3530 se_mask[2] = (se_mask[1] << rb_per_se); 3531 se_mask[3] = (se_mask[2] << rb_per_se); 3532 3533 se_mask[0] &= rb_mask; 3534 se_mask[1] &= rb_mask; 3535 se_mask[2] &= rb_mask; 3536 se_mask[3] &= rb_mask; 3537 3538 assert(num_se == 1 || num_se == 2 || num_se == 4); 3539 assert(sh_per_se == 1 || sh_per_se == 2); 3540 assert(rb_per_pkr == 1 || rb_per_pkr == 2); 3541 3542 /* XXX: I can't figure out what the *_XSEL and *_YSEL 3543 * fields are for, so I'm leaving them as their default 3544 * values. */ 3545 3546 for (se = 0; se < num_se; se++) { 3547 unsigned raster_config_se = raster_config; 3548 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 3549 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 3550 int idx = (se / 2) * 2; 3551 3552 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 3553 raster_config_se &= C_028350_SE_MAP; 3554 3555 if (!se_mask[idx]) { 3556 raster_config_se |= 3557 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3); 3558 } else { 3559 raster_config_se |= 3560 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0); 3561 } 3562 } 3563 3564 pkr0_mask &= rb_mask; 3565 pkr1_mask &= rb_mask; 3566 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 3567 raster_config_se &= C_028350_PKR_MAP; 3568 3569 if (!pkr0_mask) { 3570 raster_config_se |= 3571 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3); 3572 } else { 3573 raster_config_se |= 3574 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0); 3575 } 3576 } 3577 3578 if (rb_per_se >= 2) { 3579 unsigned rb0_mask = 1 << (se * rb_per_se); 3580 unsigned rb1_mask = rb0_mask << 1; 3581 3582 rb0_mask &= rb_mask; 3583 rb1_mask &= rb_mask; 3584 if (!rb0_mask || !rb1_mask) { 3585 raster_config_se &= C_028350_RB_MAP_PKR0; 3586 3587 if (!rb0_mask) { 3588 raster_config_se |= 3589 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3); 3590 } else { 3591 raster_config_se |= 3592 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0); 3593 } 3594 } 3595 3596 if (rb_per_se > 2) { 3597 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 3598 rb1_mask = rb0_mask << 1; 3599 rb0_mask &= rb_mask; 3600 rb1_mask &= rb_mask; 3601 if (!rb0_mask || !rb1_mask) { 3602 raster_config_se &= C_028350_RB_MAP_PKR1; 3603 3604 if (!rb0_mask) { 3605 raster_config_se |= 3606 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3); 3607 } else { 3608 raster_config_se |= 3609 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0); 3610 } 3611 } 3612 } 3613 } 3614 3615 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ 3616 if (sctx->b.chip_class < CIK) 3617 si_pm4_set_reg(pm4, GRBM_GFX_INDEX, 3618 SE_INDEX(se) | SH_BROADCAST_WRITES | 3619 INSTANCE_BROADCAST_WRITES); 3620 else 3621 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX, 3622 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) | 3623 S_030800_INSTANCE_BROADCAST_WRITES(1)); 3624 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se); 3625 } 3626 3627 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ 3628 if (sctx->b.chip_class < CIK) 3629 si_pm4_set_reg(pm4, GRBM_GFX_INDEX, 3630 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES | 3631 INSTANCE_BROADCAST_WRITES); 3632 else { 3633 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX, 3634 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) | 3635 S_030800_INSTANCE_BROADCAST_WRITES(1)); 3636 3637 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || 3638 (!se_mask[2] && !se_mask[3]))) { 3639 raster_config_1 &= C_028354_SE_PAIR_MAP; 3640 3641 if (!se_mask[0] && !se_mask[1]) { 3642 raster_config_1 |= 3643 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3); 3644 } else { 3645 raster_config_1 |= 3646 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0); 3647 } 3648 } 3649 3650 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); 3651 } 3652} 3653 3654static void si_init_config(struct si_context *sctx) 3655{ 3656 struct si_screen *sscreen = sctx->screen; 3657 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16); 3658 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask; 3659 unsigned raster_config, raster_config_1; 3660 uint64_t border_color_va = sctx->border_color_buffer->gpu_address; 3661 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 3662 int i; 3663 3664 if (!pm4) 3665 return; 3666 3667 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL); 3668 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1)); 3669 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1)); 3670 si_pm4_cmd_end(pm4, false); 3671 3672 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64)); 3673 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0)); 3674 3675 /* FIXME calculate these values somehow ??? */ 3676 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES); 3677 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40); 3678 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2); 3679 3680 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); 3681 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); 3682 3683 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); 3684 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); 3685 if (sctx->b.chip_class < CIK) 3686 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | 3687 S_008A14_CLIP_VTX_REORDER_ENA(1)); 3688 3689 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210); 3690 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98); 3691 3692 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0); 3693 3694 for (i = 0; i < 16; i++) { 3695 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0); 3696 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0)); 3697 } 3698 3699 switch (sctx->screen->b.family) { 3700 case CHIP_TAHITI: 3701 case CHIP_PITCAIRN: 3702 raster_config = 0x2a00126a; 3703 raster_config_1 = 0x00000000; 3704 break; 3705 case CHIP_VERDE: 3706 raster_config = 0x0000124a; 3707 raster_config_1 = 0x00000000; 3708 break; 3709 case CHIP_OLAND: 3710 raster_config = 0x00000082; 3711 raster_config_1 = 0x00000000; 3712 break; 3713 case CHIP_HAINAN: 3714 raster_config = 0x00000000; 3715 raster_config_1 = 0x00000000; 3716 break; 3717 case CHIP_BONAIRE: 3718 raster_config = 0x16000012; 3719 raster_config_1 = 0x00000000; 3720 break; 3721 case CHIP_HAWAII: 3722 raster_config = 0x3a00161a; 3723 raster_config_1 = 0x0000002e; 3724 break; 3725 case CHIP_FIJI: 3726 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) { 3727 /* old kernels with old tiling config */ 3728 raster_config = 0x16000012; 3729 raster_config_1 = 0x0000002a; 3730 } else { 3731 raster_config = 0x3a00161a; 3732 raster_config_1 = 0x0000002e; 3733 } 3734 break; 3735 case CHIP_POLARIS10: 3736 raster_config = 0x16000012; 3737 raster_config_1 = 0x0000002a; 3738 break; 3739 case CHIP_POLARIS11: 3740 raster_config = 0x16000012; 3741 raster_config_1 = 0x00000000; 3742 break; 3743 case CHIP_TONGA: 3744 raster_config = 0x16000012; 3745 raster_config_1 = 0x0000002a; 3746 break; 3747 case CHIP_ICELAND: 3748 if (num_rb == 1) 3749 raster_config = 0x00000000; 3750 else 3751 raster_config = 0x00000002; 3752 raster_config_1 = 0x00000000; 3753 break; 3754 case CHIP_CARRIZO: 3755 raster_config = 0x00000002; 3756 raster_config_1 = 0x00000000; 3757 break; 3758 case CHIP_KAVERI: 3759 /* KV should be 0x00000002, but that causes problems with radeon */ 3760 raster_config = 0x00000000; /* 0x00000002 */ 3761 raster_config_1 = 0x00000000; 3762 break; 3763 case CHIP_KABINI: 3764 case CHIP_MULLINS: 3765 case CHIP_STONEY: 3766 raster_config = 0x00000000; 3767 raster_config_1 = 0x00000000; 3768 break; 3769 default: 3770 fprintf(stderr, 3771 "radeonsi: Unknown GPU, using 0 for raster_config\n"); 3772 raster_config = 0x00000000; 3773 raster_config_1 = 0x00000000; 3774 break; 3775 } 3776 3777 /* Always use the default config when all backends are enabled 3778 * (or when we failed to determine the enabled backends). 3779 */ 3780 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) { 3781 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 3782 raster_config); 3783 if (sctx->b.chip_class >= CIK) 3784 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 3785 raster_config_1); 3786 } else { 3787 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1); 3788 } 3789 3790 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); 3791 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1)); 3792 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, 3793 S_028244_BR_X(16384) | S_028244_BR_Y(16384)); 3794 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0); 3795 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, 3796 S_028034_BR_X(16384) | S_028034_BR_Y(16384)); 3797 3798 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); 3799 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 3800 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */ 3801 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0); 3802 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0); 3803 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); 3804 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); 3805 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); 3806 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 3807 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 3808 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE)); 3809 3810 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); 3811 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); 3812 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0); 3813 3814 if (sctx->b.chip_class >= CIK) { 3815 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0); 3816 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff)); 3817 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff)); 3818 3819 if (sscreen->b.info.num_good_compute_units / 3820 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) { 3821 /* Too few available compute units per SH. Disallowing 3822 * VS to run on CU0 could hurt us more than late VS 3823 * allocation would help. 3824 * 3825 * LATE_ALLOC_VS = 2 is the highest safe number. 3826 */ 3827 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff)); 3828 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff)); 3829 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2)); 3830 } else { 3831 /* Set LATE_ALLOC_VS == 31. It should be less than 3832 * the number of scratch waves. Limitations: 3833 * - VS can't execute on CU0. 3834 * - If HS writes outputs to LDS, LS can't execute on CU0. 3835 */ 3836 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe)); 3837 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe)); 3838 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31)); 3839 } 3840 3841 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff)); 3842 } 3843 3844 if (sctx->b.chip_class >= VI) { 3845 unsigned vgt_tess_distribution; 3846 3847 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL, 3848 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) | 3849 S_028424_OVERWRITE_COMBINER_WATERMARK(4)); 3850 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30); 3851 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32); 3852 3853 vgt_tess_distribution = 3854 S_028B50_ACCUM_ISOLINE(32) | 3855 S_028B50_ACCUM_TRI(11) | 3856 S_028B50_ACCUM_QUAD(11) | 3857 S_028B50_DONUT_SPLIT(16); 3858 3859 /* Testing with Unigine Heaven extreme tesselation yielded best results 3860 * with TRAP_SPLIT = 3. 3861 */ 3862 if (sctx->b.family == CHIP_FIJI || 3863 sctx->b.family >= CHIP_POLARIS10) 3864 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3); 3865 3866 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution); 3867 } 3868 3869 if (sctx->b.family == CHIP_STONEY) 3870 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0); 3871 3872 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8); 3873 if (sctx->b.chip_class >= CIK) 3874 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40); 3875 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ, 3876 RADEON_PRIO_BORDER_COLORS); 3877 3878 si_pm4_upload_indirect_buffer(sctx, pm4); 3879 sctx->init_config = pm4; 3880} 3881