si_state.c revision 8662e66bf237a820a704df112718be599136098b
1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Christian König <christian.koenig@amd.com> 25 */ 26 27#include "util/u_memory.h" 28#include "util/u_framebuffer.h" 29#include "util/u_blitter.h" 30#include "util/u_helpers.h" 31#include "util/u_math.h" 32#include "util/u_pack_color.h" 33#include "util/u_upload_mgr.h" 34#include "util/u_format_s3tc.h" 35#include "tgsi/tgsi_parse.h" 36#include "tgsi/tgsi_scan.h" 37#include "si_pipe.h" 38#include "si_shader.h" 39#include "si_state.h" 40#include "../radeon/r600_cs.h" 41#include "sid.h" 42 43static uint32_t cik_num_banks(struct si_screen *rscreen, unsigned bpe, unsigned tile_split) 44{ 45 if (rscreen->b.info.cik_macrotile_mode_array_valid) { 46 unsigned index, tileb; 47 48 tileb = 8 * 8 * bpe; 49 tileb = MIN2(tile_split, tileb); 50 51 for (index = 0; tileb > 64; index++) { 52 tileb >>= 1; 53 } 54 55 assert(index < 16); 56 57 return (rscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3; 58 } 59 60 /* The old way. */ 61 switch (rscreen->b.tiling_info.num_banks) { 62 case 2: 63 return V_02803C_ADDR_SURF_2_BANK; 64 case 4: 65 return V_02803C_ADDR_SURF_4_BANK; 66 case 8: 67 default: 68 return V_02803C_ADDR_SURF_8_BANK; 69 case 16: 70 return V_02803C_ADDR_SURF_16_BANK; 71 } 72} 73 74static unsigned cik_tile_split(unsigned tile_split) 75{ 76 switch (tile_split) { 77 case 64: 78 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B; 79 break; 80 case 128: 81 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B; 82 break; 83 case 256: 84 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B; 85 break; 86 case 512: 87 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B; 88 break; 89 default: 90 case 1024: 91 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB; 92 break; 93 case 2048: 94 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB; 95 break; 96 case 4096: 97 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB; 98 break; 99 } 100 return tile_split; 101} 102 103static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect) 104{ 105 switch (macro_tile_aspect) { 106 default: 107 case 1: 108 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1; 109 break; 110 case 2: 111 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2; 112 break; 113 case 4: 114 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4; 115 break; 116 case 8: 117 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8; 118 break; 119 } 120 return macro_tile_aspect; 121} 122 123static unsigned cik_bank_wh(unsigned bankwh) 124{ 125 switch (bankwh) { 126 default: 127 case 1: 128 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1; 129 break; 130 case 2: 131 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2; 132 break; 133 case 4: 134 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4; 135 break; 136 case 8: 137 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8; 138 break; 139 } 140 return bankwh; 141} 142 143static unsigned cik_db_pipe_config(struct si_screen *rscreen, unsigned tile_mode) 144{ 145 if (rscreen->b.info.si_tile_mode_array_valid) { 146 uint32_t gb_tile_mode = rscreen->b.info.si_tile_mode_array[tile_mode]; 147 148 return G_009910_PIPE_CONFIG(gb_tile_mode); 149 } 150 151 /* This is probably broken for a lot of chips, but it's only used 152 * if the kernel cannot return the tile mode array for CIK. */ 153 switch (rscreen->b.info.r600_num_tile_pipes) { 154 case 16: 155 return V_02803C_X_ADDR_SURF_P16_32X32_16X16; 156 case 8: 157 return V_02803C_X_ADDR_SURF_P8_32X32_16X16; 158 case 4: 159 default: 160 if (rscreen->b.info.r600_num_backends == 4) 161 return V_02803C_X_ADDR_SURF_P4_16X16; 162 else 163 return V_02803C_X_ADDR_SURF_P4_8X16; 164 case 2: 165 return V_02803C_ADDR_SURF_P2; 166 } 167} 168 169/* 170 * inferred framebuffer and blender state 171 */ 172static void si_update_fb_blend_state(struct si_context *sctx) 173{ 174 struct si_pm4_state *pm4; 175 struct si_state_blend *blend = sctx->queued.named.blend; 176 uint32_t mask; 177 178 if (blend == NULL) 179 return; 180 181 pm4 = si_pm4_alloc_state(sctx); 182 if (pm4 == NULL) 183 return; 184 185 mask = (1ULL << ((unsigned)sctx->framebuffer.nr_cbufs * 4)) - 1; 186 mask &= blend->cb_target_mask; 187 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask); 188 189 si_pm4_set_state(sctx, fb_blend, pm4); 190} 191 192/* 193 * Blender functions 194 */ 195 196static uint32_t si_translate_blend_function(int blend_func) 197{ 198 switch (blend_func) { 199 case PIPE_BLEND_ADD: 200 return V_028780_COMB_DST_PLUS_SRC; 201 case PIPE_BLEND_SUBTRACT: 202 return V_028780_COMB_SRC_MINUS_DST; 203 case PIPE_BLEND_REVERSE_SUBTRACT: 204 return V_028780_COMB_DST_MINUS_SRC; 205 case PIPE_BLEND_MIN: 206 return V_028780_COMB_MIN_DST_SRC; 207 case PIPE_BLEND_MAX: 208 return V_028780_COMB_MAX_DST_SRC; 209 default: 210 R600_ERR("Unknown blend function %d\n", blend_func); 211 assert(0); 212 break; 213 } 214 return 0; 215} 216 217static uint32_t si_translate_blend_factor(int blend_fact) 218{ 219 switch (blend_fact) { 220 case PIPE_BLENDFACTOR_ONE: 221 return V_028780_BLEND_ONE; 222 case PIPE_BLENDFACTOR_SRC_COLOR: 223 return V_028780_BLEND_SRC_COLOR; 224 case PIPE_BLENDFACTOR_SRC_ALPHA: 225 return V_028780_BLEND_SRC_ALPHA; 226 case PIPE_BLENDFACTOR_DST_ALPHA: 227 return V_028780_BLEND_DST_ALPHA; 228 case PIPE_BLENDFACTOR_DST_COLOR: 229 return V_028780_BLEND_DST_COLOR; 230 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 231 return V_028780_BLEND_SRC_ALPHA_SATURATE; 232 case PIPE_BLENDFACTOR_CONST_COLOR: 233 return V_028780_BLEND_CONSTANT_COLOR; 234 case PIPE_BLENDFACTOR_CONST_ALPHA: 235 return V_028780_BLEND_CONSTANT_ALPHA; 236 case PIPE_BLENDFACTOR_ZERO: 237 return V_028780_BLEND_ZERO; 238 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 239 return V_028780_BLEND_ONE_MINUS_SRC_COLOR; 240 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 241 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; 242 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 243 return V_028780_BLEND_ONE_MINUS_DST_ALPHA; 244 case PIPE_BLENDFACTOR_INV_DST_COLOR: 245 return V_028780_BLEND_ONE_MINUS_DST_COLOR; 246 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 247 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; 248 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 249 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; 250 case PIPE_BLENDFACTOR_SRC1_COLOR: 251 return V_028780_BLEND_SRC1_COLOR; 252 case PIPE_BLENDFACTOR_SRC1_ALPHA: 253 return V_028780_BLEND_SRC1_ALPHA; 254 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 255 return V_028780_BLEND_INV_SRC1_COLOR; 256 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 257 return V_028780_BLEND_INV_SRC1_ALPHA; 258 default: 259 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 260 assert(0); 261 break; 262 } 263 return 0; 264} 265 266static void *si_create_blend_state_mode(struct pipe_context *ctx, 267 const struct pipe_blend_state *state, 268 unsigned mode) 269{ 270 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend); 271 struct si_pm4_state *pm4 = &blend->pm4; 272 273 uint32_t color_control = 0; 274 275 if (blend == NULL) 276 return NULL; 277 278 blend->alpha_to_one = state->alpha_to_one; 279 280 if (state->logicop_enable) { 281 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4)); 282 } else { 283 color_control |= S_028808_ROP3(0xcc); 284 } 285 286 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 287 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) | 288 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | 289 S_028B70_ALPHA_TO_MASK_OFFSET1(2) | 290 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | 291 S_028B70_ALPHA_TO_MASK_OFFSET3(2)); 292 293 blend->cb_target_mask = 0; 294 for (int i = 0; i < 8; i++) { 295 /* state->rt entries > 0 only written if independent blending */ 296 const int j = state->independent_blend_enable ? i : 0; 297 298 unsigned eqRGB = state->rt[j].rgb_func; 299 unsigned srcRGB = state->rt[j].rgb_src_factor; 300 unsigned dstRGB = state->rt[j].rgb_dst_factor; 301 unsigned eqA = state->rt[j].alpha_func; 302 unsigned srcA = state->rt[j].alpha_src_factor; 303 unsigned dstA = state->rt[j].alpha_dst_factor; 304 305 unsigned blend_cntl = 0; 306 307 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 308 blend->cb_target_mask |= state->rt[j].colormask << (4 * i); 309 310 if (!state->rt[j].blend_enable) { 311 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 312 continue; 313 } 314 315 blend_cntl |= S_028780_ENABLE(1); 316 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); 317 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); 318 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); 319 320 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 321 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); 322 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); 323 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); 324 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); 325 } 326 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 327 } 328 329 if (blend->cb_target_mask) { 330 color_control |= S_028808_MODE(mode); 331 } else { 332 color_control |= S_028808_MODE(V_028808_CB_DISABLE); 333 } 334 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); 335 336 return blend; 337} 338 339static void *si_create_blend_state(struct pipe_context *ctx, 340 const struct pipe_blend_state *state) 341{ 342 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL); 343} 344 345static void si_bind_blend_state(struct pipe_context *ctx, void *state) 346{ 347 struct si_context *sctx = (struct si_context *)ctx; 348 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state); 349 si_update_fb_blend_state(sctx); 350} 351 352static void si_delete_blend_state(struct pipe_context *ctx, void *state) 353{ 354 struct si_context *sctx = (struct si_context *)ctx; 355 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state); 356} 357 358static void si_set_blend_color(struct pipe_context *ctx, 359 const struct pipe_blend_color *state) 360{ 361 struct si_context *sctx = (struct si_context *)ctx; 362 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 363 364 if (pm4 == NULL) 365 return; 366 367 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0])); 368 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1])); 369 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2])); 370 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3])); 371 372 si_pm4_set_state(sctx, blend_color, pm4); 373} 374 375/* 376 * Clipping, scissors and viewport 377 */ 378 379static void si_set_clip_state(struct pipe_context *ctx, 380 const struct pipe_clip_state *state) 381{ 382 struct si_context *sctx = (struct si_context *)ctx; 383 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 384 struct pipe_constant_buffer cb; 385 386 if (pm4 == NULL) 387 return; 388 389 for (int i = 0; i < 6; i++) { 390 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16, 391 fui(state->ucp[i][0])); 392 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16, 393 fui(state->ucp[i][1])); 394 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16, 395 fui(state->ucp[i][2])); 396 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16, 397 fui(state->ucp[i][3])); 398 } 399 400 cb.buffer = NULL; 401 cb.user_buffer = state->ucp; 402 cb.buffer_offset = 0; 403 cb.buffer_size = 4*4*8; 404 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb); 405 pipe_resource_reference(&cb.buffer, NULL); 406 407 si_pm4_set_state(sctx, clip, pm4); 408} 409 410static void si_set_scissor_states(struct pipe_context *ctx, 411 unsigned start_slot, 412 unsigned num_scissors, 413 const struct pipe_scissor_state *state) 414{ 415 struct si_context *sctx = (struct si_context *)ctx; 416 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 417 uint32_t tl, br; 418 419 if (pm4 == NULL) 420 return; 421 422 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny); 423 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 424 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl); 425 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br); 426 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl); 427 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br); 428 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl); 429 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br); 430 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl); 431 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br); 432 433 si_pm4_set_state(sctx, scissor, pm4); 434} 435 436static void si_set_viewport_states(struct pipe_context *ctx, 437 unsigned start_slot, 438 unsigned num_viewports, 439 const struct pipe_viewport_state *state) 440{ 441 struct si_context *sctx = (struct si_context *)ctx; 442 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport); 443 struct si_pm4_state *pm4 = &viewport->pm4; 444 445 if (viewport == NULL) 446 return; 447 448 viewport->viewport = *state; 449 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0])); 450 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0])); 451 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1])); 452 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1])); 453 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2])); 454 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2])); 455 456 si_pm4_set_state(sctx, viewport, viewport); 457} 458 459/* 460 * inferred state between framebuffer and rasterizer 461 */ 462static void si_update_fb_rs_state(struct si_context *sctx) 463{ 464 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 465 struct si_pm4_state *pm4; 466 unsigned offset_db_fmt_cntl = 0, depth; 467 float offset_units; 468 469 if (!rs || !sctx->framebuffer.zsbuf) 470 return; 471 472 offset_units = sctx->queued.named.rasterizer->offset_units; 473 switch (sctx->framebuffer.zsbuf->texture->format) { 474 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 475 case PIPE_FORMAT_X8Z24_UNORM: 476 case PIPE_FORMAT_Z24X8_UNORM: 477 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 478 depth = -24; 479 offset_units *= 2.0f; 480 break; 481 case PIPE_FORMAT_Z32_FLOAT: 482 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 483 depth = -23; 484 offset_units *= 1.0f; 485 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 486 break; 487 case PIPE_FORMAT_Z16_UNORM: 488 depth = -16; 489 offset_units *= 4.0f; 490 break; 491 default: 492 return; 493 } 494 495 pm4 = si_pm4_alloc_state(sctx); 496 497 if (pm4 == NULL) 498 return; 499 500 /* FIXME some of those reg can be computed with cso */ 501 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 502 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 503 fui(sctx->queued.named.rasterizer->offset_scale)); 504 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units)); 505 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 506 fui(sctx->queued.named.rasterizer->offset_scale)); 507 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units)); 508 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl); 509 510 si_pm4_set_state(sctx, fb_rs, pm4); 511} 512 513/* 514 * Rasterizer 515 */ 516 517static uint32_t si_translate_fill(uint32_t func) 518{ 519 switch(func) { 520 case PIPE_POLYGON_MODE_FILL: 521 return V_028814_X_DRAW_TRIANGLES; 522 case PIPE_POLYGON_MODE_LINE: 523 return V_028814_X_DRAW_LINES; 524 case PIPE_POLYGON_MODE_POINT: 525 return V_028814_X_DRAW_POINTS; 526 default: 527 assert(0); 528 return V_028814_X_DRAW_POINTS; 529 } 530} 531 532static void *si_create_rs_state(struct pipe_context *ctx, 533 const struct pipe_rasterizer_state *state) 534{ 535 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer); 536 struct si_pm4_state *pm4 = &rs->pm4; 537 unsigned tmp; 538 unsigned prov_vtx = 1, polygon_dual_mode; 539 unsigned clip_rule; 540 float psize_min, psize_max; 541 542 if (rs == NULL) { 543 return NULL; 544 } 545 546 rs->two_side = state->light_twoside; 547 rs->multisample_enable = state->multisample; 548 rs->clip_plane_enable = state->clip_plane_enable; 549 rs->line_stipple_enable = state->line_stipple_enable; 550 551 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 552 state->fill_back != PIPE_POLYGON_MODE_FILL); 553 554 if (state->flatshade_first) 555 prov_vtx = 0; 556 557 rs->flatshade = state->flatshade; 558 rs->sprite_coord_enable = state->sprite_coord_enable; 559 rs->pa_sc_line_stipple = state->line_stipple_enable ? 560 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 561 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 562 rs->pa_su_sc_mode_cntl = 563 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 564 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 565 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 566 S_028814_FACE(!state->front_ccw) | 567 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 568 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 569 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 570 S_028814_POLY_MODE(polygon_dual_mode) | 571 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | 572 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)); 573 rs->pa_cl_clip_cntl = 574 S_028810_PS_UCP_MODE(3) | 575 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 576 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 577 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) | 578 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 579 580 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 581 582 /* offset */ 583 rs->offset_units = state->offset_units; 584 rs->offset_scale = state->offset_scale * 12.0f; 585 586 tmp = S_0286D4_FLAT_SHADE_ENA(1); 587 if (state->sprite_coord_enable) { 588 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 589 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | 590 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | 591 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | 592 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1); 593 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 594 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 595 } 596 } 597 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp); 598 599 /* point size 12.4 fixed point */ 600 tmp = (unsigned)(state->point_size * 8.0); 601 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 602 603 if (state->point_size_per_vertex) { 604 psize_min = util_get_min_point_size(state); 605 psize_max = 8192; 606 } else { 607 /* Force the point size to be as if the vertex output was disabled. */ 608 psize_min = state->point_size; 609 psize_max = state->point_size; 610 } 611 /* Divide by two, because 0.5 = 1 pixel. */ 612 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX, 613 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) | 614 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2))); 615 616 tmp = (unsigned)state->line_width * 8; 617 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); 618 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0, 619 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) | 620 S_028A48_MSAA_ENABLE(state->multisample)); 621 622 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL, 623 S_028BE4_PIX_CENTER(state->half_pixel_center) | 624 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH)); 625 626 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 627 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule); 628 629 return rs; 630} 631 632static void si_bind_rs_state(struct pipe_context *ctx, void *state) 633{ 634 struct si_context *sctx = (struct si_context *)ctx; 635 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state; 636 637 if (state == NULL) 638 return; 639 640 // TODO 641 sctx->sprite_coord_enable = rs->sprite_coord_enable; 642 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; 643 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl; 644 645 si_pm4_bind_state(sctx, rasterizer, rs); 646 si_update_fb_rs_state(sctx); 647} 648 649static void si_delete_rs_state(struct pipe_context *ctx, void *state) 650{ 651 struct si_context *sctx = (struct si_context *)ctx; 652 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state); 653} 654 655/* 656 * infeered state between dsa and stencil ref 657 */ 658static void si_update_dsa_stencil_ref(struct si_context *sctx) 659{ 660 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 661 struct pipe_stencil_ref *ref = &sctx->stencil_ref; 662 struct si_state_dsa *dsa = sctx->queued.named.dsa; 663 664 if (pm4 == NULL) 665 return; 666 667 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK, 668 S_028430_STENCILTESTVAL(ref->ref_value[0]) | 669 S_028430_STENCILMASK(dsa->valuemask[0]) | 670 S_028430_STENCILWRITEMASK(dsa->writemask[0]) | 671 S_028430_STENCILOPVAL(1)); 672 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF, 673 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) | 674 S_028434_STENCILMASK_BF(dsa->valuemask[1]) | 675 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) | 676 S_028434_STENCILOPVAL_BF(1)); 677 678 si_pm4_set_state(sctx, dsa_stencil_ref, pm4); 679} 680 681static void si_set_pipe_stencil_ref(struct pipe_context *ctx, 682 const struct pipe_stencil_ref *state) 683{ 684 struct si_context *sctx = (struct si_context *)ctx; 685 sctx->stencil_ref = *state; 686 si_update_dsa_stencil_ref(sctx); 687} 688 689 690/* 691 * DSA 692 */ 693 694static uint32_t si_translate_stencil_op(int s_op) 695{ 696 switch (s_op) { 697 case PIPE_STENCIL_OP_KEEP: 698 return V_02842C_STENCIL_KEEP; 699 case PIPE_STENCIL_OP_ZERO: 700 return V_02842C_STENCIL_ZERO; 701 case PIPE_STENCIL_OP_REPLACE: 702 return V_02842C_STENCIL_REPLACE_TEST; 703 case PIPE_STENCIL_OP_INCR: 704 return V_02842C_STENCIL_ADD_CLAMP; 705 case PIPE_STENCIL_OP_DECR: 706 return V_02842C_STENCIL_SUB_CLAMP; 707 case PIPE_STENCIL_OP_INCR_WRAP: 708 return V_02842C_STENCIL_ADD_WRAP; 709 case PIPE_STENCIL_OP_DECR_WRAP: 710 return V_02842C_STENCIL_SUB_WRAP; 711 case PIPE_STENCIL_OP_INVERT: 712 return V_02842C_STENCIL_INVERT; 713 default: 714 R600_ERR("Unknown stencil op %d", s_op); 715 assert(0); 716 break; 717 } 718 return 0; 719} 720 721static void *si_create_dsa_state(struct pipe_context *ctx, 722 const struct pipe_depth_stencil_alpha_state *state) 723{ 724 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa); 725 struct si_pm4_state *pm4 = &dsa->pm4; 726 unsigned db_depth_control; 727 unsigned db_render_control; 728 uint32_t db_stencil_control = 0; 729 730 if (dsa == NULL) { 731 return NULL; 732 } 733 734 dsa->valuemask[0] = state->stencil[0].valuemask; 735 dsa->valuemask[1] = state->stencil[1].valuemask; 736 dsa->writemask[0] = state->stencil[0].writemask; 737 dsa->writemask[1] = state->stencil[1].writemask; 738 739 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 740 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 741 S_028800_ZFUNC(state->depth.func); 742 743 /* stencil */ 744 if (state->stencil[0].enabled) { 745 db_depth_control |= S_028800_STENCIL_ENABLE(1); 746 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); 747 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op)); 748 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op)); 749 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op)); 750 751 if (state->stencil[1].enabled) { 752 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 753 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); 754 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op)); 755 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op)); 756 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op)); 757 } 758 } 759 760 /* alpha */ 761 if (state->alpha.enabled) { 762 dsa->alpha_func = state->alpha.func; 763 dsa->alpha_ref = state->alpha.ref_value; 764 765 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 + 766 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref)); 767 } else { 768 dsa->alpha_func = PIPE_FUNC_ALWAYS; 769 } 770 771 /* misc */ 772 db_render_control = 0; 773 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); 774 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control); 775 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); 776 777 return dsa; 778} 779 780static void si_bind_dsa_state(struct pipe_context *ctx, void *state) 781{ 782 struct si_context *sctx = (struct si_context *)ctx; 783 struct si_state_dsa *dsa = state; 784 785 if (state == NULL) 786 return; 787 788 si_pm4_bind_state(sctx, dsa, dsa); 789 si_update_dsa_stencil_ref(sctx); 790} 791 792static void si_delete_dsa_state(struct pipe_context *ctx, void *state) 793{ 794 struct si_context *sctx = (struct si_context *)ctx; 795 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state); 796} 797 798static void *si_create_db_flush_dsa(struct si_context *sctx, bool copy_depth, 799 bool copy_stencil, int sample) 800{ 801 struct pipe_depth_stencil_alpha_state dsa; 802 struct si_state_dsa *state; 803 804 memset(&dsa, 0, sizeof(dsa)); 805 806 state = sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa); 807 if (copy_depth || copy_stencil) { 808 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, 809 S_028000_DEPTH_COPY(copy_depth) | 810 S_028000_STENCIL_COPY(copy_stencil) | 811 S_028000_COPY_CENTROID(1) | 812 S_028000_COPY_SAMPLE(sample)); 813 } else { 814 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, 815 S_028000_DEPTH_COMPRESS_DISABLE(1) | 816 S_028000_STENCIL_COMPRESS_DISABLE(1)); 817 } 818 819 return state; 820} 821 822/* 823 * format translation 824 */ 825static uint32_t si_translate_colorformat(enum pipe_format format) 826{ 827 const struct util_format_description *desc = util_format_description(format); 828 829#define HAS_SIZE(x,y,z,w) \ 830 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \ 831 desc->channel[2].size == (z) && desc->channel[3].size == (w)) 832 833 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ 834 return V_028C70_COLOR_10_11_11; 835 836 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) 837 return V_028C70_COLOR_INVALID; 838 839 switch (desc->nr_channels) { 840 case 1: 841 switch (desc->channel[0].size) { 842 case 8: 843 return V_028C70_COLOR_8; 844 case 16: 845 return V_028C70_COLOR_16; 846 case 32: 847 return V_028C70_COLOR_32; 848 } 849 break; 850 case 2: 851 if (desc->channel[0].size == desc->channel[1].size) { 852 switch (desc->channel[0].size) { 853 case 8: 854 return V_028C70_COLOR_8_8; 855 case 16: 856 return V_028C70_COLOR_16_16; 857 case 32: 858 return V_028C70_COLOR_32_32; 859 } 860 } else if (HAS_SIZE(8,24,0,0)) { 861 return V_028C70_COLOR_24_8; 862 } else if (HAS_SIZE(24,8,0,0)) { 863 return V_028C70_COLOR_8_24; 864 } 865 break; 866 case 3: 867 if (HAS_SIZE(5,6,5,0)) { 868 return V_028C70_COLOR_5_6_5; 869 } else if (HAS_SIZE(32,8,24,0)) { 870 return V_028C70_COLOR_X24_8_32_FLOAT; 871 } 872 break; 873 case 4: 874 if (desc->channel[0].size == desc->channel[1].size && 875 desc->channel[0].size == desc->channel[2].size && 876 desc->channel[0].size == desc->channel[3].size) { 877 switch (desc->channel[0].size) { 878 case 4: 879 return V_028C70_COLOR_4_4_4_4; 880 case 8: 881 return V_028C70_COLOR_8_8_8_8; 882 case 16: 883 return V_028C70_COLOR_16_16_16_16; 884 case 32: 885 return V_028C70_COLOR_32_32_32_32; 886 } 887 } else if (HAS_SIZE(5,5,5,1)) { 888 return V_028C70_COLOR_1_5_5_5; 889 } else if (HAS_SIZE(10,10,10,2)) { 890 return V_028C70_COLOR_2_10_10_10; 891 } 892 break; 893 } 894 return V_028C70_COLOR_INVALID; 895} 896 897static uint32_t si_translate_colorswap(enum pipe_format format) 898{ 899 const struct util_format_description *desc = util_format_description(format); 900 901#define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz) 902 903 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ 904 return V_028C70_SWAP_STD; 905 906 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) 907 return ~0; 908 909 switch (desc->nr_channels) { 910 case 1: 911 if (HAS_SWIZZLE(0,X)) 912 return V_028C70_SWAP_STD; /* X___ */ 913 else if (HAS_SWIZZLE(3,X)) 914 return V_028C70_SWAP_ALT_REV; /* ___X */ 915 break; 916 case 2: 917 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) || 918 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) || 919 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y))) 920 return V_028C70_SWAP_STD; /* XY__ */ 921 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) || 922 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) || 923 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X))) 924 return V_028C70_SWAP_STD_REV; /* YX__ */ 925 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y)) 926 return V_028C70_SWAP_ALT; /* X__Y */ 927 break; 928 case 3: 929 if (HAS_SWIZZLE(0,X)) 930 return V_028C70_SWAP_STD; /* XYZ */ 931 else if (HAS_SWIZZLE(0,Z)) 932 return V_028C70_SWAP_STD_REV; /* ZYX */ 933 break; 934 case 4: 935 /* check the middle channels, the 1st and 4th channel can be NONE */ 936 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) 937 return V_028C70_SWAP_STD; /* XYZW */ 938 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) 939 return V_028C70_SWAP_STD_REV; /* WZYX */ 940 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) 941 return V_028C70_SWAP_ALT; /* ZYXW */ 942 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y)) 943 return V_028C70_SWAP_ALT_REV; /* WXYZ */ 944 break; 945 } 946 return ~0U; 947} 948 949static uint32_t si_colorformat_endian_swap(uint32_t colorformat) 950{ 951 if (SI_BIG_ENDIAN) { 952 switch(colorformat) { 953 /* 8-bit buffers. */ 954 case V_028C70_COLOR_8: 955 return V_028C70_ENDIAN_NONE; 956 957 /* 16-bit buffers. */ 958 case V_028C70_COLOR_5_6_5: 959 case V_028C70_COLOR_1_5_5_5: 960 case V_028C70_COLOR_4_4_4_4: 961 case V_028C70_COLOR_16: 962 case V_028C70_COLOR_8_8: 963 return V_028C70_ENDIAN_8IN16; 964 965 /* 32-bit buffers. */ 966 case V_028C70_COLOR_8_8_8_8: 967 case V_028C70_COLOR_2_10_10_10: 968 case V_028C70_COLOR_8_24: 969 case V_028C70_COLOR_24_8: 970 case V_028C70_COLOR_16_16: 971 return V_028C70_ENDIAN_8IN32; 972 973 /* 64-bit buffers. */ 974 case V_028C70_COLOR_16_16_16_16: 975 return V_028C70_ENDIAN_8IN16; 976 977 case V_028C70_COLOR_32_32: 978 return V_028C70_ENDIAN_8IN32; 979 980 /* 128-bit buffers. */ 981 case V_028C70_COLOR_32_32_32_32: 982 return V_028C70_ENDIAN_8IN32; 983 default: 984 return V_028C70_ENDIAN_NONE; /* Unsupported. */ 985 } 986 } else { 987 return V_028C70_ENDIAN_NONE; 988 } 989} 990 991/* Returns the size in bits of the widest component of a CB format */ 992static unsigned si_colorformat_max_comp_size(uint32_t colorformat) 993{ 994 switch(colorformat) { 995 case V_028C70_COLOR_4_4_4_4: 996 return 4; 997 998 case V_028C70_COLOR_1_5_5_5: 999 case V_028C70_COLOR_5_5_5_1: 1000 return 5; 1001 1002 case V_028C70_COLOR_5_6_5: 1003 return 6; 1004 1005 case V_028C70_COLOR_8: 1006 case V_028C70_COLOR_8_8: 1007 case V_028C70_COLOR_8_8_8_8: 1008 return 8; 1009 1010 case V_028C70_COLOR_10_10_10_2: 1011 case V_028C70_COLOR_2_10_10_10: 1012 return 10; 1013 1014 case V_028C70_COLOR_10_11_11: 1015 case V_028C70_COLOR_11_11_10: 1016 return 11; 1017 1018 case V_028C70_COLOR_16: 1019 case V_028C70_COLOR_16_16: 1020 case V_028C70_COLOR_16_16_16_16: 1021 return 16; 1022 1023 case V_028C70_COLOR_8_24: 1024 case V_028C70_COLOR_24_8: 1025 return 24; 1026 1027 case V_028C70_COLOR_32: 1028 case V_028C70_COLOR_32_32: 1029 case V_028C70_COLOR_32_32_32_32: 1030 case V_028C70_COLOR_X24_8_32_FLOAT: 1031 return 32; 1032 } 1033 1034 assert(!"Unknown maximum component size"); 1035 return 0; 1036} 1037 1038static uint32_t si_translate_dbformat(enum pipe_format format) 1039{ 1040 switch (format) { 1041 case PIPE_FORMAT_Z16_UNORM: 1042 return V_028040_Z_16; 1043 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1044 case PIPE_FORMAT_X8Z24_UNORM: 1045 case PIPE_FORMAT_Z24X8_UNORM: 1046 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1047 return V_028040_Z_24; /* deprecated on SI */ 1048 case PIPE_FORMAT_Z32_FLOAT: 1049 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1050 return V_028040_Z_32_FLOAT; 1051 default: 1052 return V_028040_Z_INVALID; 1053 } 1054} 1055 1056/* 1057 * Texture translation 1058 */ 1059 1060static uint32_t si_translate_texformat(struct pipe_screen *screen, 1061 enum pipe_format format, 1062 const struct util_format_description *desc, 1063 int first_non_void) 1064{ 1065 struct si_screen *rscreen = (struct si_screen*)screen; 1066 bool enable_s3tc = rscreen->b.info.drm_minor >= 31; 1067 boolean uniform = TRUE; 1068 int i; 1069 1070 /* Colorspace (return non-RGB formats directly). */ 1071 switch (desc->colorspace) { 1072 /* Depth stencil formats */ 1073 case UTIL_FORMAT_COLORSPACE_ZS: 1074 switch (format) { 1075 case PIPE_FORMAT_Z16_UNORM: 1076 return V_008F14_IMG_DATA_FORMAT_16; 1077 case PIPE_FORMAT_X24S8_UINT: 1078 case PIPE_FORMAT_Z24X8_UNORM: 1079 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1080 return V_008F14_IMG_DATA_FORMAT_8_24; 1081 case PIPE_FORMAT_X8Z24_UNORM: 1082 case PIPE_FORMAT_S8X24_UINT: 1083 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1084 return V_008F14_IMG_DATA_FORMAT_24_8; 1085 case PIPE_FORMAT_S8_UINT: 1086 return V_008F14_IMG_DATA_FORMAT_8; 1087 case PIPE_FORMAT_Z32_FLOAT: 1088 return V_008F14_IMG_DATA_FORMAT_32; 1089 case PIPE_FORMAT_X32_S8X24_UINT: 1090 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1091 return V_008F14_IMG_DATA_FORMAT_X24_8_32; 1092 default: 1093 goto out_unknown; 1094 } 1095 1096 case UTIL_FORMAT_COLORSPACE_YUV: 1097 goto out_unknown; /* TODO */ 1098 1099 case UTIL_FORMAT_COLORSPACE_SRGB: 1100 if (desc->nr_channels != 4 && desc->nr_channels != 1) 1101 goto out_unknown; 1102 break; 1103 1104 default: 1105 break; 1106 } 1107 1108 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 1109 if (!enable_s3tc) 1110 goto out_unknown; 1111 1112 switch (format) { 1113 case PIPE_FORMAT_RGTC1_SNORM: 1114 case PIPE_FORMAT_LATC1_SNORM: 1115 case PIPE_FORMAT_RGTC1_UNORM: 1116 case PIPE_FORMAT_LATC1_UNORM: 1117 return V_008F14_IMG_DATA_FORMAT_BC4; 1118 case PIPE_FORMAT_RGTC2_SNORM: 1119 case PIPE_FORMAT_LATC2_SNORM: 1120 case PIPE_FORMAT_RGTC2_UNORM: 1121 case PIPE_FORMAT_LATC2_UNORM: 1122 return V_008F14_IMG_DATA_FORMAT_BC5; 1123 default: 1124 goto out_unknown; 1125 } 1126 } 1127 1128 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 1129 1130 if (!enable_s3tc) 1131 goto out_unknown; 1132 1133 if (!util_format_s3tc_enabled) { 1134 goto out_unknown; 1135 } 1136 1137 switch (format) { 1138 case PIPE_FORMAT_DXT1_RGB: 1139 case PIPE_FORMAT_DXT1_RGBA: 1140 case PIPE_FORMAT_DXT1_SRGB: 1141 case PIPE_FORMAT_DXT1_SRGBA: 1142 return V_008F14_IMG_DATA_FORMAT_BC1; 1143 case PIPE_FORMAT_DXT3_RGBA: 1144 case PIPE_FORMAT_DXT3_SRGBA: 1145 return V_008F14_IMG_DATA_FORMAT_BC2; 1146 case PIPE_FORMAT_DXT5_RGBA: 1147 case PIPE_FORMAT_DXT5_SRGBA: 1148 return V_008F14_IMG_DATA_FORMAT_BC3; 1149 default: 1150 goto out_unknown; 1151 } 1152 } 1153 1154 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 1155 return V_008F14_IMG_DATA_FORMAT_5_9_9_9; 1156 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 1157 return V_008F14_IMG_DATA_FORMAT_10_11_11; 1158 } 1159 1160 /* R8G8Bx_SNORM - TODO CxV8U8 */ 1161 1162 /* See whether the components are of the same size. */ 1163 for (i = 1; i < desc->nr_channels; i++) { 1164 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1165 } 1166 1167 /* Non-uniform formats. */ 1168 if (!uniform) { 1169 switch(desc->nr_channels) { 1170 case 3: 1171 if (desc->channel[0].size == 5 && 1172 desc->channel[1].size == 6 && 1173 desc->channel[2].size == 5) { 1174 return V_008F14_IMG_DATA_FORMAT_5_6_5; 1175 } 1176 goto out_unknown; 1177 case 4: 1178 if (desc->channel[0].size == 5 && 1179 desc->channel[1].size == 5 && 1180 desc->channel[2].size == 5 && 1181 desc->channel[3].size == 1) { 1182 return V_008F14_IMG_DATA_FORMAT_1_5_5_5; 1183 } 1184 if (desc->channel[0].size == 10 && 1185 desc->channel[1].size == 10 && 1186 desc->channel[2].size == 10 && 1187 desc->channel[3].size == 2) { 1188 return V_008F14_IMG_DATA_FORMAT_2_10_10_10; 1189 } 1190 goto out_unknown; 1191 } 1192 goto out_unknown; 1193 } 1194 1195 if (first_non_void < 0 || first_non_void > 3) 1196 goto out_unknown; 1197 1198 /* uniform formats */ 1199 switch (desc->channel[first_non_void].size) { 1200 case 4: 1201 switch (desc->nr_channels) { 1202#if 0 /* Not supported for render targets */ 1203 case 2: 1204 return V_008F14_IMG_DATA_FORMAT_4_4; 1205#endif 1206 case 4: 1207 return V_008F14_IMG_DATA_FORMAT_4_4_4_4; 1208 } 1209 break; 1210 case 8: 1211 switch (desc->nr_channels) { 1212 case 1: 1213 return V_008F14_IMG_DATA_FORMAT_8; 1214 case 2: 1215 return V_008F14_IMG_DATA_FORMAT_8_8; 1216 case 4: 1217 return V_008F14_IMG_DATA_FORMAT_8_8_8_8; 1218 } 1219 break; 1220 case 16: 1221 switch (desc->nr_channels) { 1222 case 1: 1223 return V_008F14_IMG_DATA_FORMAT_16; 1224 case 2: 1225 return V_008F14_IMG_DATA_FORMAT_16_16; 1226 case 4: 1227 return V_008F14_IMG_DATA_FORMAT_16_16_16_16; 1228 } 1229 break; 1230 case 32: 1231 switch (desc->nr_channels) { 1232 case 1: 1233 return V_008F14_IMG_DATA_FORMAT_32; 1234 case 2: 1235 return V_008F14_IMG_DATA_FORMAT_32_32; 1236#if 0 /* Not supported for render targets */ 1237 case 3: 1238 return V_008F14_IMG_DATA_FORMAT_32_32_32; 1239#endif 1240 case 4: 1241 return V_008F14_IMG_DATA_FORMAT_32_32_32_32; 1242 } 1243 } 1244 1245out_unknown: 1246 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1247 return ~0; 1248} 1249 1250static unsigned si_tex_wrap(unsigned wrap) 1251{ 1252 switch (wrap) { 1253 default: 1254 case PIPE_TEX_WRAP_REPEAT: 1255 return V_008F30_SQ_TEX_WRAP; 1256 case PIPE_TEX_WRAP_CLAMP: 1257 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER; 1258 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 1259 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL; 1260 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 1261 return V_008F30_SQ_TEX_CLAMP_BORDER; 1262 case PIPE_TEX_WRAP_MIRROR_REPEAT: 1263 return V_008F30_SQ_TEX_MIRROR; 1264 case PIPE_TEX_WRAP_MIRROR_CLAMP: 1265 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 1266 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 1267 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 1268 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 1269 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER; 1270 } 1271} 1272 1273static unsigned si_tex_filter(unsigned filter) 1274{ 1275 switch (filter) { 1276 default: 1277 case PIPE_TEX_FILTER_NEAREST: 1278 return V_008F38_SQ_TEX_XY_FILTER_POINT; 1279 case PIPE_TEX_FILTER_LINEAR: 1280 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR; 1281 } 1282} 1283 1284static unsigned si_tex_mipfilter(unsigned filter) 1285{ 1286 switch (filter) { 1287 case PIPE_TEX_MIPFILTER_NEAREST: 1288 return V_008F38_SQ_TEX_Z_FILTER_POINT; 1289 case PIPE_TEX_MIPFILTER_LINEAR: 1290 return V_008F38_SQ_TEX_Z_FILTER_LINEAR; 1291 default: 1292 case PIPE_TEX_MIPFILTER_NONE: 1293 return V_008F38_SQ_TEX_Z_FILTER_NONE; 1294 } 1295} 1296 1297static unsigned si_tex_compare(unsigned compare) 1298{ 1299 switch (compare) { 1300 default: 1301 case PIPE_FUNC_NEVER: 1302 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER; 1303 case PIPE_FUNC_LESS: 1304 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS; 1305 case PIPE_FUNC_EQUAL: 1306 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL; 1307 case PIPE_FUNC_LEQUAL: 1308 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 1309 case PIPE_FUNC_GREATER: 1310 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER; 1311 case PIPE_FUNC_NOTEQUAL: 1312 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 1313 case PIPE_FUNC_GEQUAL: 1314 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 1315 case PIPE_FUNC_ALWAYS: 1316 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS; 1317 } 1318} 1319 1320static unsigned si_tex_dim(unsigned dim, unsigned nr_samples) 1321{ 1322 switch (dim) { 1323 default: 1324 case PIPE_TEXTURE_1D: 1325 return V_008F1C_SQ_RSRC_IMG_1D; 1326 case PIPE_TEXTURE_1D_ARRAY: 1327 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY; 1328 case PIPE_TEXTURE_2D: 1329 case PIPE_TEXTURE_RECT: 1330 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA : 1331 V_008F1C_SQ_RSRC_IMG_2D; 1332 case PIPE_TEXTURE_2D_ARRAY: 1333 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : 1334 V_008F1C_SQ_RSRC_IMG_2D_ARRAY; 1335 case PIPE_TEXTURE_3D: 1336 return V_008F1C_SQ_RSRC_IMG_3D; 1337 case PIPE_TEXTURE_CUBE: 1338 return V_008F1C_SQ_RSRC_IMG_CUBE; 1339 } 1340} 1341 1342/* 1343 * Format support testing 1344 */ 1345 1346static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 1347{ 1348 return si_translate_texformat(screen, format, util_format_description(format), 1349 util_format_get_first_non_void_channel(format)) != ~0U; 1350} 1351 1352static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen, 1353 const struct util_format_description *desc, 1354 int first_non_void) 1355{ 1356 unsigned type = desc->channel[first_non_void].type; 1357 int i; 1358 1359 if (type == UTIL_FORMAT_TYPE_FIXED) 1360 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1361 1362 if (desc->nr_channels == 4 && 1363 desc->channel[0].size == 10 && 1364 desc->channel[1].size == 10 && 1365 desc->channel[2].size == 10 && 1366 desc->channel[3].size == 2) 1367 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10; 1368 1369 /* See whether the components are of the same size. */ 1370 for (i = 0; i < desc->nr_channels; i++) { 1371 if (desc->channel[first_non_void].size != desc->channel[i].size) 1372 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1373 } 1374 1375 switch (desc->channel[first_non_void].size) { 1376 case 8: 1377 switch (desc->nr_channels) { 1378 case 1: 1379 return V_008F0C_BUF_DATA_FORMAT_8; 1380 case 2: 1381 return V_008F0C_BUF_DATA_FORMAT_8_8; 1382 case 3: 1383 case 4: 1384 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8; 1385 } 1386 break; 1387 case 16: 1388 switch (desc->nr_channels) { 1389 case 1: 1390 return V_008F0C_BUF_DATA_FORMAT_16; 1391 case 2: 1392 return V_008F0C_BUF_DATA_FORMAT_16_16; 1393 case 3: 1394 case 4: 1395 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16; 1396 } 1397 break; 1398 case 32: 1399 /* From the Southern Islands ISA documentation about MTBUF: 1400 * 'Memory reads of data in memory that is 32 or 64 bits do not 1401 * undergo any format conversion.' 1402 */ 1403 if (type != UTIL_FORMAT_TYPE_FLOAT && 1404 !desc->channel[first_non_void].pure_integer) 1405 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1406 1407 switch (desc->nr_channels) { 1408 case 1: 1409 return V_008F0C_BUF_DATA_FORMAT_32; 1410 case 2: 1411 return V_008F0C_BUF_DATA_FORMAT_32_32; 1412 case 3: 1413 return V_008F0C_BUF_DATA_FORMAT_32_32_32; 1414 case 4: 1415 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32; 1416 } 1417 break; 1418 } 1419 1420 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1421} 1422 1423static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen, 1424 const struct util_format_description *desc, 1425 int first_non_void) 1426{ 1427 switch (desc->channel[first_non_void].type) { 1428 case UTIL_FORMAT_TYPE_SIGNED: 1429 if (desc->channel[first_non_void].normalized) 1430 return V_008F0C_BUF_NUM_FORMAT_SNORM; 1431 else if (desc->channel[first_non_void].pure_integer) 1432 return V_008F0C_BUF_NUM_FORMAT_SINT; 1433 else 1434 return V_008F0C_BUF_NUM_FORMAT_SSCALED; 1435 break; 1436 case UTIL_FORMAT_TYPE_UNSIGNED: 1437 if (desc->channel[first_non_void].normalized) 1438 return V_008F0C_BUF_NUM_FORMAT_UNORM; 1439 else if (desc->channel[first_non_void].pure_integer) 1440 return V_008F0C_BUF_NUM_FORMAT_UINT; 1441 else 1442 return V_008F0C_BUF_NUM_FORMAT_USCALED; 1443 break; 1444 case UTIL_FORMAT_TYPE_FLOAT: 1445 default: 1446 return V_008F0C_BUF_NUM_FORMAT_FLOAT; 1447 } 1448} 1449 1450static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format) 1451{ 1452 const struct util_format_description *desc; 1453 int first_non_void; 1454 unsigned data_format; 1455 1456 desc = util_format_description(format); 1457 first_non_void = util_format_get_first_non_void_channel(format); 1458 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void); 1459 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID; 1460} 1461 1462static bool si_is_colorbuffer_format_supported(enum pipe_format format) 1463{ 1464 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID && 1465 si_translate_colorswap(format) != ~0U; 1466} 1467 1468static bool si_is_zs_format_supported(enum pipe_format format) 1469{ 1470 return si_translate_dbformat(format) != V_028040_Z_INVALID; 1471} 1472 1473boolean si_is_format_supported(struct pipe_screen *screen, 1474 enum pipe_format format, 1475 enum pipe_texture_target target, 1476 unsigned sample_count, 1477 unsigned usage) 1478{ 1479 struct si_screen *rscreen = (struct si_screen *)screen; 1480 unsigned retval = 0; 1481 1482 if (target >= PIPE_MAX_TEXTURE_TYPES) { 1483 R600_ERR("r600: unsupported texture type %d\n", target); 1484 return FALSE; 1485 } 1486 1487 if (!util_format_is_supported(format, usage)) 1488 return FALSE; 1489 1490 if (sample_count > 1) { 1491 if (HAVE_LLVM < 0x0304) 1492 return FALSE; 1493 1494 /* 2D tiling on CIK is supported since DRM 2.35.0 */ 1495 if (rscreen->b.chip_class >= CIK && rscreen->b.info.drm_minor < 35) 1496 return FALSE; 1497 1498 switch (sample_count) { 1499 case 2: 1500 case 4: 1501 case 8: 1502 break; 1503 default: 1504 return FALSE; 1505 } 1506 } 1507 1508 if (usage & PIPE_BIND_SAMPLER_VIEW) { 1509 if (target == PIPE_BUFFER) { 1510 if (si_is_vertex_format_supported(screen, format)) 1511 retval |= PIPE_BIND_SAMPLER_VIEW; 1512 } else { 1513 if (si_is_sampler_format_supported(screen, format)) 1514 retval |= PIPE_BIND_SAMPLER_VIEW; 1515 } 1516 } 1517 1518 if ((usage & (PIPE_BIND_RENDER_TARGET | 1519 PIPE_BIND_DISPLAY_TARGET | 1520 PIPE_BIND_SCANOUT | 1521 PIPE_BIND_SHARED)) && 1522 si_is_colorbuffer_format_supported(format)) { 1523 retval |= usage & 1524 (PIPE_BIND_RENDER_TARGET | 1525 PIPE_BIND_DISPLAY_TARGET | 1526 PIPE_BIND_SCANOUT | 1527 PIPE_BIND_SHARED); 1528 } 1529 1530 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 1531 si_is_zs_format_supported(format)) { 1532 retval |= PIPE_BIND_DEPTH_STENCIL; 1533 } 1534 1535 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 1536 si_is_vertex_format_supported(screen, format)) { 1537 retval |= PIPE_BIND_VERTEX_BUFFER; 1538 } 1539 1540 if (usage & PIPE_BIND_TRANSFER_READ) 1541 retval |= PIPE_BIND_TRANSFER_READ; 1542 if (usage & PIPE_BIND_TRANSFER_WRITE) 1543 retval |= PIPE_BIND_TRANSFER_WRITE; 1544 1545 return retval == usage; 1546} 1547 1548static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil) 1549{ 1550 unsigned tile_mode_index = 0; 1551 1552 if (stencil) { 1553 tile_mode_index = rtex->surface.stencil_tiling_index[level]; 1554 } else { 1555 tile_mode_index = rtex->surface.tiling_index[level]; 1556 } 1557 return tile_mode_index; 1558} 1559 1560/* 1561 * framebuffer handling 1562 */ 1563 1564static void si_cb(struct si_context *sctx, struct si_pm4_state *pm4, 1565 const struct pipe_framebuffer_state *state, int cb) 1566{ 1567 struct r600_texture *rtex; 1568 struct si_surface *surf; 1569 unsigned level = state->cbufs[cb]->u.tex.level; 1570 unsigned pitch, slice; 1571 unsigned color_info, color_attrib, color_pitch, color_view; 1572 unsigned tile_mode_index; 1573 unsigned format, swap, ntype, endian; 1574 uint64_t offset; 1575 const struct util_format_description *desc; 1576 int i; 1577 unsigned blend_clamp = 0, blend_bypass = 0; 1578 unsigned max_comp_size; 1579 1580 surf = (struct si_surface *)state->cbufs[cb]; 1581 rtex = (struct r600_texture*)state->cbufs[cb]->texture; 1582 1583 offset = rtex->surface.level[level].offset; 1584 1585 /* Layered rendering doesn't work with LINEAR_GENERAL. 1586 * (LINEAR_ALIGNED and others work) */ 1587 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) { 1588 assert(state->cbufs[cb]->u.tex.first_layer == state->cbufs[cb]->u.tex.last_layer); 1589 offset += rtex->surface.level[level].slice_size * 1590 state->cbufs[cb]->u.tex.first_layer; 1591 color_view = 0; 1592 } else { 1593 color_view = S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) | 1594 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer); 1595 } 1596 1597 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; 1598 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1599 if (slice) { 1600 slice = slice - 1; 1601 } 1602 1603 tile_mode_index = si_tile_mode_index(rtex, level, false); 1604 1605 desc = util_format_description(surf->base.format); 1606 for (i = 0; i < 4; i++) { 1607 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1608 break; 1609 } 1610 } 1611 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { 1612 ntype = V_028C70_NUMBER_FLOAT; 1613 } else { 1614 ntype = V_028C70_NUMBER_UNORM; 1615 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1616 ntype = V_028C70_NUMBER_SRGB; 1617 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1618 if (desc->channel[i].pure_integer) { 1619 ntype = V_028C70_NUMBER_SINT; 1620 } else { 1621 assert(desc->channel[i].normalized); 1622 ntype = V_028C70_NUMBER_SNORM; 1623 } 1624 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1625 if (desc->channel[i].pure_integer) { 1626 ntype = V_028C70_NUMBER_UINT; 1627 } else { 1628 assert(desc->channel[i].normalized); 1629 ntype = V_028C70_NUMBER_UNORM; 1630 } 1631 } 1632 } 1633 1634 format = si_translate_colorformat(surf->base.format); 1635 if (format == V_028C70_COLOR_INVALID) { 1636 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format); 1637 } 1638 assert(format != V_028C70_COLOR_INVALID); 1639 swap = si_translate_colorswap(surf->base.format); 1640 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { 1641 endian = V_028C70_ENDIAN_NONE; 1642 } else { 1643 endian = si_colorformat_endian_swap(format); 1644 } 1645 1646 /* blend clamp should be set for all NORM/SRGB types */ 1647 if (ntype == V_028C70_NUMBER_UNORM || 1648 ntype == V_028C70_NUMBER_SNORM || 1649 ntype == V_028C70_NUMBER_SRGB) 1650 blend_clamp = 1; 1651 1652 /* set blend bypass according to docs if SINT/UINT or 1653 8/24 COLOR variants */ 1654 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT || 1655 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 || 1656 format == V_028C70_COLOR_X24_8_32_FLOAT) { 1657 blend_clamp = 0; 1658 blend_bypass = 1; 1659 } 1660 1661 color_info = S_028C70_FORMAT(format) | 1662 S_028C70_COMP_SWAP(swap) | 1663 S_028C70_BLEND_CLAMP(blend_clamp) | 1664 S_028C70_BLEND_BYPASS(blend_bypass) | 1665 S_028C70_NUMBER_TYPE(ntype) | 1666 S_028C70_ENDIAN(endian); 1667 1668 color_pitch = S_028C64_TILE_MAX(pitch); 1669 1670 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) | 1671 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1); 1672 1673 if (rtex->resource.b.b.nr_samples > 1) { 1674 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples); 1675 1676 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | 1677 S_028C74_NUM_FRAGMENTS(log_samples); 1678 1679 if (rtex->fmask.size) { 1680 color_info |= S_028C70_COMPRESSION(1); 1681 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height); 1682 1683 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index); 1684 1685 if (sctx->b.chip_class == SI) { 1686 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */ 1687 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); 1688 } 1689 if (sctx->b.chip_class >= CIK) { 1690 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1); 1691 } 1692 } 1693 } 1694 1695 if (rtex->cmask.size) { 1696 color_info |= S_028C70_FAST_CLEAR(1); 1697 } 1698 1699 offset += r600_resource_va(sctx->b.b.screen, state->cbufs[cb]->texture); 1700 offset >>= 8; 1701 1702 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); 1703 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset); 1704 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, color_pitch); 1705 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice)); 1706 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, color_view); 1707 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info); 1708 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib); 1709 1710 if (rtex->cmask.size) { 1711 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C, 1712 offset + (rtex->cmask.offset >> 8)); 1713 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C, 1714 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max)); 1715 } 1716 if (rtex->fmask.size) { 1717 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C, 1718 offset + (rtex->fmask.offset >> 8)); 1719 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C, 1720 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max)); 1721 } 1722 1723 /* set CB_COLOR1_INFO for possible dual-src blending */ 1724 if (state->nr_cbufs == 1) { 1725 assert(cb == 0); 1726 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info); 1727 } 1728 1729 /* Determine pixel shader export format */ 1730 max_comp_size = si_colorformat_max_comp_size(format); 1731 if (ntype == V_028C70_NUMBER_SRGB || 1732 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) && 1733 max_comp_size <= 10) || 1734 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) { 1735 sctx->export_16bpc |= 1 << cb; 1736 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */ 1737 if (state->nr_cbufs == 1) 1738 sctx->export_16bpc |= 1 << 1; 1739 } 1740} 1741 1742static void si_db(struct si_context *sctx, struct si_pm4_state *pm4, 1743 const struct pipe_framebuffer_state *state) 1744{ 1745 struct si_screen *rscreen = sctx->screen; 1746 struct r600_texture *rtex; 1747 struct si_surface *surf; 1748 unsigned level, pitch, slice, format, tile_mode_index, array_mode; 1749 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config; 1750 uint32_t z_info, s_info, db_depth_info; 1751 uint64_t z_offs, s_offs; 1752 uint32_t db_htile_data_base, db_htile_surface; 1753 1754 if (state->zsbuf == NULL) { 1755 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID)); 1756 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID)); 1757 return; 1758 } 1759 1760 surf = (struct si_surface *)state->zsbuf; 1761 level = surf->base.u.tex.level; 1762 rtex = (struct r600_texture*)surf->base.texture; 1763 1764 format = si_translate_dbformat(rtex->resource.b.b.format); 1765 1766 if (format == V_028040_Z_INVALID) { 1767 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format); 1768 } 1769 assert(format != V_028040_Z_INVALID); 1770 1771 s_offs = z_offs = r600_resource_va(sctx->b.b.screen, surf->base.texture); 1772 z_offs += rtex->surface.level[level].offset; 1773 s_offs += rtex->surface.stencil_level[level].offset; 1774 1775 z_offs >>= 8; 1776 s_offs >>= 8; 1777 1778 pitch = (rtex->surface.level[level].nblk_x / 8) - 1; 1779 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1780 if (slice) { 1781 slice = slice - 1; 1782 } 1783 1784 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1); 1785 1786 z_info = S_028040_FORMAT(format); 1787 if (rtex->resource.b.b.nr_samples > 1) { 1788 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)); 1789 } 1790 1791 if (rtex->surface.flags & RADEON_SURF_SBUFFER) 1792 s_info = S_028044_FORMAT(V_028044_STENCIL_8); 1793 else 1794 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID); 1795 1796 if (sctx->b.chip_class >= CIK) { 1797 switch (rtex->surface.level[level].mode) { 1798 case RADEON_SURF_MODE_2D: 1799 array_mode = V_02803C_ARRAY_2D_TILED_THIN1; 1800 break; 1801 case RADEON_SURF_MODE_1D: 1802 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1803 case RADEON_SURF_MODE_LINEAR: 1804 default: 1805 array_mode = V_02803C_ARRAY_1D_TILED_THIN1; 1806 break; 1807 } 1808 tile_split = rtex->surface.tile_split; 1809 stile_split = rtex->surface.stencil_tile_split; 1810 macro_aspect = rtex->surface.mtilea; 1811 bankw = rtex->surface.bankw; 1812 bankh = rtex->surface.bankh; 1813 tile_split = cik_tile_split(tile_split); 1814 stile_split = cik_tile_split(stile_split); 1815 macro_aspect = cik_macro_tile_aspect(macro_aspect); 1816 bankw = cik_bank_wh(bankw); 1817 bankh = cik_bank_wh(bankh); 1818 nbanks = cik_num_banks(rscreen, rtex->surface.bpe, rtex->surface.tile_split); 1819 tile_mode_index = si_tile_mode_index(rtex, level, false); 1820 pipe_config = cik_db_pipe_config(rscreen, tile_mode_index); 1821 1822 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) | 1823 S_02803C_PIPE_CONFIG(pipe_config) | 1824 S_02803C_BANK_WIDTH(bankw) | 1825 S_02803C_BANK_HEIGHT(bankh) | 1826 S_02803C_MACRO_TILE_ASPECT(macro_aspect) | 1827 S_02803C_NUM_BANKS(nbanks); 1828 z_info |= S_028040_TILE_SPLIT(tile_split); 1829 s_info |= S_028044_TILE_SPLIT(stile_split); 1830 } else { 1831 tile_mode_index = si_tile_mode_index(rtex, level, false); 1832 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); 1833 tile_mode_index = si_tile_mode_index(rtex, level, true); 1834 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index); 1835 } 1836 1837 /* HiZ aka depth buffer htile */ 1838 /* use htile only for first level */ 1839 if (rtex->htile_buffer && !level) { 1840 const struct util_format_description *fmt_desc; 1841 1842 z_info |= S_028040_TILE_SURFACE_ENABLE(1); 1843 1844 /* This is optimal for the clear value of 1.0 and using 1845 * the LESS and LEQUAL test functions. Set this to 0 1846 * for the opposite case. This can only be changed when 1847 * clearing. */ 1848 z_info |= S_028040_ZRANGE_PRECISION(1); 1849 1850 fmt_desc = util_format_description(rtex->resource.b.b.format); 1851 if (!util_format_has_stencil(fmt_desc)) { 1852 /* Use all of the htile_buffer for depth */ 1853 s_info |= S_028044_TILE_STENCIL_DISABLE(1); 1854 } 1855 1856 uint64_t va = r600_resource_va(&sctx->screen->b.b, &rtex->htile_buffer->b.b); 1857 db_htile_data_base = va >> 8; 1858 db_htile_surface = S_028ABC_FULL_CACHE(1); 1859 1860 si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE); 1861 } else { 1862 db_htile_data_base = 0; 1863 db_htile_surface = 0; 1864 } 1865 1866 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, 1867 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) | 1868 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer)); 1869 si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, db_htile_data_base); 1870 1871 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info); 1872 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info); 1873 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info); 1874 1875 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); 1876 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs); 1877 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs); 1878 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs); 1879 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs); 1880 1881 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch)); 1882 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice)); 1883 1884 si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, db_htile_surface); 1885} 1886 1887#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \ 1888 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \ 1889 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \ 1890 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \ 1891 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28)) 1892 1893/* 2xMSAA 1894 * There are two locations (-4, 4), (4, -4). */ 1895static uint32_t sample_locs_2x[] = { 1896 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), 1897 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), 1898 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), 1899 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), 1900}; 1901static unsigned max_dist_2x = 4; 1902/* 4xMSAA 1903 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */ 1904static uint32_t sample_locs_4x[] = { 1905 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), 1906 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), 1907 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), 1908 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), 1909}; 1910static unsigned max_dist_4x = 6; 1911/* Cayman/SI 8xMSAA */ 1912static uint32_t cm_sample_locs_8x[] = { 1913 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), 1914 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), 1915 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), 1916 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), 1917 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), 1918 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), 1919 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), 1920 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), 1921}; 1922static unsigned cm_max_dist_8x = 8; 1923/* Cayman/SI 16xMSAA */ 1924static uint32_t cm_sample_locs_16x[] = { 1925 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5), 1926 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5), 1927 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5), 1928 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5), 1929 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1), 1930 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1), 1931 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1), 1932 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1), 1933 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6), 1934 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6), 1935 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6), 1936 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6), 1937 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0), 1938 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0), 1939 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0), 1940 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0), 1941}; 1942static unsigned cm_max_dist_16x = 8; 1943 1944static void si_get_sample_position(struct pipe_context *ctx, 1945 unsigned sample_count, 1946 unsigned sample_index, 1947 float *out_value) 1948{ 1949 int offset, index; 1950 struct { 1951 int idx:4; 1952 } val; 1953 switch (sample_count) { 1954 case 1: 1955 default: 1956 out_value[0] = out_value[1] = 0.5; 1957 break; 1958 case 2: 1959 offset = 4 * (sample_index * 2); 1960 val.idx = (sample_locs_2x[0] >> offset) & 0xf; 1961 out_value[0] = (float)(val.idx + 8) / 16.0f; 1962 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf; 1963 out_value[1] = (float)(val.idx + 8) / 16.0f; 1964 break; 1965 case 4: 1966 offset = 4 * (sample_index * 2); 1967 val.idx = (sample_locs_4x[0] >> offset) & 0xf; 1968 out_value[0] = (float)(val.idx + 8) / 16.0f; 1969 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf; 1970 out_value[1] = (float)(val.idx + 8) / 16.0f; 1971 break; 1972 case 8: 1973 offset = 4 * (sample_index % 4 * 2); 1974 index = (sample_index / 4) * 4; 1975 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf; 1976 out_value[0] = (float)(val.idx + 8) / 16.0f; 1977 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf; 1978 out_value[1] = (float)(val.idx + 8) / 16.0f; 1979 break; 1980 case 16: 1981 offset = 4 * (sample_index % 4 * 2); 1982 index = (sample_index / 4) * 4; 1983 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf; 1984 out_value[0] = (float)(val.idx + 8) / 16.0f; 1985 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf; 1986 out_value[1] = (float)(val.idx + 8) / 16.0f; 1987 break; 1988 } 1989} 1990 1991static void si_set_msaa_state(struct si_context *sctx, struct si_pm4_state *pm4, int nr_samples) 1992{ 1993 unsigned max_dist = 0; 1994 1995 switch (nr_samples) { 1996 default: 1997 nr_samples = 0; 1998 break; 1999 case 2: 2000 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]); 2001 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]); 2002 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]); 2003 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]); 2004 max_dist = max_dist_2x; 2005 break; 2006 case 4: 2007 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]); 2008 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]); 2009 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]); 2010 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]); 2011 max_dist = max_dist_4x; 2012 break; 2013 case 8: 2014 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]); 2015 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]); 2016 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0); 2017 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0); 2018 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]); 2019 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]); 2020 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0); 2021 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0); 2022 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]); 2023 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]); 2024 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0); 2025 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0); 2026 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]); 2027 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]); 2028 max_dist = cm_max_dist_8x; 2029 break; 2030 case 16: 2031 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]); 2032 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]); 2033 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]); 2034 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]); 2035 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]); 2036 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]); 2037 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]); 2038 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]); 2039 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]); 2040 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]); 2041 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]); 2042 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]); 2043 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]); 2044 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]); 2045 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]); 2046 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]); 2047 max_dist = cm_max_dist_16x; 2048 break; 2049 } 2050 2051 if (nr_samples > 1) { 2052 unsigned log_samples = util_logbase2(nr_samples); 2053 2054 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 2055 S_028BDC_LAST_PIXEL(1) | 2056 S_028BDC_EXPAND_LINE_WIDTH(1)); 2057 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 2058 S_028BE0_MSAA_NUM_SAMPLES(log_samples) | 2059 S_028BE0_MAX_SAMPLE_DIST(max_dist) | 2060 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); 2061 2062 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 2063 S_028804_MAX_ANCHOR_SAMPLES(log_samples) | 2064 S_028804_PS_ITER_SAMPLES(log_samples) | 2065 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) | 2066 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) | 2067 S_028804_HIGH_QUALITY_INTERSECTIONS(1) | 2068 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1)); 2069 } else { 2070 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1)); 2071 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0); 2072 2073 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 2074 S_028804_HIGH_QUALITY_INTERSECTIONS(1) | 2075 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1)); 2076 } 2077} 2078 2079static void si_set_framebuffer_state(struct pipe_context *ctx, 2080 const struct pipe_framebuffer_state *state) 2081{ 2082 struct si_context *sctx = (struct si_context *)ctx; 2083 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 2084 uint32_t tl, br; 2085 int tl_x, tl_y, br_x, br_y, nr_samples, i; 2086 2087 if (pm4 == NULL) 2088 return; 2089 2090 if (sctx->framebuffer.nr_cbufs) { 2091 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB | 2092 R600_CONTEXT_FLUSH_AND_INV_CB_META; 2093 } 2094 if (sctx->framebuffer.zsbuf) { 2095 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB | 2096 R600_CONTEXT_FLUSH_AND_INV_DB_META; 2097 } 2098 2099 util_copy_framebuffer_state(&sctx->framebuffer, state); 2100 2101 /* build states */ 2102 sctx->export_16bpc = 0; 2103 sctx->fb_compressed_cb_mask = 0; 2104 for (i = 0; i < state->nr_cbufs; i++) { 2105 struct r600_texture *rtex; 2106 2107 if (!state->cbufs[i]) { 2108 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C, 2109 S_028C70_FORMAT(V_028C70_COLOR_INVALID)); 2110 continue; 2111 } 2112 2113 rtex = (struct r600_texture*)state->cbufs[i]->texture; 2114 2115 si_cb(sctx, pm4, state, i); 2116 2117 if (rtex->fmask.size || rtex->cmask.size) { 2118 sctx->fb_compressed_cb_mask |= 1 << i; 2119 } 2120 } 2121 for (; i < 8; i++) { 2122 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C, 2123 S_028C70_FORMAT(V_028C70_COLOR_INVALID)); 2124 } 2125 2126 assert(!(sctx->export_16bpc & ~0xff)); 2127 si_db(sctx, pm4, state); 2128 2129 tl_x = 0; 2130 tl_y = 0; 2131 br_x = state->width; 2132 br_y = state->height; 2133 2134 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y); 2135 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y); 2136 2137 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl); 2138 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br); 2139 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl); 2140 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br); 2141 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl); 2142 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br); 2143 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl); 2144 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br); 2145 2146 nr_samples = util_framebuffer_get_num_samples(state); 2147 2148 si_set_msaa_state(sctx, pm4, nr_samples); 2149 sctx->fb_log_samples = util_logbase2(nr_samples); 2150 sctx->fb_cb0_is_integer = state->nr_cbufs && state->cbufs[0] && 2151 util_format_is_pure_integer(state->cbufs[0]->format); 2152 2153 si_pm4_set_state(sctx, framebuffer, pm4); 2154 si_update_fb_rs_state(sctx); 2155 si_update_fb_blend_state(sctx); 2156} 2157 2158/* 2159 * shaders 2160 */ 2161 2162/* Compute the key for the hw shader variant */ 2163static INLINE void si_shader_selector_key(struct pipe_context *ctx, 2164 struct si_pipe_shader_selector *sel, 2165 union si_shader_key *key) 2166{ 2167 struct si_context *sctx = (struct si_context *)ctx; 2168 memset(key, 0, sizeof(*key)); 2169 2170 if (sel->type == PIPE_SHADER_VERTEX) { 2171 unsigned i; 2172 if (!sctx->vertex_elements) 2173 return; 2174 2175 for (i = 0; i < sctx->vertex_elements->count; ++i) 2176 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor; 2177 2178 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0) 2179 key->vs.ucps_enabled |= 0x2; 2180 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf) 2181 key->vs.ucps_enabled |= 0x1; 2182 } else if (sel->type == PIPE_SHADER_FRAGMENT) { 2183 if (sel->fs_write_all) 2184 key->ps.nr_cbufs = sctx->framebuffer.nr_cbufs; 2185 key->ps.export_16bpc = sctx->export_16bpc; 2186 2187 if (sctx->queued.named.rasterizer) { 2188 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side; 2189 key->ps.flatshade = sctx->queued.named.rasterizer->flatshade; 2190 2191 if (sctx->queued.named.blend) { 2192 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one && 2193 sctx->queued.named.rasterizer->multisample_enable && 2194 !sctx->fb_cb0_is_integer; 2195 } 2196 } 2197 if (sctx->queued.named.dsa) { 2198 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func; 2199 2200 /* Alpha-test should be disabled if colorbuffer 0 is integer. */ 2201 if (sctx->framebuffer.nr_cbufs && 2202 sctx->framebuffer.cbufs[0] && 2203 util_format_is_pure_integer(sctx->framebuffer.cbufs[0]->texture->format)) 2204 key->ps.alpha_func = PIPE_FUNC_ALWAYS; 2205 } else { 2206 key->ps.alpha_func = PIPE_FUNC_ALWAYS; 2207 } 2208 } 2209} 2210 2211/* Select the hw shader variant depending on the current state. 2212 * (*dirty) is set to 1 if current variant was changed */ 2213int si_shader_select(struct pipe_context *ctx, 2214 struct si_pipe_shader_selector *sel, 2215 unsigned *dirty) 2216{ 2217 union si_shader_key key; 2218 struct si_pipe_shader * shader = NULL; 2219 int r; 2220 2221 si_shader_selector_key(ctx, sel, &key); 2222 2223 /* Check if we don't need to change anything. 2224 * This path is also used for most shaders that don't need multiple 2225 * variants, it will cost just a computation of the key and this 2226 * test. */ 2227 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) { 2228 return 0; 2229 } 2230 2231 /* lookup if we have other variants in the list */ 2232 if (sel->num_shaders > 1) { 2233 struct si_pipe_shader *p = sel->current, *c = p->next_variant; 2234 2235 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) { 2236 p = c; 2237 c = c->next_variant; 2238 } 2239 2240 if (c) { 2241 p->next_variant = c->next_variant; 2242 shader = c; 2243 } 2244 } 2245 2246 if (unlikely(!shader)) { 2247 shader = CALLOC(1, sizeof(struct si_pipe_shader)); 2248 shader->selector = sel; 2249 shader->key = key; 2250 2251 r = si_pipe_shader_create(ctx, shader); 2252 if (unlikely(r)) { 2253 R600_ERR("Failed to build shader variant (type=%u) %d\n", 2254 sel->type, r); 2255 sel->current = NULL; 2256 FREE(shader); 2257 return r; 2258 } 2259 sel->num_shaders++; 2260 } 2261 2262 if (dirty) 2263 *dirty = 1; 2264 2265 shader->next_variant = sel->current; 2266 sel->current = shader; 2267 2268 return 0; 2269} 2270 2271static void *si_create_shader_state(struct pipe_context *ctx, 2272 const struct pipe_shader_state *state, 2273 unsigned pipe_shader_type) 2274{ 2275 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector); 2276 int r; 2277 2278 sel->type = pipe_shader_type; 2279 sel->tokens = tgsi_dup_tokens(state->tokens); 2280 sel->so = state->stream_output; 2281 2282 if (pipe_shader_type == PIPE_SHADER_FRAGMENT) { 2283 struct tgsi_shader_info info; 2284 2285 tgsi_scan_shader(state->tokens, &info); 2286 sel->fs_write_all = info.color0_writes_all_cbufs; 2287 } 2288 2289 r = si_shader_select(ctx, sel, NULL); 2290 if (r) { 2291 free(sel); 2292 return NULL; 2293 } 2294 2295 return sel; 2296} 2297 2298static void *si_create_fs_state(struct pipe_context *ctx, 2299 const struct pipe_shader_state *state) 2300{ 2301 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT); 2302} 2303 2304static void *si_create_vs_state(struct pipe_context *ctx, 2305 const struct pipe_shader_state *state) 2306{ 2307 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX); 2308} 2309 2310static void si_bind_vs_shader(struct pipe_context *ctx, void *state) 2311{ 2312 struct si_context *sctx = (struct si_context *)ctx; 2313 struct si_pipe_shader_selector *sel = state; 2314 2315 if (sctx->vs_shader == sel) 2316 return; 2317 2318 if (!sel || !sel->current) 2319 return; 2320 2321 sctx->vs_shader = sel; 2322 si_pm4_bind_state(sctx, vs, sel->current->pm4); 2323 sctx->b.streamout.stride_in_dw = sel->so.stride; 2324 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE; 2325} 2326 2327static void si_bind_ps_shader(struct pipe_context *ctx, void *state) 2328{ 2329 struct si_context *sctx = (struct si_context *)ctx; 2330 struct si_pipe_shader_selector *sel = state; 2331 2332 if (sctx->ps_shader == sel) 2333 return; 2334 2335 if (!sel || !sel->current) 2336 sel = sctx->dummy_pixel_shader; 2337 2338 sctx->ps_shader = sel; 2339 si_pm4_bind_state(sctx, ps, sel->current->pm4); 2340 sctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE; 2341} 2342 2343static void si_delete_shader_selector(struct pipe_context *ctx, 2344 struct si_pipe_shader_selector *sel) 2345{ 2346 struct si_context *sctx = (struct si_context *)ctx; 2347 struct si_pipe_shader *p = sel->current, *c; 2348 2349 while (p) { 2350 c = p->next_variant; 2351 si_pm4_delete_state(sctx, vs, p->pm4); 2352 si_pipe_shader_destroy(ctx, p); 2353 free(p); 2354 p = c; 2355 } 2356 2357 free(sel->tokens); 2358 free(sel); 2359 } 2360 2361static void si_delete_vs_shader(struct pipe_context *ctx, void *state) 2362{ 2363 struct si_context *sctx = (struct si_context *)ctx; 2364 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; 2365 2366 if (sctx->vs_shader == sel) { 2367 sctx->vs_shader = NULL; 2368 } 2369 2370 si_delete_shader_selector(ctx, sel); 2371} 2372 2373static void si_delete_ps_shader(struct pipe_context *ctx, void *state) 2374{ 2375 struct si_context *sctx = (struct si_context *)ctx; 2376 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; 2377 2378 if (sctx->ps_shader == sel) { 2379 sctx->ps_shader = NULL; 2380 } 2381 2382 si_delete_shader_selector(ctx, sel); 2383} 2384 2385/* 2386 * Samplers 2387 */ 2388 2389static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx, 2390 struct pipe_resource *texture, 2391 const struct pipe_sampler_view *state) 2392{ 2393 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view); 2394 struct r600_texture *tmp = (struct r600_texture*)texture; 2395 const struct util_format_description *desc; 2396 unsigned format, num_format; 2397 uint32_t pitch = 0; 2398 unsigned char state_swizzle[4], swizzle[4]; 2399 unsigned height, depth, width; 2400 enum pipe_format pipe_format = state->format; 2401 struct radeon_surface_level *surflevel; 2402 int first_non_void; 2403 uint64_t va; 2404 2405 if (view == NULL) 2406 return NULL; 2407 2408 /* initialize base object */ 2409 view->base = *state; 2410 view->base.texture = NULL; 2411 pipe_resource_reference(&view->base.texture, texture); 2412 view->base.reference.count = 1; 2413 view->base.context = ctx; 2414 view->resource = &tmp->resource; 2415 2416 /* Buffer resource. */ 2417 if (texture->target == PIPE_BUFFER) { 2418 unsigned stride; 2419 2420 desc = util_format_description(state->format); 2421 first_non_void = util_format_get_first_non_void_channel(state->format); 2422 stride = desc->block.bits / 8; 2423 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride; 2424 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void); 2425 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void); 2426 2427 view->state[0] = va; 2428 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | 2429 S_008F04_STRIDE(stride); 2430 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element; 2431 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | 2432 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | 2433 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | 2434 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | 2435 S_008F0C_NUM_FORMAT(num_format) | 2436 S_008F0C_DATA_FORMAT(format); 2437 return &view->base; 2438 } 2439 2440 state_swizzle[0] = state->swizzle_r; 2441 state_swizzle[1] = state->swizzle_g; 2442 state_swizzle[2] = state->swizzle_b; 2443 state_swizzle[3] = state->swizzle_a; 2444 2445 surflevel = tmp->surface.level; 2446 2447 /* Texturing with separate depth and stencil. */ 2448 if (tmp->is_depth && !tmp->is_flushing_texture) { 2449 switch (pipe_format) { 2450 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 2451 pipe_format = PIPE_FORMAT_Z32_FLOAT; 2452 break; 2453 case PIPE_FORMAT_X8Z24_UNORM: 2454 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2455 /* Z24 is always stored like this. */ 2456 pipe_format = PIPE_FORMAT_Z24X8_UNORM; 2457 break; 2458 case PIPE_FORMAT_X24S8_UINT: 2459 case PIPE_FORMAT_S8X24_UINT: 2460 case PIPE_FORMAT_X32_S8X24_UINT: 2461 pipe_format = PIPE_FORMAT_S8_UINT; 2462 surflevel = tmp->surface.stencil_level; 2463 break; 2464 default:; 2465 } 2466 } 2467 2468 desc = util_format_description(pipe_format); 2469 2470 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) { 2471 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0}; 2472 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1}; 2473 2474 switch (pipe_format) { 2475 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2476 case PIPE_FORMAT_X24S8_UINT: 2477 case PIPE_FORMAT_X32_S8X24_UINT: 2478 case PIPE_FORMAT_X8Z24_UNORM: 2479 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle); 2480 break; 2481 default: 2482 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle); 2483 } 2484 } else { 2485 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle); 2486 } 2487 2488 first_non_void = util_format_get_first_non_void_channel(pipe_format); 2489 2490 switch (pipe_format) { 2491 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2492 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2493 break; 2494 default: 2495 if (first_non_void < 0) { 2496 if (util_format_is_compressed(pipe_format)) { 2497 switch (pipe_format) { 2498 case PIPE_FORMAT_DXT1_SRGB: 2499 case PIPE_FORMAT_DXT1_SRGBA: 2500 case PIPE_FORMAT_DXT3_SRGBA: 2501 case PIPE_FORMAT_DXT5_SRGBA: 2502 num_format = V_008F14_IMG_NUM_FORMAT_SRGB; 2503 break; 2504 case PIPE_FORMAT_RGTC1_SNORM: 2505 case PIPE_FORMAT_LATC1_SNORM: 2506 case PIPE_FORMAT_RGTC2_SNORM: 2507 case PIPE_FORMAT_LATC2_SNORM: 2508 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 2509 break; 2510 default: 2511 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2512 break; 2513 } 2514 } else { 2515 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2516 } 2517 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) { 2518 num_format = V_008F14_IMG_NUM_FORMAT_SRGB; 2519 } else { 2520 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2521 2522 switch (desc->channel[first_non_void].type) { 2523 case UTIL_FORMAT_TYPE_FLOAT: 2524 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2525 break; 2526 case UTIL_FORMAT_TYPE_SIGNED: 2527 if (desc->channel[first_non_void].normalized) 2528 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 2529 else if (desc->channel[first_non_void].pure_integer) 2530 num_format = V_008F14_IMG_NUM_FORMAT_SINT; 2531 else 2532 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED; 2533 break; 2534 case UTIL_FORMAT_TYPE_UNSIGNED: 2535 if (desc->channel[first_non_void].normalized) 2536 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2537 else if (desc->channel[first_non_void].pure_integer) 2538 num_format = V_008F14_IMG_NUM_FORMAT_UINT; 2539 else 2540 num_format = V_008F14_IMG_NUM_FORMAT_USCALED; 2541 } 2542 } 2543 } 2544 2545 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void); 2546 if (format == ~0) { 2547 format = 0; 2548 } 2549 2550 /* not supported any more */ 2551 //endian = si_colorformat_endian_swap(format); 2552 2553 width = surflevel[0].npix_x; 2554 height = surflevel[0].npix_y; 2555 depth = surflevel[0].npix_z; 2556 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format); 2557 2558 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 2559 height = 1; 2560 depth = texture->array_size; 2561 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 2562 depth = texture->array_size; 2563 } 2564 2565 va = r600_resource_va(ctx->screen, texture); 2566 va += surflevel[0].offset; 2567 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size; 2568 view->state[0] = va >> 8; 2569 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) | 2570 S_008F14_DATA_FORMAT(format) | 2571 S_008F14_NUM_FORMAT(num_format)); 2572 view->state[2] = (S_008F18_WIDTH(width - 1) | 2573 S_008F18_HEIGHT(height - 1)); 2574 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) | 2575 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | 2576 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | 2577 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | 2578 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ? 2579 0 : state->u.tex.first_level - tmp->mipmap_shift) | 2580 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ? 2581 util_logbase2(texture->nr_samples) : 2582 state->u.tex.last_level - tmp->mipmap_shift) | 2583 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) | 2584 S_008F1C_POW2_PAD(texture->last_level > 0) | 2585 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples))); 2586 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1)); 2587 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) | 2588 S_008F24_LAST_ARRAY(state->u.tex.last_layer)); 2589 view->state[6] = 0; 2590 view->state[7] = 0; 2591 2592 /* Initialize the sampler view for FMASK. */ 2593 if (tmp->fmask.size) { 2594 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset; 2595 uint32_t fmask_format; 2596 2597 switch (texture->nr_samples) { 2598 case 2: 2599 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2; 2600 break; 2601 case 4: 2602 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4; 2603 break; 2604 case 8: 2605 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8; 2606 break; 2607 default: 2608 assert(0); 2609 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID; 2610 } 2611 2612 view->fmask_state[0] = va >> 8; 2613 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) | 2614 S_008F14_DATA_FORMAT(fmask_format) | 2615 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT); 2616 view->fmask_state[2] = S_008F18_WIDTH(width - 1) | 2617 S_008F18_HEIGHT(height - 1); 2618 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) | 2619 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) | 2620 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | 2621 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) | 2622 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) | 2623 S_008F1C_TYPE(si_tex_dim(texture->target, 0)); 2624 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) | 2625 S_008F20_PITCH(tmp->fmask.pitch - 1); 2626 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) | 2627 S_008F24_LAST_ARRAY(state->u.tex.last_layer); 2628 view->fmask_state[6] = 0; 2629 view->fmask_state[7] = 0; 2630 } 2631 2632 return &view->base; 2633} 2634 2635static void si_sampler_view_destroy(struct pipe_context *ctx, 2636 struct pipe_sampler_view *state) 2637{ 2638 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; 2639 2640 pipe_resource_reference(&state->texture, NULL); 2641 FREE(resource); 2642} 2643 2644static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter) 2645{ 2646 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER || 2647 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER || 2648 (linear_filter && 2649 (wrap == PIPE_TEX_WRAP_CLAMP || 2650 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP)); 2651} 2652 2653static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state) 2654{ 2655 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST || 2656 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST; 2657 2658 return (state->border_color.ui[0] || state->border_color.ui[1] || 2659 state->border_color.ui[2] || state->border_color.ui[3]) && 2660 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) || 2661 wrap_mode_uses_border_color(state->wrap_t, linear_filter) || 2662 wrap_mode_uses_border_color(state->wrap_r, linear_filter)); 2663} 2664 2665static void *si_create_sampler_state(struct pipe_context *ctx, 2666 const struct pipe_sampler_state *state) 2667{ 2668 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state); 2669 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; 2670 unsigned border_color_type; 2671 2672 if (rstate == NULL) { 2673 return NULL; 2674 } 2675 2676 if (sampler_state_needs_border_color(state)) 2677 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER; 2678 else 2679 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; 2680 2681 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | 2682 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) | 2683 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) | 2684 (state->max_anisotropy & 0x7) << 9 | /* XXX */ 2685 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) | 2686 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) | 2687 aniso_flag_offset << 16 | /* XXX */ 2688 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map)); 2689 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | 2690 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8))); 2691 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) | 2692 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) | 2693 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) | 2694 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter))); 2695 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type); 2696 2697 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) { 2698 memcpy(rstate->border_color, state->border_color.ui, 2699 sizeof(rstate->border_color)); 2700 } 2701 2702 return rstate; 2703} 2704 2705/* XXX consider moving this function to si_descriptors.c for gcc to inline 2706 * the si_set_sampler_view calls. LTO might help too. */ 2707static void si_set_sampler_views(struct pipe_context *ctx, 2708 unsigned shader, unsigned start, 2709 unsigned count, 2710 struct pipe_sampler_view **views) 2711{ 2712 struct si_context *sctx = (struct si_context *)ctx; 2713 struct si_textures_info *samplers = &sctx->samplers[shader]; 2714 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views; 2715 int i; 2716 2717 if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT) 2718 return; 2719 2720 assert(start == 0); 2721 2722 for (i = 0; i < count; i++) { 2723 if (!views[i]) { 2724 samplers->depth_texture_mask &= ~(1 << i); 2725 samplers->compressed_colortex_mask &= ~(1 << i); 2726 si_set_sampler_view(sctx, shader, i, NULL, NULL); 2727 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i, 2728 NULL, NULL); 2729 continue; 2730 } 2731 2732 si_set_sampler_view(sctx, shader, i, views[i], rviews[i]->state); 2733 2734 if (views[i]->texture->target != PIPE_BUFFER) { 2735 struct r600_texture *rtex = 2736 (struct r600_texture*)views[i]->texture; 2737 2738 if (rtex->is_depth && !rtex->is_flushing_texture) { 2739 samplers->depth_texture_mask |= 1 << i; 2740 } else { 2741 samplers->depth_texture_mask &= ~(1 << i); 2742 } 2743 if (rtex->cmask.size || rtex->fmask.size) { 2744 samplers->compressed_colortex_mask |= 1 << i; 2745 } else { 2746 samplers->compressed_colortex_mask &= ~(1 << i); 2747 } 2748 2749 if (rtex->fmask.size) { 2750 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i, 2751 views[i], rviews[i]->fmask_state); 2752 } else { 2753 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i, 2754 NULL, NULL); 2755 } 2756 } 2757 } 2758 for (; i < samplers->n_views; i++) { 2759 samplers->depth_texture_mask &= ~(1 << i); 2760 samplers->compressed_colortex_mask &= ~(1 << i); 2761 si_set_sampler_view(sctx, shader, i, NULL, NULL); 2762 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i, 2763 NULL, NULL); 2764 } 2765 2766 samplers->n_views = count; 2767 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE; 2768} 2769 2770static struct si_pm4_state *si_set_sampler_states(struct si_context *sctx, unsigned count, 2771 void **states, 2772 struct si_textures_info *samplers, 2773 unsigned user_data_reg) 2774{ 2775 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states; 2776 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 2777 uint32_t *border_color_table = NULL; 2778 int i, j; 2779 2780 if (!count) 2781 goto out; 2782 2783 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE; 2784 2785 si_pm4_sh_data_begin(pm4); 2786 for (i = 0; i < count; i++) { 2787 if (rstates[i] && 2788 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) == 2789 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) { 2790 if (!sctx->border_color_table || 2791 ((sctx->border_color_offset + count - i) & 2792 C_008F3C_BORDER_COLOR_PTR)) { 2793 r600_resource_reference(&sctx->border_color_table, NULL); 2794 sctx->border_color_offset = 0; 2795 2796 sctx->border_color_table = 2797 si_resource_create_custom(&sctx->screen->b.b, 2798 PIPE_USAGE_STAGING, 2799 4096 * 4 * 4); 2800 } 2801 2802 if (!border_color_table) { 2803 border_color_table = 2804 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf, 2805 sctx->b.rings.gfx.cs, 2806 PIPE_TRANSFER_WRITE | 2807 PIPE_TRANSFER_UNSYNCHRONIZED); 2808 } 2809 2810 for (j = 0; j < 4; j++) { 2811 border_color_table[4 * sctx->border_color_offset + j] = 2812 util_le32_to_cpu(rstates[i]->border_color[j]); 2813 } 2814 2815 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR; 2816 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++); 2817 } 2818 2819 for (j = 0; j < Elements(rstates[i]->val); ++j) { 2820 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0); 2821 } 2822 } 2823 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER); 2824 2825 if (border_color_table) { 2826 uint64_t va_offset = 2827 r600_resource_va(&sctx->screen->b.b, 2828 (void*)sctx->border_color_table); 2829 2830 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8); 2831 if (sctx->b.chip_class >= CIK) 2832 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40); 2833 sctx->b.ws->buffer_unmap(sctx->border_color_table->cs_buf); 2834 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ); 2835 } 2836 2837 memcpy(samplers->samplers, states, sizeof(void*) * count); 2838 2839out: 2840 samplers->n_samplers = count; 2841 return pm4; 2842} 2843 2844static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states) 2845{ 2846 struct si_context *sctx = (struct si_context *)ctx; 2847 struct si_pm4_state *pm4; 2848 2849 pm4 = si_set_sampler_states(sctx, count, states, &sctx->samplers[PIPE_SHADER_VERTEX], 2850 R_00B130_SPI_SHADER_USER_DATA_VS_0); 2851 si_pm4_set_state(sctx, vs_sampler, pm4); 2852} 2853 2854static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states) 2855{ 2856 struct si_context *sctx = (struct si_context *)ctx; 2857 struct si_pm4_state *pm4; 2858 2859 pm4 = si_set_sampler_states(sctx, count, states, &sctx->samplers[PIPE_SHADER_FRAGMENT], 2860 R_00B030_SPI_SHADER_USER_DATA_PS_0); 2861 si_pm4_set_state(sctx, ps_sampler, pm4); 2862} 2863 2864 2865static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader, 2866 unsigned start, unsigned count, 2867 void **states) 2868{ 2869 assert(start == 0); 2870 2871 switch (shader) { 2872 case PIPE_SHADER_VERTEX: 2873 si_bind_vs_sampler_states(ctx, count, states); 2874 break; 2875 case PIPE_SHADER_FRAGMENT: 2876 si_bind_ps_sampler_states(ctx, count, states); 2877 break; 2878 default: 2879 ; 2880 } 2881} 2882 2883 2884 2885static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask) 2886{ 2887 struct si_context *sctx = (struct si_context *)ctx; 2888 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 2889 uint16_t mask = sample_mask; 2890 2891 if (pm4 == NULL) 2892 return; 2893 2894 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16)); 2895 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16)); 2896 2897 si_pm4_set_state(sctx, sample_mask, pm4); 2898} 2899 2900static void si_delete_sampler_state(struct pipe_context *ctx, void *state) 2901{ 2902 free(state); 2903} 2904 2905/* 2906 * Vertex elements & buffers 2907 */ 2908 2909static void *si_create_vertex_elements(struct pipe_context *ctx, 2910 unsigned count, 2911 const struct pipe_vertex_element *elements) 2912{ 2913 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element); 2914 int i; 2915 2916 assert(count < PIPE_MAX_ATTRIBS); 2917 if (!v) 2918 return NULL; 2919 2920 v->count = count; 2921 for (i = 0; i < count; ++i) { 2922 const struct util_format_description *desc; 2923 unsigned data_format, num_format; 2924 int first_non_void; 2925 2926 desc = util_format_description(elements[i].src_format); 2927 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format); 2928 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void); 2929 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void); 2930 2931 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | 2932 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | 2933 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | 2934 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | 2935 S_008F0C_NUM_FORMAT(num_format) | 2936 S_008F0C_DATA_FORMAT(data_format); 2937 } 2938 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); 2939 2940 return v; 2941} 2942 2943static void si_bind_vertex_elements(struct pipe_context *ctx, void *state) 2944{ 2945 struct si_context *sctx = (struct si_context *)ctx; 2946 struct si_vertex_element *v = (struct si_vertex_element*)state; 2947 2948 sctx->vertex_elements = v; 2949} 2950 2951static void si_delete_vertex_element(struct pipe_context *ctx, void *state) 2952{ 2953 struct si_context *sctx = (struct si_context *)ctx; 2954 2955 if (sctx->vertex_elements == state) 2956 sctx->vertex_elements = NULL; 2957 FREE(state); 2958} 2959 2960static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count, 2961 const struct pipe_vertex_buffer *buffers) 2962{ 2963 struct si_context *sctx = (struct si_context *)ctx; 2964 2965 util_set_vertex_buffers_count(sctx->vertex_buffer, &sctx->nr_vertex_buffers, buffers, start_slot, count); 2966} 2967 2968static void si_set_index_buffer(struct pipe_context *ctx, 2969 const struct pipe_index_buffer *ib) 2970{ 2971 struct si_context *sctx = (struct si_context *)ctx; 2972 2973 if (ib) { 2974 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer); 2975 memcpy(&sctx->index_buffer, ib, sizeof(*ib)); 2976 } else { 2977 pipe_resource_reference(&sctx->index_buffer.buffer, NULL); 2978 } 2979} 2980 2981/* 2982 * Misc 2983 */ 2984static void si_set_polygon_stipple(struct pipe_context *ctx, 2985 const struct pipe_poly_stipple *state) 2986{ 2987} 2988 2989static void si_texture_barrier(struct pipe_context *ctx) 2990{ 2991 struct si_context *sctx = (struct si_context *)ctx; 2992 2993 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE | 2994 R600_CONTEXT_FLUSH_AND_INV_CB; 2995} 2996 2997static void *si_create_blend_custom(struct si_context *sctx, unsigned mode) 2998{ 2999 struct pipe_blend_state blend; 3000 3001 memset(&blend, 0, sizeof(blend)); 3002 blend.independent_blend_enable = true; 3003 blend.rt[0].colormask = 0xf; 3004 return si_create_blend_state_mode(&sctx->b.b, &blend, mode); 3005} 3006 3007static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, 3008 struct pipe_resource *texture, 3009 const struct pipe_surface *surf_tmpl) 3010{ 3011 struct r600_texture *rtex = (struct r600_texture*)texture; 3012 struct si_surface *surface = CALLOC_STRUCT(si_surface); 3013 unsigned level = surf_tmpl->u.tex.level; 3014 3015 if (surface == NULL) 3016 return NULL; 3017 3018 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level)); 3019 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level)); 3020 3021 pipe_reference_init(&surface->base.reference, 1); 3022 pipe_resource_reference(&surface->base.texture, texture); 3023 surface->base.context = pipe; 3024 surface->base.format = surf_tmpl->format; 3025 surface->base.width = rtex->surface.level[level].npix_x; 3026 surface->base.height = rtex->surface.level[level].npix_y; 3027 surface->base.texture = texture; 3028 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; 3029 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; 3030 surface->base.u.tex.level = level; 3031 3032 return &surface->base; 3033} 3034 3035static void r600_surface_destroy(struct pipe_context *pipe, 3036 struct pipe_surface *surface) 3037{ 3038 pipe_resource_reference(&surface->texture, NULL); 3039 FREE(surface); 3040} 3041 3042static boolean si_dma_copy(struct pipe_context *ctx, 3043 struct pipe_resource *dst, 3044 unsigned dst_level, 3045 unsigned dst_x, unsigned dst_y, unsigned dst_z, 3046 struct pipe_resource *src, 3047 unsigned src_level, 3048 const struct pipe_box *src_box) 3049{ 3050 /* XXX implement this or share evergreen_dma_blit with r600g */ 3051 return FALSE; 3052} 3053 3054void si_init_state_functions(struct si_context *sctx) 3055{ 3056 int i; 3057 3058 sctx->b.b.create_blend_state = si_create_blend_state; 3059 sctx->b.b.bind_blend_state = si_bind_blend_state; 3060 sctx->b.b.delete_blend_state = si_delete_blend_state; 3061 sctx->b.b.set_blend_color = si_set_blend_color; 3062 3063 sctx->b.b.create_rasterizer_state = si_create_rs_state; 3064 sctx->b.b.bind_rasterizer_state = si_bind_rs_state; 3065 sctx->b.b.delete_rasterizer_state = si_delete_rs_state; 3066 3067 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state; 3068 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state; 3069 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state; 3070 3071 for (i = 0; i < 8; i++) { 3072 sctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(sctx, true, true, i); 3073 sctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(sctx, true, false, i); 3074 sctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(sctx, false, true, i); 3075 } 3076 sctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(sctx, false, false, 0); 3077 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE); 3078 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS); 3079 3080 sctx->b.b.set_clip_state = si_set_clip_state; 3081 sctx->b.b.set_scissor_states = si_set_scissor_states; 3082 sctx->b.b.set_viewport_states = si_set_viewport_states; 3083 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref; 3084 3085 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state; 3086 sctx->b.b.get_sample_position = si_get_sample_position; 3087 3088 sctx->b.b.create_vs_state = si_create_vs_state; 3089 sctx->b.b.create_fs_state = si_create_fs_state; 3090 sctx->b.b.bind_vs_state = si_bind_vs_shader; 3091 sctx->b.b.bind_fs_state = si_bind_ps_shader; 3092 sctx->b.b.delete_vs_state = si_delete_vs_shader; 3093 sctx->b.b.delete_fs_state = si_delete_ps_shader; 3094 3095 sctx->b.b.create_sampler_state = si_create_sampler_state; 3096 sctx->b.b.bind_sampler_states = si_bind_sampler_states; 3097 sctx->b.b.delete_sampler_state = si_delete_sampler_state; 3098 3099 sctx->b.b.create_sampler_view = si_create_sampler_view; 3100 sctx->b.b.set_sampler_views = si_set_sampler_views; 3101 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy; 3102 3103 sctx->b.b.set_sample_mask = si_set_sample_mask; 3104 3105 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements; 3106 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements; 3107 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element; 3108 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers; 3109 sctx->b.b.set_index_buffer = si_set_index_buffer; 3110 3111 sctx->b.b.texture_barrier = si_texture_barrier; 3112 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple; 3113 sctx->b.b.create_surface = r600_create_surface; 3114 sctx->b.b.surface_destroy = r600_surface_destroy; 3115 sctx->b.dma_copy = si_dma_copy; 3116 3117 sctx->b.b.draw_vbo = si_draw_vbo; 3118} 3119 3120void si_init_config(struct si_context *sctx) 3121{ 3122 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 3123 3124 if (pm4 == NULL) 3125 return; 3126 3127 si_cmd_context_control(pm4); 3128 3129 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0); 3130 3131 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0); 3132 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0); 3133 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0); 3134 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0); 3135 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0); 3136 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0); 3137 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0); 3138 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0); 3139 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0); 3140 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0); 3141 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0); 3142 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0); 3143 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0); 3144 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0); 3145 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); 3146 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); 3147 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0); 3148 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); 3149 if (sctx->b.chip_class == SI) { 3150 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, 3151 S_028AA8_SWITCH_ON_EOP(1) | 3152 S_028AA8_PARTIAL_VS_WAVE_ON(1) | 3153 S_028AA8_PRIMGROUP_SIZE(63)); 3154 } 3155 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000); 3156 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); 3157 if (sctx->b.chip_class < CIK) 3158 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | 3159 S_008A14_CLIP_VTX_REORDER_ENA(1)); 3160 3161 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0); 3162 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210); 3163 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98); 3164 3165 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0); 3166 3167 if (sctx->b.chip_class >= CIK) { 3168 switch (sctx->screen->b.family) { 3169 case CHIP_BONAIRE: 3170 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012); 3171 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000); 3172 break; 3173 case CHIP_HAWAII: 3174 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a); 3175 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e); 3176 break; 3177 case CHIP_KAVERI: 3178 /* XXX todo */ 3179 case CHIP_KABINI: 3180 /* XXX todo */ 3181 default: 3182 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); 3183 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000); 3184 break; 3185 } 3186 } else { 3187 switch (sctx->screen->b.family) { 3188 case CHIP_TAHITI: 3189 case CHIP_PITCAIRN: 3190 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a); 3191 break; 3192 case CHIP_VERDE: 3193 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a); 3194 break; 3195 case CHIP_OLAND: 3196 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082); 3197 break; 3198 case CHIP_HAINAN: 3199 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); 3200 break; 3201 default: 3202 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); 3203 break; 3204 } 3205 } 3206 3207 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000); 3208 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 3209 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000); 3210 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000); 3211 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F); 3212 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000); 3213 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000); 3214 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000); 3215 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000); 3216 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000); 3217 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000); 3218 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000); 3219 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000); 3220 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000); 3221 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); 3222 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); 3223 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); 3224 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 3225 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 3226 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE)); 3227 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); 3228 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); 3229 3230 if (sctx->b.chip_class >= CIK) { 3231 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff)); 3232 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0)); 3233 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff)); 3234 } 3235 3236 si_pm4_set_state(sctx, init, pm4); 3237} 3238