si_state.c revision a38e1fd78ba406abe6c6dfd665804ec0d8f98172
1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Christian König <christian.koenig@amd.com> 25 */ 26 27#include "si_pipe.h" 28#include "si_shader.h" 29#include "sid.h" 30#include "../radeon/r600_cs.h" 31 32#include "tgsi/tgsi_parse.h" 33#include "tgsi/tgsi_scan.h" 34#include "util/u_format.h" 35#include "util/u_format_s3tc.h" 36#include "util/u_framebuffer.h" 37#include "util/u_helpers.h" 38#include "util/u_memory.h" 39 40static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem, 41 void (*emit)(struct si_context *ctx, struct r600_atom *state), 42 unsigned num_dw) 43{ 44 atom->emit = (void*)emit; 45 atom->num_dw = num_dw; 46 atom->dirty = false; 47 *list_elem = atom; 48} 49 50static uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned tile_split) 51{ 52 if (sscreen->b.info.cik_macrotile_mode_array_valid) { 53 unsigned index, tileb; 54 55 tileb = 8 * 8 * bpe; 56 tileb = MIN2(tile_split, tileb); 57 58 for (index = 0; tileb > 64; index++) { 59 tileb >>= 1; 60 } 61 62 assert(index < 16); 63 64 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3; 65 } 66 67 /* The old way. */ 68 switch (sscreen->b.tiling_info.num_banks) { 69 case 2: 70 return V_02803C_ADDR_SURF_2_BANK; 71 case 4: 72 return V_02803C_ADDR_SURF_4_BANK; 73 case 8: 74 default: 75 return V_02803C_ADDR_SURF_8_BANK; 76 case 16: 77 return V_02803C_ADDR_SURF_16_BANK; 78 } 79} 80 81static unsigned cik_tile_split(unsigned tile_split) 82{ 83 switch (tile_split) { 84 case 64: 85 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B; 86 break; 87 case 128: 88 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B; 89 break; 90 case 256: 91 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B; 92 break; 93 case 512: 94 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B; 95 break; 96 default: 97 case 1024: 98 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB; 99 break; 100 case 2048: 101 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB; 102 break; 103 case 4096: 104 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB; 105 break; 106 } 107 return tile_split; 108} 109 110static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect) 111{ 112 switch (macro_tile_aspect) { 113 default: 114 case 1: 115 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1; 116 break; 117 case 2: 118 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2; 119 break; 120 case 4: 121 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4; 122 break; 123 case 8: 124 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8; 125 break; 126 } 127 return macro_tile_aspect; 128} 129 130static unsigned cik_bank_wh(unsigned bankwh) 131{ 132 switch (bankwh) { 133 default: 134 case 1: 135 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1; 136 break; 137 case 2: 138 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2; 139 break; 140 case 4: 141 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4; 142 break; 143 case 8: 144 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8; 145 break; 146 } 147 return bankwh; 148} 149 150static unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode) 151{ 152 if (sscreen->b.info.si_tile_mode_array_valid) { 153 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode]; 154 155 return G_009910_PIPE_CONFIG(gb_tile_mode); 156 } 157 158 /* This is probably broken for a lot of chips, but it's only used 159 * if the kernel cannot return the tile mode array for CIK. */ 160 switch (sscreen->b.info.r600_num_tile_pipes) { 161 case 16: 162 return V_02803C_X_ADDR_SURF_P16_32X32_16X16; 163 case 8: 164 return V_02803C_X_ADDR_SURF_P8_32X32_16X16; 165 case 4: 166 default: 167 if (sscreen->b.info.r600_num_backends == 4) 168 return V_02803C_X_ADDR_SURF_P4_16X16; 169 else 170 return V_02803C_X_ADDR_SURF_P4_8X16; 171 case 2: 172 return V_02803C_ADDR_SURF_P2; 173 } 174} 175 176static unsigned si_map_swizzle(unsigned swizzle) 177{ 178 switch (swizzle) { 179 case UTIL_FORMAT_SWIZZLE_Y: 180 return V_008F0C_SQ_SEL_Y; 181 case UTIL_FORMAT_SWIZZLE_Z: 182 return V_008F0C_SQ_SEL_Z; 183 case UTIL_FORMAT_SWIZZLE_W: 184 return V_008F0C_SQ_SEL_W; 185 case UTIL_FORMAT_SWIZZLE_0: 186 return V_008F0C_SQ_SEL_0; 187 case UTIL_FORMAT_SWIZZLE_1: 188 return V_008F0C_SQ_SEL_1; 189 default: /* UTIL_FORMAT_SWIZZLE_X */ 190 return V_008F0C_SQ_SEL_X; 191 } 192} 193 194static uint32_t S_FIXED(float value, uint32_t frac_bits) 195{ 196 return value * (1 << frac_bits); 197} 198 199/* 12.4 fixed-point */ 200static unsigned si_pack_float_12p4(float x) 201{ 202 return x <= 0 ? 0 : 203 x >= 4096 ? 0xffff : x * 16; 204} 205 206/* 207 * inferred framebuffer and blender state 208 */ 209static void si_update_fb_blend_state(struct si_context *sctx) 210{ 211 struct si_pm4_state *pm4; 212 struct si_state_blend *blend = sctx->queued.named.blend; 213 uint32_t mask; 214 215 if (blend == NULL) 216 return; 217 218 pm4 = si_pm4_alloc_state(sctx); 219 if (pm4 == NULL) 220 return; 221 222 mask = (1ULL << ((unsigned)sctx->framebuffer.state.nr_cbufs * 4)) - 1; 223 mask &= blend->cb_target_mask; 224 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask); 225 226 si_pm4_set_state(sctx, fb_blend, pm4); 227} 228 229/* 230 * Blender functions 231 */ 232 233static uint32_t si_translate_blend_function(int blend_func) 234{ 235 switch (blend_func) { 236 case PIPE_BLEND_ADD: 237 return V_028780_COMB_DST_PLUS_SRC; 238 case PIPE_BLEND_SUBTRACT: 239 return V_028780_COMB_SRC_MINUS_DST; 240 case PIPE_BLEND_REVERSE_SUBTRACT: 241 return V_028780_COMB_DST_MINUS_SRC; 242 case PIPE_BLEND_MIN: 243 return V_028780_COMB_MIN_DST_SRC; 244 case PIPE_BLEND_MAX: 245 return V_028780_COMB_MAX_DST_SRC; 246 default: 247 R600_ERR("Unknown blend function %d\n", blend_func); 248 assert(0); 249 break; 250 } 251 return 0; 252} 253 254static uint32_t si_translate_blend_factor(int blend_fact) 255{ 256 switch (blend_fact) { 257 case PIPE_BLENDFACTOR_ONE: 258 return V_028780_BLEND_ONE; 259 case PIPE_BLENDFACTOR_SRC_COLOR: 260 return V_028780_BLEND_SRC_COLOR; 261 case PIPE_BLENDFACTOR_SRC_ALPHA: 262 return V_028780_BLEND_SRC_ALPHA; 263 case PIPE_BLENDFACTOR_DST_ALPHA: 264 return V_028780_BLEND_DST_ALPHA; 265 case PIPE_BLENDFACTOR_DST_COLOR: 266 return V_028780_BLEND_DST_COLOR; 267 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 268 return V_028780_BLEND_SRC_ALPHA_SATURATE; 269 case PIPE_BLENDFACTOR_CONST_COLOR: 270 return V_028780_BLEND_CONSTANT_COLOR; 271 case PIPE_BLENDFACTOR_CONST_ALPHA: 272 return V_028780_BLEND_CONSTANT_ALPHA; 273 case PIPE_BLENDFACTOR_ZERO: 274 return V_028780_BLEND_ZERO; 275 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 276 return V_028780_BLEND_ONE_MINUS_SRC_COLOR; 277 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 278 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; 279 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 280 return V_028780_BLEND_ONE_MINUS_DST_ALPHA; 281 case PIPE_BLENDFACTOR_INV_DST_COLOR: 282 return V_028780_BLEND_ONE_MINUS_DST_COLOR; 283 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 284 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; 285 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 286 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; 287 case PIPE_BLENDFACTOR_SRC1_COLOR: 288 return V_028780_BLEND_SRC1_COLOR; 289 case PIPE_BLENDFACTOR_SRC1_ALPHA: 290 return V_028780_BLEND_SRC1_ALPHA; 291 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 292 return V_028780_BLEND_INV_SRC1_COLOR; 293 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 294 return V_028780_BLEND_INV_SRC1_ALPHA; 295 default: 296 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 297 assert(0); 298 break; 299 } 300 return 0; 301} 302 303static void *si_create_blend_state_mode(struct pipe_context *ctx, 304 const struct pipe_blend_state *state, 305 unsigned mode) 306{ 307 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend); 308 struct si_pm4_state *pm4 = &blend->pm4; 309 310 uint32_t color_control = 0; 311 312 if (blend == NULL) 313 return NULL; 314 315 blend->alpha_to_one = state->alpha_to_one; 316 317 if (state->logicop_enable) { 318 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4)); 319 } else { 320 color_control |= S_028808_ROP3(0xcc); 321 } 322 323 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 324 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) | 325 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | 326 S_028B70_ALPHA_TO_MASK_OFFSET1(2) | 327 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | 328 S_028B70_ALPHA_TO_MASK_OFFSET3(2)); 329 330 blend->cb_target_mask = 0; 331 for (int i = 0; i < 8; i++) { 332 /* state->rt entries > 0 only written if independent blending */ 333 const int j = state->independent_blend_enable ? i : 0; 334 335 unsigned eqRGB = state->rt[j].rgb_func; 336 unsigned srcRGB = state->rt[j].rgb_src_factor; 337 unsigned dstRGB = state->rt[j].rgb_dst_factor; 338 unsigned eqA = state->rt[j].alpha_func; 339 unsigned srcA = state->rt[j].alpha_src_factor; 340 unsigned dstA = state->rt[j].alpha_dst_factor; 341 342 unsigned blend_cntl = 0; 343 344 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 345 blend->cb_target_mask |= state->rt[j].colormask << (4 * i); 346 347 if (!state->rt[j].blend_enable) { 348 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 349 continue; 350 } 351 352 blend_cntl |= S_028780_ENABLE(1); 353 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); 354 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); 355 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); 356 357 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 358 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); 359 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); 360 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); 361 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); 362 } 363 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 364 } 365 366 if (blend->cb_target_mask) { 367 color_control |= S_028808_MODE(mode); 368 } else { 369 color_control |= S_028808_MODE(V_028808_CB_DISABLE); 370 } 371 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); 372 373 return blend; 374} 375 376static void *si_create_blend_state(struct pipe_context *ctx, 377 const struct pipe_blend_state *state) 378{ 379 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL); 380} 381 382static void si_bind_blend_state(struct pipe_context *ctx, void *state) 383{ 384 struct si_context *sctx = (struct si_context *)ctx; 385 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state); 386 si_update_fb_blend_state(sctx); 387} 388 389static void si_delete_blend_state(struct pipe_context *ctx, void *state) 390{ 391 struct si_context *sctx = (struct si_context *)ctx; 392 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state); 393} 394 395static void si_set_blend_color(struct pipe_context *ctx, 396 const struct pipe_blend_color *state) 397{ 398 struct si_context *sctx = (struct si_context *)ctx; 399 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 400 401 if (pm4 == NULL) 402 return; 403 404 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0])); 405 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1])); 406 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2])); 407 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3])); 408 409 si_pm4_set_state(sctx, blend_color, pm4); 410} 411 412/* 413 * Clipping, scissors and viewport 414 */ 415 416static void si_set_clip_state(struct pipe_context *ctx, 417 const struct pipe_clip_state *state) 418{ 419 struct si_context *sctx = (struct si_context *)ctx; 420 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 421 struct pipe_constant_buffer cb; 422 423 if (pm4 == NULL) 424 return; 425 426 for (int i = 0; i < 6; i++) { 427 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16, 428 fui(state->ucp[i][0])); 429 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16, 430 fui(state->ucp[i][1])); 431 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16, 432 fui(state->ucp[i][2])); 433 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16, 434 fui(state->ucp[i][3])); 435 } 436 437 cb.buffer = NULL; 438 cb.user_buffer = state->ucp; 439 cb.buffer_offset = 0; 440 cb.buffer_size = 4*4*8; 441 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb); 442 pipe_resource_reference(&cb.buffer, NULL); 443 444 si_pm4_set_state(sctx, clip, pm4); 445} 446 447static void si_set_scissor_states(struct pipe_context *ctx, 448 unsigned start_slot, 449 unsigned num_scissors, 450 const struct pipe_scissor_state *state) 451{ 452 struct si_context *sctx = (struct si_context *)ctx; 453 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 454 455 if (pm4 == NULL) 456 return; 457 458 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 459 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) | 460 S_028250_WINDOW_OFFSET_DISABLE(1)); 461 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, 462 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy)); 463 464 si_pm4_set_state(sctx, scissor, pm4); 465} 466 467static void si_set_viewport_states(struct pipe_context *ctx, 468 unsigned start_slot, 469 unsigned num_viewports, 470 const struct pipe_viewport_state *state) 471{ 472 struct si_context *sctx = (struct si_context *)ctx; 473 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport); 474 struct si_pm4_state *pm4 = &viewport->pm4; 475 476 if (viewport == NULL) 477 return; 478 479 viewport->viewport = *state; 480 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0])); 481 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0])); 482 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1])); 483 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1])); 484 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2])); 485 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2])); 486 487 si_pm4_set_state(sctx, viewport, viewport); 488} 489 490/* 491 * inferred state between framebuffer and rasterizer 492 */ 493static void si_update_fb_rs_state(struct si_context *sctx) 494{ 495 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 496 struct si_pm4_state *pm4; 497 float offset_units; 498 499 if (!rs || !sctx->framebuffer.state.zsbuf) 500 return; 501 502 offset_units = sctx->queued.named.rasterizer->offset_units; 503 switch (sctx->framebuffer.state.zsbuf->texture->format) { 504 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 505 case PIPE_FORMAT_X8Z24_UNORM: 506 case PIPE_FORMAT_Z24X8_UNORM: 507 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 508 offset_units *= 2.0f; 509 break; 510 case PIPE_FORMAT_Z32_FLOAT: 511 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 512 offset_units *= 1.0f; 513 break; 514 case PIPE_FORMAT_Z16_UNORM: 515 offset_units *= 4.0f; 516 break; 517 default: 518 return; 519 } 520 521 pm4 = si_pm4_alloc_state(sctx); 522 523 if (pm4 == NULL) 524 return; 525 526 /* FIXME some of those reg can be computed with cso */ 527 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 528 fui(sctx->queued.named.rasterizer->offset_scale)); 529 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units)); 530 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 531 fui(sctx->queued.named.rasterizer->offset_scale)); 532 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units)); 533 534 si_pm4_set_state(sctx, fb_rs, pm4); 535} 536 537/* 538 * Rasterizer 539 */ 540 541static uint32_t si_translate_fill(uint32_t func) 542{ 543 switch(func) { 544 case PIPE_POLYGON_MODE_FILL: 545 return V_028814_X_DRAW_TRIANGLES; 546 case PIPE_POLYGON_MODE_LINE: 547 return V_028814_X_DRAW_LINES; 548 case PIPE_POLYGON_MODE_POINT: 549 return V_028814_X_DRAW_POINTS; 550 default: 551 assert(0); 552 return V_028814_X_DRAW_POINTS; 553 } 554} 555 556static void *si_create_rs_state(struct pipe_context *ctx, 557 const struct pipe_rasterizer_state *state) 558{ 559 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer); 560 struct si_pm4_state *pm4 = &rs->pm4; 561 unsigned tmp; 562 unsigned prov_vtx = 1, polygon_dual_mode; 563 float psize_min, psize_max; 564 565 if (rs == NULL) { 566 return NULL; 567 } 568 569 rs->two_side = state->light_twoside; 570 rs->multisample_enable = state->multisample; 571 rs->clip_plane_enable = state->clip_plane_enable; 572 rs->line_stipple_enable = state->line_stipple_enable; 573 574 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 575 state->fill_back != PIPE_POLYGON_MODE_FILL); 576 577 if (state->flatshade_first) 578 prov_vtx = 0; 579 580 rs->flatshade = state->flatshade; 581 rs->sprite_coord_enable = state->sprite_coord_enable; 582 rs->pa_sc_line_stipple = state->line_stipple_enable ? 583 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 584 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 585 rs->pa_su_sc_mode_cntl = 586 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 587 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 588 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 589 S_028814_FACE(!state->front_ccw) | 590 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 591 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 592 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 593 S_028814_POLY_MODE(polygon_dual_mode) | 594 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | 595 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)); 596 rs->pa_cl_clip_cntl = 597 S_028810_PS_UCP_MODE(3) | 598 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 599 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 600 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) | 601 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 602 603 /* offset */ 604 rs->offset_units = state->offset_units; 605 rs->offset_scale = state->offset_scale * 12.0f; 606 607 tmp = S_0286D4_FLAT_SHADE_ENA(1); 608 if (state->sprite_coord_enable) { 609 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 610 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | 611 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | 612 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | 613 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1); 614 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 615 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 616 } 617 } 618 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp); 619 620 /* point size 12.4 fixed point */ 621 tmp = (unsigned)(state->point_size * 8.0); 622 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 623 624 if (state->point_size_per_vertex) { 625 psize_min = util_get_min_point_size(state); 626 psize_max = 8192; 627 } else { 628 /* Force the point size to be as if the vertex output was disabled. */ 629 psize_min = state->point_size; 630 psize_max = state->point_size; 631 } 632 /* Divide by two, because 0.5 = 1 pixel. */ 633 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX, 634 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) | 635 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2))); 636 637 tmp = (unsigned)state->line_width * 8; 638 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); 639 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0, 640 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) | 641 S_028A48_MSAA_ENABLE(state->multisample) | 642 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor)); 643 644 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL, 645 S_028BE4_PIX_CENTER(state->half_pixel_center) | 646 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH)); 647 648 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 649 650 return rs; 651} 652 653static void si_bind_rs_state(struct pipe_context *ctx, void *state) 654{ 655 struct si_context *sctx = (struct si_context *)ctx; 656 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state; 657 658 if (state == NULL) 659 return; 660 661 // TODO 662 sctx->sprite_coord_enable = rs->sprite_coord_enable; 663 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; 664 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl; 665 666 si_pm4_bind_state(sctx, rasterizer, rs); 667 si_update_fb_rs_state(sctx); 668} 669 670static void si_delete_rs_state(struct pipe_context *ctx, void *state) 671{ 672 struct si_context *sctx = (struct si_context *)ctx; 673 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state); 674} 675 676/* 677 * infeered state between dsa and stencil ref 678 */ 679static void si_update_dsa_stencil_ref(struct si_context *sctx) 680{ 681 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 682 struct pipe_stencil_ref *ref = &sctx->stencil_ref; 683 struct si_state_dsa *dsa = sctx->queued.named.dsa; 684 685 if (pm4 == NULL) 686 return; 687 688 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK, 689 S_028430_STENCILTESTVAL(ref->ref_value[0]) | 690 S_028430_STENCILMASK(dsa->valuemask[0]) | 691 S_028430_STENCILWRITEMASK(dsa->writemask[0]) | 692 S_028430_STENCILOPVAL(1)); 693 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF, 694 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) | 695 S_028434_STENCILMASK_BF(dsa->valuemask[1]) | 696 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) | 697 S_028434_STENCILOPVAL_BF(1)); 698 699 si_pm4_set_state(sctx, dsa_stencil_ref, pm4); 700} 701 702static void si_set_pipe_stencil_ref(struct pipe_context *ctx, 703 const struct pipe_stencil_ref *state) 704{ 705 struct si_context *sctx = (struct si_context *)ctx; 706 sctx->stencil_ref = *state; 707 si_update_dsa_stencil_ref(sctx); 708} 709 710 711/* 712 * DSA 713 */ 714 715static uint32_t si_translate_stencil_op(int s_op) 716{ 717 switch (s_op) { 718 case PIPE_STENCIL_OP_KEEP: 719 return V_02842C_STENCIL_KEEP; 720 case PIPE_STENCIL_OP_ZERO: 721 return V_02842C_STENCIL_ZERO; 722 case PIPE_STENCIL_OP_REPLACE: 723 return V_02842C_STENCIL_REPLACE_TEST; 724 case PIPE_STENCIL_OP_INCR: 725 return V_02842C_STENCIL_ADD_CLAMP; 726 case PIPE_STENCIL_OP_DECR: 727 return V_02842C_STENCIL_SUB_CLAMP; 728 case PIPE_STENCIL_OP_INCR_WRAP: 729 return V_02842C_STENCIL_ADD_WRAP; 730 case PIPE_STENCIL_OP_DECR_WRAP: 731 return V_02842C_STENCIL_SUB_WRAP; 732 case PIPE_STENCIL_OP_INVERT: 733 return V_02842C_STENCIL_INVERT; 734 default: 735 R600_ERR("Unknown stencil op %d", s_op); 736 assert(0); 737 break; 738 } 739 return 0; 740} 741 742static void *si_create_dsa_state(struct pipe_context *ctx, 743 const struct pipe_depth_stencil_alpha_state *state) 744{ 745 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa); 746 struct si_pm4_state *pm4 = &dsa->pm4; 747 unsigned db_depth_control; 748 unsigned db_render_control; 749 uint32_t db_stencil_control = 0; 750 751 if (dsa == NULL) { 752 return NULL; 753 } 754 755 dsa->valuemask[0] = state->stencil[0].valuemask; 756 dsa->valuemask[1] = state->stencil[1].valuemask; 757 dsa->writemask[0] = state->stencil[0].writemask; 758 dsa->writemask[1] = state->stencil[1].writemask; 759 760 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 761 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 762 S_028800_ZFUNC(state->depth.func); 763 764 /* stencil */ 765 if (state->stencil[0].enabled) { 766 db_depth_control |= S_028800_STENCIL_ENABLE(1); 767 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); 768 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op)); 769 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op)); 770 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op)); 771 772 if (state->stencil[1].enabled) { 773 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 774 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); 775 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op)); 776 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op)); 777 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op)); 778 } 779 } 780 781 /* alpha */ 782 if (state->alpha.enabled) { 783 dsa->alpha_func = state->alpha.func; 784 dsa->alpha_ref = state->alpha.ref_value; 785 786 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 + 787 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref)); 788 } else { 789 dsa->alpha_func = PIPE_FUNC_ALWAYS; 790 } 791 792 /* misc */ 793 db_render_control = 0; 794 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); 795 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control); 796 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); 797 798 return dsa; 799} 800 801static void si_bind_dsa_state(struct pipe_context *ctx, void *state) 802{ 803 struct si_context *sctx = (struct si_context *)ctx; 804 struct si_state_dsa *dsa = state; 805 806 if (state == NULL) 807 return; 808 809 si_pm4_bind_state(sctx, dsa, dsa); 810 si_update_dsa_stencil_ref(sctx); 811} 812 813static void si_delete_dsa_state(struct pipe_context *ctx, void *state) 814{ 815 struct si_context *sctx = (struct si_context *)ctx; 816 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state); 817} 818 819static void *si_create_db_flush_dsa(struct si_context *sctx, bool copy_depth, 820 bool copy_stencil, int sample) 821{ 822 struct pipe_depth_stencil_alpha_state dsa; 823 struct si_state_dsa *state; 824 825 memset(&dsa, 0, sizeof(dsa)); 826 827 state = sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa); 828 if (copy_depth || copy_stencil) { 829 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, 830 S_028000_DEPTH_COPY(copy_depth) | 831 S_028000_STENCIL_COPY(copy_stencil) | 832 S_028000_COPY_CENTROID(1) | 833 S_028000_COPY_SAMPLE(sample)); 834 } else { 835 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, 836 S_028000_DEPTH_COMPRESS_DISABLE(1) | 837 S_028000_STENCIL_COMPRESS_DISABLE(1)); 838 } 839 840 return state; 841} 842 843/* 844 * format translation 845 */ 846static uint32_t si_translate_colorformat(enum pipe_format format) 847{ 848 const struct util_format_description *desc = util_format_description(format); 849 850#define HAS_SIZE(x,y,z,w) \ 851 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \ 852 desc->channel[2].size == (z) && desc->channel[3].size == (w)) 853 854 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ 855 return V_028C70_COLOR_10_11_11; 856 857 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) 858 return V_028C70_COLOR_INVALID; 859 860 switch (desc->nr_channels) { 861 case 1: 862 switch (desc->channel[0].size) { 863 case 8: 864 return V_028C70_COLOR_8; 865 case 16: 866 return V_028C70_COLOR_16; 867 case 32: 868 return V_028C70_COLOR_32; 869 } 870 break; 871 case 2: 872 if (desc->channel[0].size == desc->channel[1].size) { 873 switch (desc->channel[0].size) { 874 case 8: 875 return V_028C70_COLOR_8_8; 876 case 16: 877 return V_028C70_COLOR_16_16; 878 case 32: 879 return V_028C70_COLOR_32_32; 880 } 881 } else if (HAS_SIZE(8,24,0,0)) { 882 return V_028C70_COLOR_24_8; 883 } else if (HAS_SIZE(24,8,0,0)) { 884 return V_028C70_COLOR_8_24; 885 } 886 break; 887 case 3: 888 if (HAS_SIZE(5,6,5,0)) { 889 return V_028C70_COLOR_5_6_5; 890 } else if (HAS_SIZE(32,8,24,0)) { 891 return V_028C70_COLOR_X24_8_32_FLOAT; 892 } 893 break; 894 case 4: 895 if (desc->channel[0].size == desc->channel[1].size && 896 desc->channel[0].size == desc->channel[2].size && 897 desc->channel[0].size == desc->channel[3].size) { 898 switch (desc->channel[0].size) { 899 case 4: 900 return V_028C70_COLOR_4_4_4_4; 901 case 8: 902 return V_028C70_COLOR_8_8_8_8; 903 case 16: 904 return V_028C70_COLOR_16_16_16_16; 905 case 32: 906 return V_028C70_COLOR_32_32_32_32; 907 } 908 } else if (HAS_SIZE(5,5,5,1)) { 909 return V_028C70_COLOR_1_5_5_5; 910 } else if (HAS_SIZE(10,10,10,2)) { 911 return V_028C70_COLOR_2_10_10_10; 912 } 913 break; 914 } 915 return V_028C70_COLOR_INVALID; 916} 917 918static uint32_t si_colorformat_endian_swap(uint32_t colorformat) 919{ 920 if (SI_BIG_ENDIAN) { 921 switch(colorformat) { 922 /* 8-bit buffers. */ 923 case V_028C70_COLOR_8: 924 return V_028C70_ENDIAN_NONE; 925 926 /* 16-bit buffers. */ 927 case V_028C70_COLOR_5_6_5: 928 case V_028C70_COLOR_1_5_5_5: 929 case V_028C70_COLOR_4_4_4_4: 930 case V_028C70_COLOR_16: 931 case V_028C70_COLOR_8_8: 932 return V_028C70_ENDIAN_8IN16; 933 934 /* 32-bit buffers. */ 935 case V_028C70_COLOR_8_8_8_8: 936 case V_028C70_COLOR_2_10_10_10: 937 case V_028C70_COLOR_8_24: 938 case V_028C70_COLOR_24_8: 939 case V_028C70_COLOR_16_16: 940 return V_028C70_ENDIAN_8IN32; 941 942 /* 64-bit buffers. */ 943 case V_028C70_COLOR_16_16_16_16: 944 return V_028C70_ENDIAN_8IN16; 945 946 case V_028C70_COLOR_32_32: 947 return V_028C70_ENDIAN_8IN32; 948 949 /* 128-bit buffers. */ 950 case V_028C70_COLOR_32_32_32_32: 951 return V_028C70_ENDIAN_8IN32; 952 default: 953 return V_028C70_ENDIAN_NONE; /* Unsupported. */ 954 } 955 } else { 956 return V_028C70_ENDIAN_NONE; 957 } 958} 959 960/* Returns the size in bits of the widest component of a CB format */ 961static unsigned si_colorformat_max_comp_size(uint32_t colorformat) 962{ 963 switch(colorformat) { 964 case V_028C70_COLOR_4_4_4_4: 965 return 4; 966 967 case V_028C70_COLOR_1_5_5_5: 968 case V_028C70_COLOR_5_5_5_1: 969 return 5; 970 971 case V_028C70_COLOR_5_6_5: 972 return 6; 973 974 case V_028C70_COLOR_8: 975 case V_028C70_COLOR_8_8: 976 case V_028C70_COLOR_8_8_8_8: 977 return 8; 978 979 case V_028C70_COLOR_10_10_10_2: 980 case V_028C70_COLOR_2_10_10_10: 981 return 10; 982 983 case V_028C70_COLOR_10_11_11: 984 case V_028C70_COLOR_11_11_10: 985 return 11; 986 987 case V_028C70_COLOR_16: 988 case V_028C70_COLOR_16_16: 989 case V_028C70_COLOR_16_16_16_16: 990 return 16; 991 992 case V_028C70_COLOR_8_24: 993 case V_028C70_COLOR_24_8: 994 return 24; 995 996 case V_028C70_COLOR_32: 997 case V_028C70_COLOR_32_32: 998 case V_028C70_COLOR_32_32_32_32: 999 case V_028C70_COLOR_X24_8_32_FLOAT: 1000 return 32; 1001 } 1002 1003 assert(!"Unknown maximum component size"); 1004 return 0; 1005} 1006 1007static uint32_t si_translate_dbformat(enum pipe_format format) 1008{ 1009 switch (format) { 1010 case PIPE_FORMAT_Z16_UNORM: 1011 return V_028040_Z_16; 1012 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1013 case PIPE_FORMAT_X8Z24_UNORM: 1014 case PIPE_FORMAT_Z24X8_UNORM: 1015 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1016 return V_028040_Z_24; /* deprecated on SI */ 1017 case PIPE_FORMAT_Z32_FLOAT: 1018 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1019 return V_028040_Z_32_FLOAT; 1020 default: 1021 return V_028040_Z_INVALID; 1022 } 1023} 1024 1025/* 1026 * Texture translation 1027 */ 1028 1029static uint32_t si_translate_texformat(struct pipe_screen *screen, 1030 enum pipe_format format, 1031 const struct util_format_description *desc, 1032 int first_non_void) 1033{ 1034 struct si_screen *sscreen = (struct si_screen*)screen; 1035 bool enable_s3tc = sscreen->b.info.drm_minor >= 31; 1036 boolean uniform = TRUE; 1037 int i; 1038 1039 /* Colorspace (return non-RGB formats directly). */ 1040 switch (desc->colorspace) { 1041 /* Depth stencil formats */ 1042 case UTIL_FORMAT_COLORSPACE_ZS: 1043 switch (format) { 1044 case PIPE_FORMAT_Z16_UNORM: 1045 return V_008F14_IMG_DATA_FORMAT_16; 1046 case PIPE_FORMAT_X24S8_UINT: 1047 case PIPE_FORMAT_Z24X8_UNORM: 1048 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1049 return V_008F14_IMG_DATA_FORMAT_8_24; 1050 case PIPE_FORMAT_X8Z24_UNORM: 1051 case PIPE_FORMAT_S8X24_UINT: 1052 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1053 return V_008F14_IMG_DATA_FORMAT_24_8; 1054 case PIPE_FORMAT_S8_UINT: 1055 return V_008F14_IMG_DATA_FORMAT_8; 1056 case PIPE_FORMAT_Z32_FLOAT: 1057 return V_008F14_IMG_DATA_FORMAT_32; 1058 case PIPE_FORMAT_X32_S8X24_UINT: 1059 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1060 return V_008F14_IMG_DATA_FORMAT_X24_8_32; 1061 default: 1062 goto out_unknown; 1063 } 1064 1065 case UTIL_FORMAT_COLORSPACE_YUV: 1066 goto out_unknown; /* TODO */ 1067 1068 case UTIL_FORMAT_COLORSPACE_SRGB: 1069 if (desc->nr_channels != 4 && desc->nr_channels != 1) 1070 goto out_unknown; 1071 break; 1072 1073 default: 1074 break; 1075 } 1076 1077 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 1078 if (!enable_s3tc) 1079 goto out_unknown; 1080 1081 switch (format) { 1082 case PIPE_FORMAT_RGTC1_SNORM: 1083 case PIPE_FORMAT_LATC1_SNORM: 1084 case PIPE_FORMAT_RGTC1_UNORM: 1085 case PIPE_FORMAT_LATC1_UNORM: 1086 return V_008F14_IMG_DATA_FORMAT_BC4; 1087 case PIPE_FORMAT_RGTC2_SNORM: 1088 case PIPE_FORMAT_LATC2_SNORM: 1089 case PIPE_FORMAT_RGTC2_UNORM: 1090 case PIPE_FORMAT_LATC2_UNORM: 1091 return V_008F14_IMG_DATA_FORMAT_BC5; 1092 default: 1093 goto out_unknown; 1094 } 1095 } 1096 1097 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 1098 1099 if (!enable_s3tc) 1100 goto out_unknown; 1101 1102 if (!util_format_s3tc_enabled) { 1103 goto out_unknown; 1104 } 1105 1106 switch (format) { 1107 case PIPE_FORMAT_DXT1_RGB: 1108 case PIPE_FORMAT_DXT1_RGBA: 1109 case PIPE_FORMAT_DXT1_SRGB: 1110 case PIPE_FORMAT_DXT1_SRGBA: 1111 return V_008F14_IMG_DATA_FORMAT_BC1; 1112 case PIPE_FORMAT_DXT3_RGBA: 1113 case PIPE_FORMAT_DXT3_SRGBA: 1114 return V_008F14_IMG_DATA_FORMAT_BC2; 1115 case PIPE_FORMAT_DXT5_RGBA: 1116 case PIPE_FORMAT_DXT5_SRGBA: 1117 return V_008F14_IMG_DATA_FORMAT_BC3; 1118 default: 1119 goto out_unknown; 1120 } 1121 } 1122 1123 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 1124 return V_008F14_IMG_DATA_FORMAT_5_9_9_9; 1125 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 1126 return V_008F14_IMG_DATA_FORMAT_10_11_11; 1127 } 1128 1129 /* R8G8Bx_SNORM - TODO CxV8U8 */ 1130 1131 /* See whether the components are of the same size. */ 1132 for (i = 1; i < desc->nr_channels; i++) { 1133 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1134 } 1135 1136 /* Non-uniform formats. */ 1137 if (!uniform) { 1138 switch(desc->nr_channels) { 1139 case 3: 1140 if (desc->channel[0].size == 5 && 1141 desc->channel[1].size == 6 && 1142 desc->channel[2].size == 5) { 1143 return V_008F14_IMG_DATA_FORMAT_5_6_5; 1144 } 1145 goto out_unknown; 1146 case 4: 1147 if (desc->channel[0].size == 5 && 1148 desc->channel[1].size == 5 && 1149 desc->channel[2].size == 5 && 1150 desc->channel[3].size == 1) { 1151 return V_008F14_IMG_DATA_FORMAT_1_5_5_5; 1152 } 1153 if (desc->channel[0].size == 10 && 1154 desc->channel[1].size == 10 && 1155 desc->channel[2].size == 10 && 1156 desc->channel[3].size == 2) { 1157 return V_008F14_IMG_DATA_FORMAT_2_10_10_10; 1158 } 1159 goto out_unknown; 1160 } 1161 goto out_unknown; 1162 } 1163 1164 if (first_non_void < 0 || first_non_void > 3) 1165 goto out_unknown; 1166 1167 /* uniform formats */ 1168 switch (desc->channel[first_non_void].size) { 1169 case 4: 1170 switch (desc->nr_channels) { 1171#if 0 /* Not supported for render targets */ 1172 case 2: 1173 return V_008F14_IMG_DATA_FORMAT_4_4; 1174#endif 1175 case 4: 1176 return V_008F14_IMG_DATA_FORMAT_4_4_4_4; 1177 } 1178 break; 1179 case 8: 1180 switch (desc->nr_channels) { 1181 case 1: 1182 return V_008F14_IMG_DATA_FORMAT_8; 1183 case 2: 1184 return V_008F14_IMG_DATA_FORMAT_8_8; 1185 case 4: 1186 return V_008F14_IMG_DATA_FORMAT_8_8_8_8; 1187 } 1188 break; 1189 case 16: 1190 switch (desc->nr_channels) { 1191 case 1: 1192 return V_008F14_IMG_DATA_FORMAT_16; 1193 case 2: 1194 return V_008F14_IMG_DATA_FORMAT_16_16; 1195 case 4: 1196 return V_008F14_IMG_DATA_FORMAT_16_16_16_16; 1197 } 1198 break; 1199 case 32: 1200 switch (desc->nr_channels) { 1201 case 1: 1202 return V_008F14_IMG_DATA_FORMAT_32; 1203 case 2: 1204 return V_008F14_IMG_DATA_FORMAT_32_32; 1205#if 0 /* Not supported for render targets */ 1206 case 3: 1207 return V_008F14_IMG_DATA_FORMAT_32_32_32; 1208#endif 1209 case 4: 1210 return V_008F14_IMG_DATA_FORMAT_32_32_32_32; 1211 } 1212 } 1213 1214out_unknown: 1215 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1216 return ~0; 1217} 1218 1219static unsigned si_tex_wrap(unsigned wrap) 1220{ 1221 switch (wrap) { 1222 default: 1223 case PIPE_TEX_WRAP_REPEAT: 1224 return V_008F30_SQ_TEX_WRAP; 1225 case PIPE_TEX_WRAP_CLAMP: 1226 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER; 1227 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 1228 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL; 1229 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 1230 return V_008F30_SQ_TEX_CLAMP_BORDER; 1231 case PIPE_TEX_WRAP_MIRROR_REPEAT: 1232 return V_008F30_SQ_TEX_MIRROR; 1233 case PIPE_TEX_WRAP_MIRROR_CLAMP: 1234 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 1235 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 1236 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 1237 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 1238 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER; 1239 } 1240} 1241 1242static unsigned si_tex_filter(unsigned filter) 1243{ 1244 switch (filter) { 1245 default: 1246 case PIPE_TEX_FILTER_NEAREST: 1247 return V_008F38_SQ_TEX_XY_FILTER_POINT; 1248 case PIPE_TEX_FILTER_LINEAR: 1249 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR; 1250 } 1251} 1252 1253static unsigned si_tex_mipfilter(unsigned filter) 1254{ 1255 switch (filter) { 1256 case PIPE_TEX_MIPFILTER_NEAREST: 1257 return V_008F38_SQ_TEX_Z_FILTER_POINT; 1258 case PIPE_TEX_MIPFILTER_LINEAR: 1259 return V_008F38_SQ_TEX_Z_FILTER_LINEAR; 1260 default: 1261 case PIPE_TEX_MIPFILTER_NONE: 1262 return V_008F38_SQ_TEX_Z_FILTER_NONE; 1263 } 1264} 1265 1266static unsigned si_tex_compare(unsigned compare) 1267{ 1268 switch (compare) { 1269 default: 1270 case PIPE_FUNC_NEVER: 1271 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER; 1272 case PIPE_FUNC_LESS: 1273 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS; 1274 case PIPE_FUNC_EQUAL: 1275 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL; 1276 case PIPE_FUNC_LEQUAL: 1277 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 1278 case PIPE_FUNC_GREATER: 1279 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER; 1280 case PIPE_FUNC_NOTEQUAL: 1281 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 1282 case PIPE_FUNC_GEQUAL: 1283 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 1284 case PIPE_FUNC_ALWAYS: 1285 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS; 1286 } 1287} 1288 1289static unsigned si_tex_dim(unsigned dim, unsigned nr_samples) 1290{ 1291 switch (dim) { 1292 default: 1293 case PIPE_TEXTURE_1D: 1294 return V_008F1C_SQ_RSRC_IMG_1D; 1295 case PIPE_TEXTURE_1D_ARRAY: 1296 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY; 1297 case PIPE_TEXTURE_2D: 1298 case PIPE_TEXTURE_RECT: 1299 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA : 1300 V_008F1C_SQ_RSRC_IMG_2D; 1301 case PIPE_TEXTURE_2D_ARRAY: 1302 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : 1303 V_008F1C_SQ_RSRC_IMG_2D_ARRAY; 1304 case PIPE_TEXTURE_3D: 1305 return V_008F1C_SQ_RSRC_IMG_3D; 1306 case PIPE_TEXTURE_CUBE: 1307 return V_008F1C_SQ_RSRC_IMG_CUBE; 1308 } 1309} 1310 1311/* 1312 * Format support testing 1313 */ 1314 1315static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 1316{ 1317 return si_translate_texformat(screen, format, util_format_description(format), 1318 util_format_get_first_non_void_channel(format)) != ~0U; 1319} 1320 1321static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen, 1322 const struct util_format_description *desc, 1323 int first_non_void) 1324{ 1325 unsigned type = desc->channel[first_non_void].type; 1326 int i; 1327 1328 if (type == UTIL_FORMAT_TYPE_FIXED) 1329 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1330 1331 if (desc->nr_channels == 4 && 1332 desc->channel[0].size == 10 && 1333 desc->channel[1].size == 10 && 1334 desc->channel[2].size == 10 && 1335 desc->channel[3].size == 2) 1336 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10; 1337 1338 /* See whether the components are of the same size. */ 1339 for (i = 0; i < desc->nr_channels; i++) { 1340 if (desc->channel[first_non_void].size != desc->channel[i].size) 1341 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1342 } 1343 1344 switch (desc->channel[first_non_void].size) { 1345 case 8: 1346 switch (desc->nr_channels) { 1347 case 1: 1348 return V_008F0C_BUF_DATA_FORMAT_8; 1349 case 2: 1350 return V_008F0C_BUF_DATA_FORMAT_8_8; 1351 case 3: 1352 case 4: 1353 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8; 1354 } 1355 break; 1356 case 16: 1357 switch (desc->nr_channels) { 1358 case 1: 1359 return V_008F0C_BUF_DATA_FORMAT_16; 1360 case 2: 1361 return V_008F0C_BUF_DATA_FORMAT_16_16; 1362 case 3: 1363 case 4: 1364 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16; 1365 } 1366 break; 1367 case 32: 1368 /* From the Southern Islands ISA documentation about MTBUF: 1369 * 'Memory reads of data in memory that is 32 or 64 bits do not 1370 * undergo any format conversion.' 1371 */ 1372 if (type != UTIL_FORMAT_TYPE_FLOAT && 1373 !desc->channel[first_non_void].pure_integer) 1374 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1375 1376 switch (desc->nr_channels) { 1377 case 1: 1378 return V_008F0C_BUF_DATA_FORMAT_32; 1379 case 2: 1380 return V_008F0C_BUF_DATA_FORMAT_32_32; 1381 case 3: 1382 return V_008F0C_BUF_DATA_FORMAT_32_32_32; 1383 case 4: 1384 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32; 1385 } 1386 break; 1387 } 1388 1389 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1390} 1391 1392static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen, 1393 const struct util_format_description *desc, 1394 int first_non_void) 1395{ 1396 switch (desc->channel[first_non_void].type) { 1397 case UTIL_FORMAT_TYPE_SIGNED: 1398 if (desc->channel[first_non_void].normalized) 1399 return V_008F0C_BUF_NUM_FORMAT_SNORM; 1400 else if (desc->channel[first_non_void].pure_integer) 1401 return V_008F0C_BUF_NUM_FORMAT_SINT; 1402 else 1403 return V_008F0C_BUF_NUM_FORMAT_SSCALED; 1404 break; 1405 case UTIL_FORMAT_TYPE_UNSIGNED: 1406 if (desc->channel[first_non_void].normalized) 1407 return V_008F0C_BUF_NUM_FORMAT_UNORM; 1408 else if (desc->channel[first_non_void].pure_integer) 1409 return V_008F0C_BUF_NUM_FORMAT_UINT; 1410 else 1411 return V_008F0C_BUF_NUM_FORMAT_USCALED; 1412 break; 1413 case UTIL_FORMAT_TYPE_FLOAT: 1414 default: 1415 return V_008F0C_BUF_NUM_FORMAT_FLOAT; 1416 } 1417} 1418 1419static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format) 1420{ 1421 const struct util_format_description *desc; 1422 int first_non_void; 1423 unsigned data_format; 1424 1425 desc = util_format_description(format); 1426 first_non_void = util_format_get_first_non_void_channel(format); 1427 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void); 1428 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID; 1429} 1430 1431static bool si_is_colorbuffer_format_supported(enum pipe_format format) 1432{ 1433 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID && 1434 r600_translate_colorswap(format) != ~0U; 1435} 1436 1437static bool si_is_zs_format_supported(enum pipe_format format) 1438{ 1439 return si_translate_dbformat(format) != V_028040_Z_INVALID; 1440} 1441 1442boolean si_is_format_supported(struct pipe_screen *screen, 1443 enum pipe_format format, 1444 enum pipe_texture_target target, 1445 unsigned sample_count, 1446 unsigned usage) 1447{ 1448 struct si_screen *sscreen = (struct si_screen *)screen; 1449 unsigned retval = 0; 1450 1451 if (target >= PIPE_MAX_TEXTURE_TYPES) { 1452 R600_ERR("r600: unsupported texture type %d\n", target); 1453 return FALSE; 1454 } 1455 1456 if (!util_format_is_supported(format, usage)) 1457 return FALSE; 1458 1459 if (sample_count > 1) { 1460 if (HAVE_LLVM < 0x0304) 1461 return FALSE; 1462 1463 /* 2D tiling on CIK is supported since DRM 2.35.0 */ 1464 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35) 1465 return FALSE; 1466 1467 switch (sample_count) { 1468 case 2: 1469 case 4: 1470 case 8: 1471 break; 1472 default: 1473 return FALSE; 1474 } 1475 } 1476 1477 if (usage & PIPE_BIND_SAMPLER_VIEW) { 1478 if (target == PIPE_BUFFER) { 1479 if (si_is_vertex_format_supported(screen, format)) 1480 retval |= PIPE_BIND_SAMPLER_VIEW; 1481 } else { 1482 if (si_is_sampler_format_supported(screen, format)) 1483 retval |= PIPE_BIND_SAMPLER_VIEW; 1484 } 1485 } 1486 1487 if ((usage & (PIPE_BIND_RENDER_TARGET | 1488 PIPE_BIND_DISPLAY_TARGET | 1489 PIPE_BIND_SCANOUT | 1490 PIPE_BIND_SHARED)) && 1491 si_is_colorbuffer_format_supported(format)) { 1492 retval |= usage & 1493 (PIPE_BIND_RENDER_TARGET | 1494 PIPE_BIND_DISPLAY_TARGET | 1495 PIPE_BIND_SCANOUT | 1496 PIPE_BIND_SHARED); 1497 } 1498 1499 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 1500 si_is_zs_format_supported(format)) { 1501 retval |= PIPE_BIND_DEPTH_STENCIL; 1502 } 1503 1504 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 1505 si_is_vertex_format_supported(screen, format)) { 1506 retval |= PIPE_BIND_VERTEX_BUFFER; 1507 } 1508 1509 if (usage & PIPE_BIND_TRANSFER_READ) 1510 retval |= PIPE_BIND_TRANSFER_READ; 1511 if (usage & PIPE_BIND_TRANSFER_WRITE) 1512 retval |= PIPE_BIND_TRANSFER_WRITE; 1513 1514 return retval == usage; 1515} 1516 1517static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil) 1518{ 1519 unsigned tile_mode_index = 0; 1520 1521 if (stencil) { 1522 tile_mode_index = rtex->surface.stencil_tiling_index[level]; 1523 } else { 1524 tile_mode_index = rtex->surface.tiling_index[level]; 1525 } 1526 return tile_mode_index; 1527} 1528 1529/* 1530 * framebuffer handling 1531 */ 1532 1533static void si_initialize_color_surface(struct si_context *sctx, 1534 struct r600_surface *surf) 1535{ 1536 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; 1537 unsigned level = surf->base.u.tex.level; 1538 uint64_t offset = rtex->surface.level[level].offset; 1539 unsigned pitch, slice; 1540 unsigned color_info, color_attrib, color_pitch, color_view; 1541 unsigned tile_mode_index; 1542 unsigned format, swap, ntype, endian; 1543 const struct util_format_description *desc; 1544 int i; 1545 unsigned blend_clamp = 0, blend_bypass = 0; 1546 unsigned max_comp_size; 1547 1548 /* Layered rendering doesn't work with LINEAR_GENERAL. 1549 * (LINEAR_ALIGNED and others work) */ 1550 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) { 1551 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer); 1552 offset += rtex->surface.level[level].slice_size * 1553 surf->base.u.tex.first_layer; 1554 color_view = 0; 1555 } else { 1556 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | 1557 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); 1558 } 1559 1560 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; 1561 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1562 if (slice) { 1563 slice = slice - 1; 1564 } 1565 1566 tile_mode_index = si_tile_mode_index(rtex, level, false); 1567 1568 desc = util_format_description(surf->base.format); 1569 for (i = 0; i < 4; i++) { 1570 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1571 break; 1572 } 1573 } 1574 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { 1575 ntype = V_028C70_NUMBER_FLOAT; 1576 } else { 1577 ntype = V_028C70_NUMBER_UNORM; 1578 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1579 ntype = V_028C70_NUMBER_SRGB; 1580 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1581 if (desc->channel[i].pure_integer) { 1582 ntype = V_028C70_NUMBER_SINT; 1583 } else { 1584 assert(desc->channel[i].normalized); 1585 ntype = V_028C70_NUMBER_SNORM; 1586 } 1587 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1588 if (desc->channel[i].pure_integer) { 1589 ntype = V_028C70_NUMBER_UINT; 1590 } else { 1591 assert(desc->channel[i].normalized); 1592 ntype = V_028C70_NUMBER_UNORM; 1593 } 1594 } 1595 } 1596 1597 format = si_translate_colorformat(surf->base.format); 1598 if (format == V_028C70_COLOR_INVALID) { 1599 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format); 1600 } 1601 assert(format != V_028C70_COLOR_INVALID); 1602 swap = r600_translate_colorswap(surf->base.format); 1603 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { 1604 endian = V_028C70_ENDIAN_NONE; 1605 } else { 1606 endian = si_colorformat_endian_swap(format); 1607 } 1608 1609 /* blend clamp should be set for all NORM/SRGB types */ 1610 if (ntype == V_028C70_NUMBER_UNORM || 1611 ntype == V_028C70_NUMBER_SNORM || 1612 ntype == V_028C70_NUMBER_SRGB) 1613 blend_clamp = 1; 1614 1615 /* set blend bypass according to docs if SINT/UINT or 1616 8/24 COLOR variants */ 1617 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT || 1618 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 || 1619 format == V_028C70_COLOR_X24_8_32_FLOAT) { 1620 blend_clamp = 0; 1621 blend_bypass = 1; 1622 } 1623 1624 color_info = S_028C70_FORMAT(format) | 1625 S_028C70_COMP_SWAP(swap) | 1626 S_028C70_BLEND_CLAMP(blend_clamp) | 1627 S_028C70_BLEND_BYPASS(blend_bypass) | 1628 S_028C70_NUMBER_TYPE(ntype) | 1629 S_028C70_ENDIAN(endian); 1630 1631 color_pitch = S_028C64_TILE_MAX(pitch); 1632 1633 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) | 1634 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1); 1635 1636 if (rtex->resource.b.b.nr_samples > 1) { 1637 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples); 1638 1639 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | 1640 S_028C74_NUM_FRAGMENTS(log_samples); 1641 1642 if (rtex->fmask.size) { 1643 color_info |= S_028C70_COMPRESSION(1); 1644 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height); 1645 1646 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index); 1647 1648 if (sctx->b.chip_class == SI) { 1649 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */ 1650 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); 1651 } 1652 if (sctx->b.chip_class >= CIK) { 1653 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1); 1654 } 1655 } 1656 } 1657 1658 offset += r600_resource_va(sctx->b.b.screen, surf->base.texture); 1659 1660 surf->cb_color_base = offset >> 8; 1661 surf->cb_color_pitch = color_pitch; 1662 surf->cb_color_slice = S_028C68_TILE_MAX(slice); 1663 surf->cb_color_view = color_view; 1664 surf->cb_color_info = color_info; 1665 surf->cb_color_attrib = color_attrib; 1666 1667 if (rtex->fmask.size) { 1668 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8; 1669 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max); 1670 } else { 1671 /* This must be set for fast clear to work without FMASK. */ 1672 surf->cb_color_fmask = surf->cb_color_base; 1673 surf->cb_color_fmask_slice = surf->cb_color_slice; 1674 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index); 1675 1676 if (sctx->b.chip_class == SI) { 1677 unsigned bankh = util_logbase2(rtex->surface.bankh); 1678 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh); 1679 } 1680 1681 if (sctx->b.chip_class >= CIK) { 1682 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch); 1683 } 1684 } 1685 1686 /* Determine pixel shader export format */ 1687 max_comp_size = si_colorformat_max_comp_size(format); 1688 if (ntype == V_028C70_NUMBER_SRGB || 1689 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) && 1690 max_comp_size <= 10) || 1691 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) { 1692 surf->export_16bpc = true; 1693 } 1694 1695 surf->color_initialized = true; 1696} 1697 1698static void si_init_depth_surface(struct si_context *sctx, 1699 struct r600_surface *surf) 1700{ 1701 struct si_screen *sscreen = sctx->screen; 1702 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; 1703 unsigned level = surf->base.u.tex.level; 1704 unsigned pitch, slice, format, tile_mode_index, array_mode; 1705 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config; 1706 uint32_t z_info, s_info, db_depth_info; 1707 uint64_t z_offs, s_offs; 1708 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl; 1709 1710 switch (sctx->framebuffer.state.zsbuf->texture->format) { 1711 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1712 case PIPE_FORMAT_X8Z24_UNORM: 1713 case PIPE_FORMAT_Z24X8_UNORM: 1714 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1715 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24); 1716 break; 1717 case PIPE_FORMAT_Z32_FLOAT: 1718 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1719 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | 1720 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 1721 break; 1722 case PIPE_FORMAT_Z16_UNORM: 1723 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16); 1724 break; 1725 default: 1726 assert(0); 1727 } 1728 1729 format = si_translate_dbformat(rtex->resource.b.b.format); 1730 1731 if (format == V_028040_Z_INVALID) { 1732 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format); 1733 } 1734 assert(format != V_028040_Z_INVALID); 1735 1736 s_offs = z_offs = r600_resource_va(sctx->b.b.screen, surf->base.texture); 1737 z_offs += rtex->surface.level[level].offset; 1738 s_offs += rtex->surface.stencil_level[level].offset; 1739 1740 pitch = (rtex->surface.level[level].nblk_x / 8) - 1; 1741 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1742 if (slice) { 1743 slice = slice - 1; 1744 } 1745 1746 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1); 1747 1748 z_info = S_028040_FORMAT(format); 1749 if (rtex->resource.b.b.nr_samples > 1) { 1750 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)); 1751 } 1752 1753 if (rtex->surface.flags & RADEON_SURF_SBUFFER) 1754 s_info = S_028044_FORMAT(V_028044_STENCIL_8); 1755 else 1756 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID); 1757 1758 if (sctx->b.chip_class >= CIK) { 1759 switch (rtex->surface.level[level].mode) { 1760 case RADEON_SURF_MODE_2D: 1761 array_mode = V_02803C_ARRAY_2D_TILED_THIN1; 1762 break; 1763 case RADEON_SURF_MODE_1D: 1764 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1765 case RADEON_SURF_MODE_LINEAR: 1766 default: 1767 array_mode = V_02803C_ARRAY_1D_TILED_THIN1; 1768 break; 1769 } 1770 tile_split = rtex->surface.tile_split; 1771 stile_split = rtex->surface.stencil_tile_split; 1772 macro_aspect = rtex->surface.mtilea; 1773 bankw = rtex->surface.bankw; 1774 bankh = rtex->surface.bankh; 1775 tile_split = cik_tile_split(tile_split); 1776 stile_split = cik_tile_split(stile_split); 1777 macro_aspect = cik_macro_tile_aspect(macro_aspect); 1778 bankw = cik_bank_wh(bankw); 1779 bankh = cik_bank_wh(bankh); 1780 nbanks = cik_num_banks(sscreen, rtex->surface.bpe, rtex->surface.tile_split); 1781 tile_mode_index = si_tile_mode_index(rtex, level, false); 1782 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index); 1783 1784 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) | 1785 S_02803C_PIPE_CONFIG(pipe_config) | 1786 S_02803C_BANK_WIDTH(bankw) | 1787 S_02803C_BANK_HEIGHT(bankh) | 1788 S_02803C_MACRO_TILE_ASPECT(macro_aspect) | 1789 S_02803C_NUM_BANKS(nbanks); 1790 z_info |= S_028040_TILE_SPLIT(tile_split); 1791 s_info |= S_028044_TILE_SPLIT(stile_split); 1792 } else { 1793 tile_mode_index = si_tile_mode_index(rtex, level, false); 1794 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); 1795 tile_mode_index = si_tile_mode_index(rtex, level, true); 1796 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index); 1797 } 1798 1799 /* HiZ aka depth buffer htile */ 1800 /* use htile only for first level */ 1801 if (rtex->htile_buffer && !level) { 1802 const struct util_format_description *fmt_desc; 1803 1804 z_info |= S_028040_TILE_SURFACE_ENABLE(1); 1805 1806 /* This is optimal for the clear value of 1.0 and using 1807 * the LESS and LEQUAL test functions. Set this to 0 1808 * for the opposite case. This can only be changed when 1809 * clearing. */ 1810 z_info |= S_028040_ZRANGE_PRECISION(1); 1811 1812 fmt_desc = util_format_description(rtex->resource.b.b.format); 1813 if (!util_format_has_stencil(fmt_desc)) { 1814 /* Use all of the htile_buffer for depth */ 1815 s_info |= S_028044_TILE_STENCIL_DISABLE(1); 1816 } 1817 1818 uint64_t va = r600_resource_va(&sctx->screen->b.b, &rtex->htile_buffer->b.b); 1819 db_htile_data_base = va >> 8; 1820 db_htile_surface = S_028ABC_FULL_CACHE(1); 1821 } else { 1822 db_htile_data_base = 0; 1823 db_htile_surface = 0; 1824 } 1825 1826 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) | 1827 S_028008_SLICE_MAX(surf->base.u.tex.last_layer); 1828 surf->db_htile_data_base = db_htile_data_base; 1829 surf->db_depth_info = db_depth_info; 1830 surf->db_z_info = z_info; 1831 surf->db_stencil_info = s_info; 1832 surf->db_depth_base = z_offs >> 8; 1833 surf->db_stencil_base = s_offs >> 8; 1834 surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch); 1835 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice); 1836 surf->db_htile_surface = db_htile_surface; 1837 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl; 1838 1839 surf->depth_initialized = true; 1840} 1841 1842static void si_set_framebuffer_state(struct pipe_context *ctx, 1843 const struct pipe_framebuffer_state *state) 1844{ 1845 struct si_context *sctx = (struct si_context *)ctx; 1846 struct r600_surface *surf = NULL; 1847 struct r600_texture *rtex; 1848 int i; 1849 1850 if (sctx->framebuffer.state.nr_cbufs) { 1851 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB | 1852 R600_CONTEXT_FLUSH_AND_INV_CB_META; 1853 } 1854 if (sctx->framebuffer.state.zsbuf) { 1855 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB | 1856 R600_CONTEXT_FLUSH_AND_INV_DB_META; 1857 } 1858 1859 util_copy_framebuffer_state(&sctx->framebuffer.state, state); 1860 1861 sctx->framebuffer.export_16bpc = 0; 1862 sctx->framebuffer.compressed_cb_mask = 0; 1863 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state); 1864 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples); 1865 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] && 1866 util_format_is_pure_integer(state->cbufs[0]->format); 1867 1868 for (i = 0; i < state->nr_cbufs; i++) { 1869 if (!state->cbufs[i]) 1870 continue; 1871 1872 surf = (struct r600_surface*)state->cbufs[i]; 1873 rtex = (struct r600_texture*)surf->base.texture; 1874 1875 if (!surf->color_initialized) { 1876 si_initialize_color_surface(sctx, surf); 1877 } 1878 1879 if (surf->export_16bpc) { 1880 sctx->framebuffer.export_16bpc |= 1 << i; 1881 } 1882 1883 if (rtex->fmask.size && rtex->cmask.size) { 1884 sctx->framebuffer.compressed_cb_mask |= 1 << i; 1885 } 1886 } 1887 /* Set the 16BPC export for possible dual-src blending. */ 1888 if (i == 1 && surf && surf->export_16bpc) { 1889 sctx->framebuffer.export_16bpc |= 1 << 1; 1890 } 1891 1892 assert(!(sctx->framebuffer.export_16bpc & ~0xff)); 1893 1894 if (state->zsbuf) { 1895 surf = (struct r600_surface*)state->zsbuf; 1896 1897 if (!surf->depth_initialized) { 1898 si_init_depth_surface(sctx, surf); 1899 } 1900 } 1901 1902 si_update_fb_rs_state(sctx); 1903 si_update_fb_blend_state(sctx); 1904 1905 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3; 1906 sctx->framebuffer.atom.num_dw += state->zsbuf ? 23 : 4; 1907 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */ 1908 sctx->framebuffer.atom.num_dw += 25; /* MSAA */ 1909 sctx->framebuffer.atom.dirty = true; 1910} 1911 1912static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom) 1913{ 1914 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs; 1915 struct pipe_framebuffer_state *state = &sctx->framebuffer.state; 1916 unsigned i, nr_cbufs = state->nr_cbufs; 1917 struct r600_texture *tex = NULL; 1918 struct r600_surface *cb = NULL; 1919 1920 /* Colorbuffers. */ 1921 for (i = 0; i < nr_cbufs; i++) { 1922 cb = (struct r600_surface*)state->cbufs[i]; 1923 if (!cb) { 1924 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 1925 S_028C70_FORMAT(V_028C70_COLOR_INVALID)); 1926 continue; 1927 } 1928 1929 tex = (struct r600_texture *)cb->base.texture; 1930 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, 1931 &tex->resource, RADEON_USAGE_READWRITE, 1932 tex->surface.nsamples > 1 ? 1933 RADEON_PRIO_COLOR_BUFFER_MSAA : 1934 RADEON_PRIO_COLOR_BUFFER); 1935 1936 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) { 1937 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, 1938 tex->cmask_buffer, RADEON_USAGE_READWRITE, 1939 RADEON_PRIO_COLOR_META); 1940 } 1941 1942 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13); 1943 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */ 1944 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */ 1945 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */ 1946 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */ 1947 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */ 1948 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */ 1949 radeon_emit(cs, 0); /* R_028C78 unused */ 1950 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */ 1951 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */ 1952 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */ 1953 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */ 1954 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */ 1955 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */ 1956 } 1957 /* set CB_COLOR1_INFO for possible dual-src blending */ 1958 if (i == 1 && state->cbufs[0]) { 1959 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, 1960 cb->cb_color_info | tex->cb_color_info); 1961 i++; 1962 } 1963 for (; i < 8 ; i++) { 1964 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); 1965 } 1966 1967 /* ZS buffer. */ 1968 if (state->zsbuf) { 1969 struct r600_surface *zb = (struct r600_surface*)state->zsbuf; 1970 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture; 1971 1972 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, 1973 &rtex->resource, RADEON_USAGE_READWRITE, 1974 zb->base.texture->nr_samples > 1 ? 1975 RADEON_PRIO_DEPTH_BUFFER_MSAA : 1976 RADEON_PRIO_DEPTH_BUFFER); 1977 1978 if (zb->db_htile_data_base) { 1979 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx, 1980 rtex->htile_buffer, RADEON_USAGE_READWRITE, 1981 RADEON_PRIO_DEPTH_META); 1982 } 1983 1984 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); 1985 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base); 1986 1987 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9); 1988 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */ 1989 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */ 1990 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */ 1991 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */ 1992 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */ 1993 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */ 1994 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */ 1995 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */ 1996 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */ 1997 1998 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface); 1999 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2000 zb->pa_su_poly_offset_db_fmt_cntl); 2001 } else { 2002 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2); 2003 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */ 2004 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */ 2005 } 2006 2007 /* Framebuffer dimensions. */ 2008 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */ 2009 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR, 2010 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height)); 2011 2012 cayman_emit_msaa_state(cs, sctx->framebuffer.nr_samples); 2013} 2014 2015/* 2016 * shaders 2017 */ 2018 2019/* Compute the key for the hw shader variant */ 2020static INLINE void si_shader_selector_key(struct pipe_context *ctx, 2021 struct si_pipe_shader_selector *sel, 2022 union si_shader_key *key) 2023{ 2024 struct si_context *sctx = (struct si_context *)ctx; 2025 memset(key, 0, sizeof(*key)); 2026 2027 if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_GEOMETRY) && 2028 sctx->queued.named.rasterizer) { 2029 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf0) 2030 key->vs.ucps_enabled |= 0x2; 2031 if (sctx->queued.named.rasterizer->clip_plane_enable & 0xf) 2032 key->vs.ucps_enabled |= 0x1; 2033 } 2034 2035 if (sel->type == PIPE_SHADER_VERTEX) { 2036 unsigned i; 2037 if (!sctx->vertex_elements) 2038 return; 2039 2040 for (i = 0; i < sctx->vertex_elements->count; ++i) 2041 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor; 2042 2043 key->vs.as_es = sctx->gs_shader != NULL; 2044 } else if (sel->type == PIPE_SHADER_FRAGMENT) { 2045 if (sel->fs_write_all) 2046 key->ps.nr_cbufs = sctx->framebuffer.state.nr_cbufs; 2047 key->ps.export_16bpc = sctx->framebuffer.export_16bpc; 2048 2049 if (sctx->queued.named.rasterizer) { 2050 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side; 2051 key->ps.flatshade = sctx->queued.named.rasterizer->flatshade; 2052 2053 if (sctx->queued.named.blend) { 2054 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one && 2055 sctx->queued.named.rasterizer->multisample_enable && 2056 !sctx->framebuffer.cb0_is_integer; 2057 } 2058 } 2059 if (sctx->queued.named.dsa) { 2060 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func; 2061 2062 /* Alpha-test should be disabled if colorbuffer 0 is integer. */ 2063 if (sctx->framebuffer.cb0_is_integer) 2064 key->ps.alpha_func = PIPE_FUNC_ALWAYS; 2065 } else { 2066 key->ps.alpha_func = PIPE_FUNC_ALWAYS; 2067 } 2068 } 2069} 2070 2071/* Select the hw shader variant depending on the current state. */ 2072int si_shader_select(struct pipe_context *ctx, 2073 struct si_pipe_shader_selector *sel) 2074{ 2075 union si_shader_key key; 2076 struct si_pipe_shader * shader = NULL; 2077 int r; 2078 2079 si_shader_selector_key(ctx, sel, &key); 2080 2081 /* Check if we don't need to change anything. 2082 * This path is also used for most shaders that don't need multiple 2083 * variants, it will cost just a computation of the key and this 2084 * test. */ 2085 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) { 2086 return 0; 2087 } 2088 2089 /* lookup if we have other variants in the list */ 2090 if (sel->num_shaders > 1) { 2091 struct si_pipe_shader *p = sel->current, *c = p->next_variant; 2092 2093 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) { 2094 p = c; 2095 c = c->next_variant; 2096 } 2097 2098 if (c) { 2099 p->next_variant = c->next_variant; 2100 shader = c; 2101 } 2102 } 2103 2104 if (shader) { 2105 shader->next_variant = sel->current; 2106 sel->current = shader; 2107 } else { 2108 shader = CALLOC(1, sizeof(struct si_pipe_shader)); 2109 shader->selector = sel; 2110 shader->key = key; 2111 2112 shader->next_variant = sel->current; 2113 sel->current = shader; 2114 r = si_pipe_shader_create(ctx, shader); 2115 if (unlikely(r)) { 2116 R600_ERR("Failed to build shader variant (type=%u) %d\n", 2117 sel->type, r); 2118 sel->current = NULL; 2119 FREE(shader); 2120 return r; 2121 } 2122 sel->num_shaders++; 2123 } 2124 2125 return 0; 2126} 2127 2128static void *si_create_shader_state(struct pipe_context *ctx, 2129 const struct pipe_shader_state *state, 2130 unsigned pipe_shader_type) 2131{ 2132 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector); 2133 int r; 2134 2135 sel->type = pipe_shader_type; 2136 sel->tokens = tgsi_dup_tokens(state->tokens); 2137 sel->so = state->stream_output; 2138 2139 if (pipe_shader_type == PIPE_SHADER_FRAGMENT) { 2140 struct tgsi_shader_info info; 2141 2142 tgsi_scan_shader(state->tokens, &info); 2143 sel->fs_write_all = info.color0_writes_all_cbufs; 2144 } 2145 2146 r = si_shader_select(ctx, sel); 2147 if (r) { 2148 free(sel); 2149 return NULL; 2150 } 2151 2152 return sel; 2153} 2154 2155static void *si_create_fs_state(struct pipe_context *ctx, 2156 const struct pipe_shader_state *state) 2157{ 2158 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT); 2159} 2160 2161#if HAVE_LLVM >= 0x0305 2162 2163static void *si_create_gs_state(struct pipe_context *ctx, 2164 const struct pipe_shader_state *state) 2165{ 2166 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY); 2167} 2168 2169#endif 2170 2171static void *si_create_vs_state(struct pipe_context *ctx, 2172 const struct pipe_shader_state *state) 2173{ 2174 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX); 2175} 2176 2177static void si_bind_vs_shader(struct pipe_context *ctx, void *state) 2178{ 2179 struct si_context *sctx = (struct si_context *)ctx; 2180 struct si_pipe_shader_selector *sel = state; 2181 2182 if (sctx->vs_shader == sel) 2183 return; 2184 2185 if (!sel || !sel->current) 2186 return; 2187 2188 sctx->vs_shader = sel; 2189} 2190 2191#if HAVE_LLVM >= 0x0305 2192 2193static void si_bind_gs_shader(struct pipe_context *ctx, void *state) 2194{ 2195 struct si_context *sctx = (struct si_context *)ctx; 2196 struct si_pipe_shader_selector *sel = state; 2197 2198 if (sctx->gs_shader == sel) 2199 return; 2200 2201 sctx->gs_shader = sel; 2202} 2203 2204#endif 2205 2206static void si_bind_ps_shader(struct pipe_context *ctx, void *state) 2207{ 2208 struct si_context *sctx = (struct si_context *)ctx; 2209 struct si_pipe_shader_selector *sel = state; 2210 2211 if (sctx->ps_shader == sel) 2212 return; 2213 2214 if (!sel || !sel->current) 2215 sel = sctx->dummy_pixel_shader; 2216 2217 sctx->ps_shader = sel; 2218} 2219 2220static void si_delete_shader_selector(struct pipe_context *ctx, 2221 struct si_pipe_shader_selector *sel) 2222{ 2223 struct si_context *sctx = (struct si_context *)ctx; 2224 struct si_pipe_shader *p = sel->current, *c; 2225 2226 while (p) { 2227 c = p->next_variant; 2228 if (sel->type == PIPE_SHADER_GEOMETRY) 2229 si_pm4_delete_state(sctx, gs, p->pm4); 2230 else if (sel->type == PIPE_SHADER_FRAGMENT) 2231 si_pm4_delete_state(sctx, ps, p->pm4); 2232 else if (p->key.vs.as_es) 2233 si_pm4_delete_state(sctx, es, p->pm4); 2234 else 2235 si_pm4_delete_state(sctx, vs, p->pm4); 2236 si_pipe_shader_destroy(ctx, p); 2237 free(p); 2238 p = c; 2239 } 2240 2241 free(sel->tokens); 2242 free(sel); 2243 } 2244 2245static void si_delete_vs_shader(struct pipe_context *ctx, void *state) 2246{ 2247 struct si_context *sctx = (struct si_context *)ctx; 2248 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; 2249 2250 if (sctx->vs_shader == sel) { 2251 sctx->vs_shader = NULL; 2252 } 2253 2254 si_delete_shader_selector(ctx, sel); 2255} 2256 2257#if HAVE_LLVM >= 0x0305 2258 2259static void si_delete_gs_shader(struct pipe_context *ctx, void *state) 2260{ 2261 struct si_context *sctx = (struct si_context *)ctx; 2262 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; 2263 2264 if (sctx->gs_shader == sel) { 2265 sctx->gs_shader = NULL; 2266 } 2267 2268 si_delete_shader_selector(ctx, sel); 2269} 2270 2271#endif 2272 2273static void si_delete_ps_shader(struct pipe_context *ctx, void *state) 2274{ 2275 struct si_context *sctx = (struct si_context *)ctx; 2276 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; 2277 2278 if (sctx->ps_shader == sel) { 2279 sctx->ps_shader = NULL; 2280 } 2281 2282 si_delete_shader_selector(ctx, sel); 2283} 2284 2285/* 2286 * Samplers 2287 */ 2288 2289static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx, 2290 struct pipe_resource *texture, 2291 const struct pipe_sampler_view *state) 2292{ 2293 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view); 2294 struct r600_texture *tmp = (struct r600_texture*)texture; 2295 const struct util_format_description *desc; 2296 unsigned format, num_format; 2297 uint32_t pitch = 0; 2298 unsigned char state_swizzle[4], swizzle[4]; 2299 unsigned height, depth, width; 2300 enum pipe_format pipe_format = state->format; 2301 struct radeon_surface_level *surflevel; 2302 int first_non_void; 2303 uint64_t va; 2304 2305 if (view == NULL) 2306 return NULL; 2307 2308 /* initialize base object */ 2309 view->base = *state; 2310 view->base.texture = NULL; 2311 pipe_resource_reference(&view->base.texture, texture); 2312 view->base.reference.count = 1; 2313 view->base.context = ctx; 2314 view->resource = &tmp->resource; 2315 2316 /* Buffer resource. */ 2317 if (texture->target == PIPE_BUFFER) { 2318 unsigned stride; 2319 2320 desc = util_format_description(state->format); 2321 first_non_void = util_format_get_first_non_void_channel(state->format); 2322 stride = desc->block.bits / 8; 2323 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride; 2324 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void); 2325 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void); 2326 2327 view->state[0] = va; 2328 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | 2329 S_008F04_STRIDE(stride); 2330 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element; 2331 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | 2332 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | 2333 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | 2334 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | 2335 S_008F0C_NUM_FORMAT(num_format) | 2336 S_008F0C_DATA_FORMAT(format); 2337 return &view->base; 2338 } 2339 2340 state_swizzle[0] = state->swizzle_r; 2341 state_swizzle[1] = state->swizzle_g; 2342 state_swizzle[2] = state->swizzle_b; 2343 state_swizzle[3] = state->swizzle_a; 2344 2345 surflevel = tmp->surface.level; 2346 2347 /* Texturing with separate depth and stencil. */ 2348 if (tmp->is_depth && !tmp->is_flushing_texture) { 2349 switch (pipe_format) { 2350 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 2351 pipe_format = PIPE_FORMAT_Z32_FLOAT; 2352 break; 2353 case PIPE_FORMAT_X8Z24_UNORM: 2354 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2355 /* Z24 is always stored like this. */ 2356 pipe_format = PIPE_FORMAT_Z24X8_UNORM; 2357 break; 2358 case PIPE_FORMAT_X24S8_UINT: 2359 case PIPE_FORMAT_S8X24_UINT: 2360 case PIPE_FORMAT_X32_S8X24_UINT: 2361 pipe_format = PIPE_FORMAT_S8_UINT; 2362 surflevel = tmp->surface.stencil_level; 2363 break; 2364 default:; 2365 } 2366 } 2367 2368 desc = util_format_description(pipe_format); 2369 2370 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) { 2371 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0}; 2372 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1}; 2373 2374 switch (pipe_format) { 2375 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2376 case PIPE_FORMAT_X24S8_UINT: 2377 case PIPE_FORMAT_X32_S8X24_UINT: 2378 case PIPE_FORMAT_X8Z24_UNORM: 2379 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle); 2380 break; 2381 default: 2382 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle); 2383 } 2384 } else { 2385 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle); 2386 } 2387 2388 first_non_void = util_format_get_first_non_void_channel(pipe_format); 2389 2390 switch (pipe_format) { 2391 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2392 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2393 break; 2394 default: 2395 if (first_non_void < 0) { 2396 if (util_format_is_compressed(pipe_format)) { 2397 switch (pipe_format) { 2398 case PIPE_FORMAT_DXT1_SRGB: 2399 case PIPE_FORMAT_DXT1_SRGBA: 2400 case PIPE_FORMAT_DXT3_SRGBA: 2401 case PIPE_FORMAT_DXT5_SRGBA: 2402 num_format = V_008F14_IMG_NUM_FORMAT_SRGB; 2403 break; 2404 case PIPE_FORMAT_RGTC1_SNORM: 2405 case PIPE_FORMAT_LATC1_SNORM: 2406 case PIPE_FORMAT_RGTC2_SNORM: 2407 case PIPE_FORMAT_LATC2_SNORM: 2408 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 2409 break; 2410 default: 2411 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2412 break; 2413 } 2414 } else { 2415 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2416 } 2417 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) { 2418 num_format = V_008F14_IMG_NUM_FORMAT_SRGB; 2419 } else { 2420 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2421 2422 switch (desc->channel[first_non_void].type) { 2423 case UTIL_FORMAT_TYPE_FLOAT: 2424 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2425 break; 2426 case UTIL_FORMAT_TYPE_SIGNED: 2427 if (desc->channel[first_non_void].normalized) 2428 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 2429 else if (desc->channel[first_non_void].pure_integer) 2430 num_format = V_008F14_IMG_NUM_FORMAT_SINT; 2431 else 2432 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED; 2433 break; 2434 case UTIL_FORMAT_TYPE_UNSIGNED: 2435 if (desc->channel[first_non_void].normalized) 2436 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2437 else if (desc->channel[first_non_void].pure_integer) 2438 num_format = V_008F14_IMG_NUM_FORMAT_UINT; 2439 else 2440 num_format = V_008F14_IMG_NUM_FORMAT_USCALED; 2441 } 2442 } 2443 } 2444 2445 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void); 2446 if (format == ~0) { 2447 format = 0; 2448 } 2449 2450 /* not supported any more */ 2451 //endian = si_colorformat_endian_swap(format); 2452 2453 width = surflevel[0].npix_x; 2454 height = surflevel[0].npix_y; 2455 depth = surflevel[0].npix_z; 2456 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format); 2457 2458 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 2459 height = 1; 2460 depth = texture->array_size; 2461 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 2462 depth = texture->array_size; 2463 } 2464 2465 va = r600_resource_va(ctx->screen, texture); 2466 va += surflevel[0].offset; 2467 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size; 2468 2469 view->state[0] = va >> 8; 2470 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) | 2471 S_008F14_DATA_FORMAT(format) | 2472 S_008F14_NUM_FORMAT(num_format)); 2473 view->state[2] = (S_008F18_WIDTH(width - 1) | 2474 S_008F18_HEIGHT(height - 1)); 2475 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) | 2476 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | 2477 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | 2478 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | 2479 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ? 2480 0 : state->u.tex.first_level - tmp->mipmap_shift) | 2481 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ? 2482 util_logbase2(texture->nr_samples) : 2483 state->u.tex.last_level - tmp->mipmap_shift) | 2484 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) | 2485 S_008F1C_POW2_PAD(texture->last_level > 0) | 2486 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples))); 2487 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1)); 2488 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) | 2489 S_008F24_LAST_ARRAY(state->u.tex.last_layer)); 2490 view->state[6] = 0; 2491 view->state[7] = 0; 2492 2493 /* Initialize the sampler view for FMASK. */ 2494 if (tmp->fmask.size) { 2495 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset; 2496 uint32_t fmask_format; 2497 2498 switch (texture->nr_samples) { 2499 case 2: 2500 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2; 2501 break; 2502 case 4: 2503 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4; 2504 break; 2505 case 8: 2506 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8; 2507 break; 2508 default: 2509 assert(0); 2510 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID; 2511 } 2512 2513 view->fmask_state[0] = va >> 8; 2514 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) | 2515 S_008F14_DATA_FORMAT(fmask_format) | 2516 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT); 2517 view->fmask_state[2] = S_008F18_WIDTH(width - 1) | 2518 S_008F18_HEIGHT(height - 1); 2519 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) | 2520 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) | 2521 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | 2522 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) | 2523 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) | 2524 S_008F1C_TYPE(si_tex_dim(texture->target, 0)); 2525 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) | 2526 S_008F20_PITCH(tmp->fmask.pitch - 1); 2527 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) | 2528 S_008F24_LAST_ARRAY(state->u.tex.last_layer); 2529 view->fmask_state[6] = 0; 2530 view->fmask_state[7] = 0; 2531 } 2532 2533 return &view->base; 2534} 2535 2536static void si_sampler_view_destroy(struct pipe_context *ctx, 2537 struct pipe_sampler_view *state) 2538{ 2539 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; 2540 2541 pipe_resource_reference(&state->texture, NULL); 2542 FREE(resource); 2543} 2544 2545static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter) 2546{ 2547 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER || 2548 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER || 2549 (linear_filter && 2550 (wrap == PIPE_TEX_WRAP_CLAMP || 2551 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP)); 2552} 2553 2554static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state) 2555{ 2556 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST || 2557 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST; 2558 2559 return (state->border_color.ui[0] || state->border_color.ui[1] || 2560 state->border_color.ui[2] || state->border_color.ui[3]) && 2561 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) || 2562 wrap_mode_uses_border_color(state->wrap_t, linear_filter) || 2563 wrap_mode_uses_border_color(state->wrap_r, linear_filter)); 2564} 2565 2566static void *si_create_sampler_state(struct pipe_context *ctx, 2567 const struct pipe_sampler_state *state) 2568{ 2569 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state); 2570 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; 2571 unsigned border_color_type; 2572 2573 if (rstate == NULL) { 2574 return NULL; 2575 } 2576 2577 if (sampler_state_needs_border_color(state)) 2578 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER; 2579 else 2580 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; 2581 2582 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | 2583 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) | 2584 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) | 2585 (state->max_anisotropy & 0x7) << 9 | /* XXX */ 2586 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) | 2587 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) | 2588 aniso_flag_offset << 16 | /* XXX */ 2589 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map)); 2590 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | 2591 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8))); 2592 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) | 2593 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) | 2594 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) | 2595 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter))); 2596 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type); 2597 2598 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) { 2599 memcpy(rstate->border_color, state->border_color.ui, 2600 sizeof(rstate->border_color)); 2601 } 2602 2603 return rstate; 2604} 2605 2606/* XXX consider moving this function to si_descriptors.c for gcc to inline 2607 * the si_set_sampler_view calls. LTO might help too. */ 2608static void si_set_sampler_views(struct pipe_context *ctx, 2609 unsigned shader, unsigned start, 2610 unsigned count, 2611 struct pipe_sampler_view **views) 2612{ 2613 struct si_context *sctx = (struct si_context *)ctx; 2614 struct si_textures_info *samplers = &sctx->samplers[shader]; 2615 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views; 2616 int i; 2617 2618 if (shader >= SI_NUM_SHADERS) 2619 return; 2620 2621 assert(start == 0); 2622 2623 for (i = 0; i < count; i++) { 2624 if (!views[i]) { 2625 samplers->depth_texture_mask &= ~(1 << i); 2626 samplers->compressed_colortex_mask &= ~(1 << i); 2627 si_set_sampler_view(sctx, shader, i, NULL, NULL); 2628 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i, 2629 NULL, NULL); 2630 continue; 2631 } 2632 2633 si_set_sampler_view(sctx, shader, i, views[i], rviews[i]->state); 2634 2635 if (views[i]->texture->target != PIPE_BUFFER) { 2636 struct r600_texture *rtex = 2637 (struct r600_texture*)views[i]->texture; 2638 2639 if (rtex->is_depth && !rtex->is_flushing_texture) { 2640 samplers->depth_texture_mask |= 1 << i; 2641 } else { 2642 samplers->depth_texture_mask &= ~(1 << i); 2643 } 2644 if (rtex->cmask.size || rtex->fmask.size) { 2645 samplers->compressed_colortex_mask |= 1 << i; 2646 } else { 2647 samplers->compressed_colortex_mask &= ~(1 << i); 2648 } 2649 2650 if (rtex->fmask.size) { 2651 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i, 2652 views[i], rviews[i]->fmask_state); 2653 } else { 2654 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i, 2655 NULL, NULL); 2656 } 2657 } 2658 } 2659 for (; i < samplers->n_views; i++) { 2660 samplers->depth_texture_mask &= ~(1 << i); 2661 samplers->compressed_colortex_mask &= ~(1 << i); 2662 si_set_sampler_view(sctx, shader, i, NULL, NULL); 2663 si_set_sampler_view(sctx, shader, FMASK_TEX_OFFSET + i, 2664 NULL, NULL); 2665 } 2666 2667 samplers->n_views = count; 2668 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE; 2669} 2670 2671static void si_set_sampler_states(struct si_context *sctx, 2672 struct si_pm4_state *pm4, 2673 unsigned count, void **states, 2674 struct si_textures_info *samplers, 2675 unsigned user_data_reg) 2676{ 2677 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states; 2678 uint32_t *border_color_table = NULL; 2679 int i, j; 2680 2681 if (!count) 2682 goto out; 2683 2684 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE; 2685 2686 si_pm4_sh_data_begin(pm4); 2687 for (i = 0; i < count; i++) { 2688 if (rstates[i] && 2689 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) == 2690 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) { 2691 if (!sctx->border_color_table || 2692 ((sctx->border_color_offset + count - i) & 2693 C_008F3C_BORDER_COLOR_PTR)) { 2694 r600_resource_reference(&sctx->border_color_table, NULL); 2695 sctx->border_color_offset = 0; 2696 2697 sctx->border_color_table = 2698 si_resource_create_custom(&sctx->screen->b.b, 2699 PIPE_USAGE_STAGING, 2700 4096 * 4 * 4); 2701 } 2702 2703 if (!border_color_table) { 2704 border_color_table = 2705 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf, 2706 sctx->b.rings.gfx.cs, 2707 PIPE_TRANSFER_WRITE | 2708 PIPE_TRANSFER_UNSYNCHRONIZED); 2709 } 2710 2711 for (j = 0; j < 4; j++) { 2712 border_color_table[4 * sctx->border_color_offset + j] = 2713 util_le32_to_cpu(rstates[i]->border_color[j]); 2714 } 2715 2716 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR; 2717 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++); 2718 } 2719 2720 for (j = 0; j < Elements(rstates[i]->val); ++j) { 2721 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0); 2722 } 2723 } 2724 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER); 2725 2726 if (border_color_table) { 2727 uint64_t va_offset = 2728 r600_resource_va(&sctx->screen->b.b, 2729 (void*)sctx->border_color_table); 2730 2731 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8); 2732 if (sctx->b.chip_class >= CIK) 2733 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40); 2734 sctx->b.ws->buffer_unmap(sctx->border_color_table->cs_buf); 2735 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ, 2736 RADEON_PRIO_SHADER_DATA); 2737 } 2738 2739 memcpy(samplers->samplers, states, sizeof(void*) * count); 2740 2741out: 2742 samplers->n_samplers = count; 2743} 2744 2745static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states) 2746{ 2747 struct si_context *sctx = (struct si_context *)ctx; 2748 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 2749 2750 si_set_sampler_states(sctx, pm4, count, states, 2751 &sctx->samplers[PIPE_SHADER_VERTEX], 2752 R_00B130_SPI_SHADER_USER_DATA_VS_0); 2753#if HAVE_LLVM >= 0x0305 2754 si_set_sampler_states(sctx, pm4, count, states, 2755 &sctx->samplers[PIPE_SHADER_VERTEX], 2756 R_00B330_SPI_SHADER_USER_DATA_ES_0); 2757#endif 2758 si_pm4_set_state(sctx, vs_sampler, pm4); 2759} 2760 2761static void si_bind_gs_sampler_states(struct pipe_context *ctx, unsigned count, void **states) 2762{ 2763 struct si_context *sctx = (struct si_context *)ctx; 2764 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 2765 2766 si_set_sampler_states(sctx, pm4, count, states, 2767 &sctx->samplers[PIPE_SHADER_GEOMETRY], 2768 R_00B230_SPI_SHADER_USER_DATA_GS_0); 2769 si_pm4_set_state(sctx, gs_sampler, pm4); 2770} 2771 2772static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states) 2773{ 2774 struct si_context *sctx = (struct si_context *)ctx; 2775 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 2776 2777 si_set_sampler_states(sctx, pm4, count, states, 2778 &sctx->samplers[PIPE_SHADER_FRAGMENT], 2779 R_00B030_SPI_SHADER_USER_DATA_PS_0); 2780 si_pm4_set_state(sctx, ps_sampler, pm4); 2781} 2782 2783 2784static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader, 2785 unsigned start, unsigned count, 2786 void **states) 2787{ 2788 assert(start == 0); 2789 2790 switch (shader) { 2791 case PIPE_SHADER_VERTEX: 2792 si_bind_vs_sampler_states(ctx, count, states); 2793 break; 2794 case PIPE_SHADER_GEOMETRY: 2795 si_bind_gs_sampler_states(ctx, count, states); 2796 break; 2797 case PIPE_SHADER_FRAGMENT: 2798 si_bind_ps_sampler_states(ctx, count, states); 2799 break; 2800 default: 2801 ; 2802 } 2803} 2804 2805 2806 2807static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask) 2808{ 2809 struct si_context *sctx = (struct si_context *)ctx; 2810 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 2811 uint16_t mask = sample_mask; 2812 2813 if (pm4 == NULL) 2814 return; 2815 2816 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16)); 2817 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16)); 2818 2819 si_pm4_set_state(sctx, sample_mask, pm4); 2820} 2821 2822static void si_delete_sampler_state(struct pipe_context *ctx, void *state) 2823{ 2824 free(state); 2825} 2826 2827/* 2828 * Vertex elements & buffers 2829 */ 2830 2831static void *si_create_vertex_elements(struct pipe_context *ctx, 2832 unsigned count, 2833 const struct pipe_vertex_element *elements) 2834{ 2835 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element); 2836 int i; 2837 2838 assert(count < PIPE_MAX_ATTRIBS); 2839 if (!v) 2840 return NULL; 2841 2842 v->count = count; 2843 for (i = 0; i < count; ++i) { 2844 const struct util_format_description *desc; 2845 unsigned data_format, num_format; 2846 int first_non_void; 2847 2848 desc = util_format_description(elements[i].src_format); 2849 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format); 2850 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void); 2851 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void); 2852 2853 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | 2854 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | 2855 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | 2856 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | 2857 S_008F0C_NUM_FORMAT(num_format) | 2858 S_008F0C_DATA_FORMAT(data_format); 2859 } 2860 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); 2861 2862 return v; 2863} 2864 2865static void si_bind_vertex_elements(struct pipe_context *ctx, void *state) 2866{ 2867 struct si_context *sctx = (struct si_context *)ctx; 2868 struct si_vertex_element *v = (struct si_vertex_element*)state; 2869 2870 sctx->vertex_elements = v; 2871} 2872 2873static void si_delete_vertex_element(struct pipe_context *ctx, void *state) 2874{ 2875 struct si_context *sctx = (struct si_context *)ctx; 2876 2877 if (sctx->vertex_elements == state) 2878 sctx->vertex_elements = NULL; 2879 FREE(state); 2880} 2881 2882static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count, 2883 const struct pipe_vertex_buffer *buffers) 2884{ 2885 struct si_context *sctx = (struct si_context *)ctx; 2886 2887 util_set_vertex_buffers_count(sctx->vertex_buffer, &sctx->nr_vertex_buffers, buffers, start_slot, count); 2888} 2889 2890static void si_set_index_buffer(struct pipe_context *ctx, 2891 const struct pipe_index_buffer *ib) 2892{ 2893 struct si_context *sctx = (struct si_context *)ctx; 2894 2895 if (ib) { 2896 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer); 2897 memcpy(&sctx->index_buffer, ib, sizeof(*ib)); 2898 } else { 2899 pipe_resource_reference(&sctx->index_buffer.buffer, NULL); 2900 } 2901} 2902 2903/* 2904 * Misc 2905 */ 2906static void si_set_polygon_stipple(struct pipe_context *ctx, 2907 const struct pipe_poly_stipple *state) 2908{ 2909} 2910 2911static void si_texture_barrier(struct pipe_context *ctx) 2912{ 2913 struct si_context *sctx = (struct si_context *)ctx; 2914 2915 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE | 2916 R600_CONTEXT_FLUSH_AND_INV_CB; 2917} 2918 2919static void *si_create_blend_custom(struct si_context *sctx, unsigned mode) 2920{ 2921 struct pipe_blend_state blend; 2922 2923 memset(&blend, 0, sizeof(blend)); 2924 blend.independent_blend_enable = true; 2925 blend.rt[0].colormask = 0xf; 2926 return si_create_blend_state_mode(&sctx->b.b, &blend, mode); 2927} 2928 2929static boolean si_dma_copy(struct pipe_context *ctx, 2930 struct pipe_resource *dst, 2931 unsigned dst_level, 2932 unsigned dst_x, unsigned dst_y, unsigned dst_z, 2933 struct pipe_resource *src, 2934 unsigned src_level, 2935 const struct pipe_box *src_box) 2936{ 2937 /* XXX implement this or share evergreen_dma_blit with r600g */ 2938 return FALSE; 2939} 2940 2941static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable) 2942{ 2943 /* XXX Turn this into a proper state. Right now the queries are 2944 * enabled in draw_vbo, which snoops r600_common_context to see 2945 * if any occlusion queries are active. */ 2946} 2947 2948static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw, 2949 bool include_draw_vbo) 2950{ 2951 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo); 2952} 2953 2954void si_init_state_functions(struct si_context *sctx) 2955{ 2956 int i; 2957 2958 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.framebuffer, si_emit_framebuffer_state, 0); 2959 2960 sctx->b.b.create_blend_state = si_create_blend_state; 2961 sctx->b.b.bind_blend_state = si_bind_blend_state; 2962 sctx->b.b.delete_blend_state = si_delete_blend_state; 2963 sctx->b.b.set_blend_color = si_set_blend_color; 2964 2965 sctx->b.b.create_rasterizer_state = si_create_rs_state; 2966 sctx->b.b.bind_rasterizer_state = si_bind_rs_state; 2967 sctx->b.b.delete_rasterizer_state = si_delete_rs_state; 2968 2969 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state; 2970 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state; 2971 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state; 2972 2973 for (i = 0; i < 8; i++) { 2974 sctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(sctx, true, true, i); 2975 sctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(sctx, true, false, i); 2976 sctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(sctx, false, true, i); 2977 } 2978 sctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(sctx, false, false, 0); 2979 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE); 2980 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS); 2981 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR); 2982 2983 sctx->b.b.set_clip_state = si_set_clip_state; 2984 sctx->b.b.set_scissor_states = si_set_scissor_states; 2985 sctx->b.b.set_viewport_states = si_set_viewport_states; 2986 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref; 2987 2988 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state; 2989 sctx->b.b.get_sample_position = cayman_get_sample_position; 2990 2991 sctx->b.b.create_vs_state = si_create_vs_state; 2992 sctx->b.b.create_fs_state = si_create_fs_state; 2993 sctx->b.b.bind_vs_state = si_bind_vs_shader; 2994 sctx->b.b.bind_fs_state = si_bind_ps_shader; 2995 sctx->b.b.delete_vs_state = si_delete_vs_shader; 2996 sctx->b.b.delete_fs_state = si_delete_ps_shader; 2997#if HAVE_LLVM >= 0x0305 2998 sctx->b.b.create_gs_state = si_create_gs_state; 2999 sctx->b.b.bind_gs_state = si_bind_gs_shader; 3000 sctx->b.b.delete_gs_state = si_delete_gs_shader; 3001#endif 3002 3003 sctx->b.b.create_sampler_state = si_create_sampler_state; 3004 sctx->b.b.bind_sampler_states = si_bind_sampler_states; 3005 sctx->b.b.delete_sampler_state = si_delete_sampler_state; 3006 3007 sctx->b.b.create_sampler_view = si_create_sampler_view; 3008 sctx->b.b.set_sampler_views = si_set_sampler_views; 3009 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy; 3010 3011 sctx->b.b.set_sample_mask = si_set_sample_mask; 3012 3013 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements; 3014 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements; 3015 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element; 3016 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers; 3017 sctx->b.b.set_index_buffer = si_set_index_buffer; 3018 3019 sctx->b.b.texture_barrier = si_texture_barrier; 3020 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple; 3021 sctx->b.dma_copy = si_dma_copy; 3022 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state; 3023 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space; 3024 3025 sctx->b.b.draw_vbo = si_draw_vbo; 3026} 3027 3028void si_init_config(struct si_context *sctx) 3029{ 3030 struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); 3031 3032 if (pm4 == NULL) 3033 return; 3034 3035 si_cmd_context_control(pm4); 3036 3037 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0); 3038 3039 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0); 3040 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0); 3041 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0); 3042 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0); 3043 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0); 3044 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0); 3045 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0); 3046 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0); 3047 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0); 3048 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0); 3049 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0); 3050 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0); 3051 3052 /* FIXME calculate these values somehow ??? */ 3053 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80); 3054 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40); 3055 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2); 3056 3057 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0); 3058 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); 3059 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0); 3060 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); 3061 3062 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0); 3063 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0); 3064 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0); 3065 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0); 3066 3067 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0); 3068 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); 3069 if (sctx->b.chip_class == SI) { 3070 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, 3071 S_028AA8_SWITCH_ON_EOP(1) | 3072 S_028AA8_PARTIAL_VS_WAVE_ON(1) | 3073 S_028AA8_PRIMGROUP_SIZE(63)); 3074 } 3075 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000); 3076 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); 3077 if (sctx->b.chip_class < CIK) 3078 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | 3079 S_008A14_CLIP_VTX_REORDER_ENA(1)); 3080 3081 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210); 3082 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98); 3083 3084 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0); 3085 3086 if (sctx->b.chip_class >= CIK) { 3087 switch (sctx->screen->b.family) { 3088 case CHIP_BONAIRE: 3089 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012); 3090 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000); 3091 break; 3092 case CHIP_HAWAII: 3093 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a); 3094 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e); 3095 break; 3096 case CHIP_KAVERI: 3097 /* XXX todo */ 3098 case CHIP_KABINI: 3099 /* XXX todo */ 3100 default: 3101 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); 3102 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000); 3103 break; 3104 } 3105 } else { 3106 switch (sctx->screen->b.family) { 3107 case CHIP_TAHITI: 3108 case CHIP_PITCAIRN: 3109 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a); 3110 break; 3111 case CHIP_VERDE: 3112 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a); 3113 break; 3114 case CHIP_OLAND: 3115 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082); 3116 break; 3117 case CHIP_HAINAN: 3118 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); 3119 break; 3120 default: 3121 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); 3122 break; 3123 } 3124 } 3125 3126 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); 3127 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1)); 3128 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, 3129 S_028244_BR_X(16384) | S_028244_BR_Y(16384)); 3130 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0); 3131 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, 3132 S_028034_BR_X(16384) | S_028034_BR_Y(16384)); 3133 3134 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); 3135 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 3136 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000); 3137 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000); 3138 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F); 3139 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000); 3140 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000); 3141 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000); 3142 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000); 3143 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000); 3144 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000); 3145 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000); 3146 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000); 3147 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000); 3148 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); 3149 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); 3150 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); 3151 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 3152 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 3153 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE)); 3154 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); 3155 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); 3156 3157 if (sctx->b.chip_class >= CIK) { 3158 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff)); 3159 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0)); 3160 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff)); 3161 } 3162 3163 si_pm4_set_state(sctx, init, pm4); 3164} 3165