si_state.c revision c408f0c5c4b07eac4bc8759bb8e6ab20f527ded0
1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Christian König <christian.koenig@amd.com> 25 */ 26 27#include "util/u_memory.h" 28#include "util/u_framebuffer.h" 29#include "util/u_blitter.h" 30#include "util/u_helpers.h" 31#include "util/u_math.h" 32#include "util/u_pack_color.h" 33#include "tgsi/tgsi_parse.h" 34#include "radeonsi_pipe.h" 35#include "radeonsi_shader.h" 36#include "si_state.h" 37#include "sid.h" 38 39/* 40 * inferred framebuffer and blender state 41 */ 42static void si_update_fb_blend_state(struct r600_context *rctx) 43{ 44 struct si_pm4_state *pm4; 45 struct si_state_blend *blend = rctx->queued.named.blend; 46 uint32_t mask; 47 48 if (blend == NULL) 49 return; 50 51 pm4 = CALLOC_STRUCT(si_pm4_state); 52 if (pm4 == NULL) 53 return; 54 55 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1; 56 mask &= blend->cb_target_mask; 57 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask); 58 59 si_pm4_set_state(rctx, fb_blend, pm4); 60} 61 62/* 63 * Blender functions 64 */ 65 66static uint32_t si_translate_blend_function(int blend_func) 67{ 68 switch (blend_func) { 69 case PIPE_BLEND_ADD: 70 return V_028780_COMB_DST_PLUS_SRC; 71 case PIPE_BLEND_SUBTRACT: 72 return V_028780_COMB_SRC_MINUS_DST; 73 case PIPE_BLEND_REVERSE_SUBTRACT: 74 return V_028780_COMB_DST_MINUS_SRC; 75 case PIPE_BLEND_MIN: 76 return V_028780_COMB_MIN_DST_SRC; 77 case PIPE_BLEND_MAX: 78 return V_028780_COMB_MAX_DST_SRC; 79 default: 80 R600_ERR("Unknown blend function %d\n", blend_func); 81 assert(0); 82 break; 83 } 84 return 0; 85} 86 87static uint32_t si_translate_blend_factor(int blend_fact) 88{ 89 switch (blend_fact) { 90 case PIPE_BLENDFACTOR_ONE: 91 return V_028780_BLEND_ONE; 92 case PIPE_BLENDFACTOR_SRC_COLOR: 93 return V_028780_BLEND_SRC_COLOR; 94 case PIPE_BLENDFACTOR_SRC_ALPHA: 95 return V_028780_BLEND_SRC_ALPHA; 96 case PIPE_BLENDFACTOR_DST_ALPHA: 97 return V_028780_BLEND_DST_ALPHA; 98 case PIPE_BLENDFACTOR_DST_COLOR: 99 return V_028780_BLEND_DST_COLOR; 100 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 101 return V_028780_BLEND_SRC_ALPHA_SATURATE; 102 case PIPE_BLENDFACTOR_CONST_COLOR: 103 return V_028780_BLEND_CONSTANT_COLOR; 104 case PIPE_BLENDFACTOR_CONST_ALPHA: 105 return V_028780_BLEND_CONSTANT_ALPHA; 106 case PIPE_BLENDFACTOR_ZERO: 107 return V_028780_BLEND_ZERO; 108 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 109 return V_028780_BLEND_ONE_MINUS_SRC_COLOR; 110 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 111 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; 112 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 113 return V_028780_BLEND_ONE_MINUS_DST_ALPHA; 114 case PIPE_BLENDFACTOR_INV_DST_COLOR: 115 return V_028780_BLEND_ONE_MINUS_DST_COLOR; 116 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 117 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; 118 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 119 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; 120 case PIPE_BLENDFACTOR_SRC1_COLOR: 121 return V_028780_BLEND_SRC1_COLOR; 122 case PIPE_BLENDFACTOR_SRC1_ALPHA: 123 return V_028780_BLEND_SRC1_ALPHA; 124 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 125 return V_028780_BLEND_INV_SRC1_COLOR; 126 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 127 return V_028780_BLEND_INV_SRC1_ALPHA; 128 default: 129 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 130 assert(0); 131 break; 132 } 133 return 0; 134} 135 136static void *si_create_blend_state(struct pipe_context *ctx, 137 const struct pipe_blend_state *state) 138{ 139 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend); 140 struct si_pm4_state *pm4 = &blend->pm4; 141 142 uint32_t color_control; 143 144 if (blend == NULL) 145 return NULL; 146 147 color_control = S_028808_MODE(V_028808_CB_NORMAL); 148 if (state->logicop_enable) { 149 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4)); 150 } else { 151 color_control |= S_028808_ROP3(0xcc); 152 } 153 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); 154 155 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0); 156 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0); 157 158 blend->cb_target_mask = 0; 159 for (int i = 0; i < 8; i++) { 160 /* state->rt entries > 0 only written if independent blending */ 161 const int j = state->independent_blend_enable ? i : 0; 162 163 unsigned eqRGB = state->rt[j].rgb_func; 164 unsigned srcRGB = state->rt[j].rgb_src_factor; 165 unsigned dstRGB = state->rt[j].rgb_dst_factor; 166 unsigned eqA = state->rt[j].alpha_func; 167 unsigned srcA = state->rt[j].alpha_src_factor; 168 unsigned dstA = state->rt[j].alpha_dst_factor; 169 170 unsigned blend_cntl = 0; 171 172 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 173 blend->cb_target_mask |= state->rt[j].colormask << (4 * i); 174 175 if (!state->rt[j].blend_enable) { 176 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 177 continue; 178 } 179 180 blend_cntl |= S_028780_ENABLE(1); 181 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); 182 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); 183 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); 184 185 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 186 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); 187 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); 188 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); 189 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); 190 } 191 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 192 } 193 194 return blend; 195} 196 197static void si_bind_blend_state(struct pipe_context *ctx, void *state) 198{ 199 struct r600_context *rctx = (struct r600_context *)ctx; 200 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state); 201 si_update_fb_blend_state(rctx); 202} 203 204static void si_delete_blend_state(struct pipe_context *ctx, void *state) 205{ 206 struct r600_context *rctx = (struct r600_context *)ctx; 207 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state); 208} 209 210static void si_set_blend_color(struct pipe_context *ctx, 211 const struct pipe_blend_color *state) 212{ 213 struct r600_context *rctx = (struct r600_context *)ctx; 214 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 215 216 if (pm4 == NULL) 217 return; 218 219 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0])); 220 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1])); 221 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2])); 222 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3])); 223 224 si_pm4_set_state(rctx, blend_color, pm4); 225} 226 227/* 228 * Clipping, scissors and viewport 229 */ 230 231static void si_set_clip_state(struct pipe_context *ctx, 232 const struct pipe_clip_state *state) 233{ 234 struct r600_context *rctx = (struct r600_context *)ctx; 235 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 236 237 if (pm4 == NULL) 238 return; 239 240 for (int i = 0; i < 6; i++) { 241 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16, 242 fui(state->ucp[i][0])); 243 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16, 244 fui(state->ucp[i][1])); 245 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16, 246 fui(state->ucp[i][2])); 247 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16, 248 fui(state->ucp[i][3])); 249 } 250 251 si_pm4_set_state(rctx, clip, pm4); 252} 253 254static void si_set_scissor_state(struct pipe_context *ctx, 255 const struct pipe_scissor_state *state) 256{ 257 struct r600_context *rctx = (struct r600_context *)ctx; 258 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 259 uint32_t tl, br; 260 261 if (pm4 == NULL) 262 return; 263 264 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny); 265 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 266 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl); 267 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br); 268 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl); 269 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br); 270 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl); 271 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br); 272 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl); 273 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br); 274 275 si_pm4_set_state(rctx, scissor, pm4); 276} 277 278static void si_set_viewport_state(struct pipe_context *ctx, 279 const struct pipe_viewport_state *state) 280{ 281 struct r600_context *rctx = (struct r600_context *)ctx; 282 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport); 283 struct si_pm4_state *pm4 = &viewport->pm4; 284 285 if (viewport == NULL) 286 return; 287 288 viewport->viewport = *state; 289 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000); 290 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000); 291 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0])); 292 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0])); 293 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1])); 294 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1])); 295 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2])); 296 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2])); 297 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F); 298 299 si_pm4_set_state(rctx, viewport, viewport); 300} 301 302/* 303 * inferred state between framebuffer and rasterizer 304 */ 305static void si_update_fb_rs_state(struct r600_context *rctx) 306{ 307 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer; 308 struct si_pm4_state *pm4; 309 unsigned offset_db_fmt_cntl = 0, depth; 310 float offset_units; 311 312 if (!rs || !rctx->framebuffer.zsbuf) 313 return; 314 315 offset_units = rctx->queued.named.rasterizer->offset_units; 316 switch (rctx->framebuffer.zsbuf->texture->format) { 317 case PIPE_FORMAT_Z24X8_UNORM: 318 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 319 depth = -24; 320 offset_units *= 2.0f; 321 break; 322 case PIPE_FORMAT_Z32_FLOAT: 323 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 324 depth = -23; 325 offset_units *= 1.0f; 326 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 327 break; 328 case PIPE_FORMAT_Z16_UNORM: 329 depth = -16; 330 offset_units *= 4.0f; 331 break; 332 default: 333 return; 334 } 335 336 pm4 = CALLOC_STRUCT(si_pm4_state); 337 /* FIXME some of those reg can be computed with cso */ 338 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 339 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 340 fui(rctx->queued.named.rasterizer->offset_scale)); 341 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units)); 342 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 343 fui(rctx->queued.named.rasterizer->offset_scale)); 344 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units)); 345 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl); 346 347 si_pm4_set_state(rctx, fb_rs, pm4); 348} 349 350/* 351 * Rasterizer 352 */ 353 354static uint32_t si_translate_fill(uint32_t func) 355{ 356 switch(func) { 357 case PIPE_POLYGON_MODE_FILL: 358 return V_028814_X_DRAW_TRIANGLES; 359 case PIPE_POLYGON_MODE_LINE: 360 return V_028814_X_DRAW_LINES; 361 case PIPE_POLYGON_MODE_POINT: 362 return V_028814_X_DRAW_POINTS; 363 default: 364 assert(0); 365 return V_028814_X_DRAW_POINTS; 366 } 367} 368 369static void *si_create_rs_state(struct pipe_context *ctx, 370 const struct pipe_rasterizer_state *state) 371{ 372 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer); 373 struct si_pm4_state *pm4 = &rs->pm4; 374 unsigned tmp; 375 unsigned prov_vtx = 1, polygon_dual_mode; 376 unsigned clip_rule; 377 float psize_min, psize_max; 378 379 if (rs == NULL) { 380 return NULL; 381 } 382 383 rs->two_side = state->light_twoside; 384 385 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 386 state->fill_back != PIPE_POLYGON_MODE_FILL); 387 388 if (state->flatshade_first) 389 prov_vtx = 0; 390 391 rs->flatshade = state->flatshade; 392 rs->sprite_coord_enable = state->sprite_coord_enable; 393 rs->pa_sc_line_stipple = state->line_stipple_enable ? 394 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 395 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 396 rs->pa_su_sc_mode_cntl = 397 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 398 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 399 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 400 S_028814_FACE(!state->front_ccw) | 401 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 402 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 403 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 404 S_028814_POLY_MODE(polygon_dual_mode) | 405 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | 406 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)); 407 rs->pa_cl_clip_cntl = 408 S_028810_PS_UCP_MODE(3) | 409 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 410 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 411 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 412 rs->pa_cl_vs_out_cntl = 413 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) | 414 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex); 415 416 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 417 418 /* offset */ 419 rs->offset_units = state->offset_units; 420 rs->offset_scale = state->offset_scale * 12.0f; 421 422 /* XXX: Flat shading hangs the GPU */ 423 tmp = S_0286D4_FLAT_SHADE_ENA(0); 424 if (state->sprite_coord_enable) { 425 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 426 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | 427 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | 428 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | 429 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1); 430 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 431 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 432 } 433 } 434 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp); 435 436 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000); 437 /* point size 12.4 fixed point */ 438 tmp = (unsigned)(state->point_size * 8.0); 439 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 440 441 if (state->point_size_per_vertex) { 442 psize_min = util_get_min_point_size(state); 443 psize_max = 8192; 444 } else { 445 /* Force the point size to be as if the vertex output was disabled. */ 446 psize_min = state->point_size; 447 psize_max = state->point_size; 448 } 449 /* Divide by two, because 0.5 = 1 pixel. */ 450 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX, 451 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | 452 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); 453 454 tmp = (unsigned)state->line_width * 8; 455 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); 456 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0, 457 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable)); 458 459 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400); 460 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL, 461 S_028BE4_PIX_CENTER(state->gl_rasterization_rules)); 462 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000); 463 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000); 464 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000); 465 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000); 466 467 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 468 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule); 469 470 return rs; 471} 472 473static void si_bind_rs_state(struct pipe_context *ctx, void *state) 474{ 475 struct r600_context *rctx = (struct r600_context *)ctx; 476 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state; 477 478 if (state == NULL) 479 return; 480 481 // TODO 482 rctx->sprite_coord_enable = rs->sprite_coord_enable; 483 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; 484 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl; 485 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl; 486 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl; 487 488 si_pm4_bind_state(rctx, rasterizer, rs); 489 si_update_fb_rs_state(rctx); 490} 491 492static void si_delete_rs_state(struct pipe_context *ctx, void *state) 493{ 494 struct r600_context *rctx = (struct r600_context *)ctx; 495 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state); 496} 497 498/* 499 * infeered state between dsa and stencil ref 500 */ 501static void si_update_dsa_stencil_ref(struct r600_context *rctx) 502{ 503 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 504 struct pipe_stencil_ref *ref = &rctx->stencil_ref; 505 struct si_state_dsa *dsa = rctx->queued.named.dsa; 506 507 if (pm4 == NULL) 508 return; 509 510 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK, 511 S_028430_STENCILTESTVAL(ref->ref_value[0]) | 512 S_028430_STENCILMASK(dsa->valuemask[0]) | 513 S_028430_STENCILWRITEMASK(dsa->writemask[0]) | 514 S_028430_STENCILOPVAL(1)); 515 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF, 516 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) | 517 S_028434_STENCILMASK_BF(dsa->valuemask[1]) | 518 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) | 519 S_028434_STENCILOPVAL_BF(1)); 520 521 si_pm4_set_state(rctx, dsa_stencil_ref, pm4); 522} 523 524static void si_set_pipe_stencil_ref(struct pipe_context *ctx, 525 const struct pipe_stencil_ref *state) 526{ 527 struct r600_context *rctx = (struct r600_context *)ctx; 528 rctx->stencil_ref = *state; 529 si_update_dsa_stencil_ref(rctx); 530} 531 532 533/* 534 * DSA 535 */ 536 537static uint32_t si_translate_stencil_op(int s_op) 538{ 539 switch (s_op) { 540 case PIPE_STENCIL_OP_KEEP: 541 return V_02842C_STENCIL_KEEP; 542 case PIPE_STENCIL_OP_ZERO: 543 return V_02842C_STENCIL_ZERO; 544 case PIPE_STENCIL_OP_REPLACE: 545 return V_02842C_STENCIL_REPLACE_TEST; 546 case PIPE_STENCIL_OP_INCR: 547 return V_02842C_STENCIL_ADD_CLAMP; 548 case PIPE_STENCIL_OP_DECR: 549 return V_02842C_STENCIL_SUB_CLAMP; 550 case PIPE_STENCIL_OP_INCR_WRAP: 551 return V_02842C_STENCIL_ADD_WRAP; 552 case PIPE_STENCIL_OP_DECR_WRAP: 553 return V_02842C_STENCIL_SUB_WRAP; 554 case PIPE_STENCIL_OP_INVERT: 555 return V_02842C_STENCIL_INVERT; 556 default: 557 R600_ERR("Unknown stencil op %d", s_op); 558 assert(0); 559 break; 560 } 561 return 0; 562} 563 564static void *si_create_dsa_state(struct pipe_context *ctx, 565 const struct pipe_depth_stencil_alpha_state *state) 566{ 567 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa); 568 struct si_pm4_state *pm4 = &dsa->pm4; 569 unsigned db_depth_control; 570 unsigned db_render_override, db_render_control; 571 uint32_t db_stencil_control = 0; 572 573 if (dsa == NULL) { 574 return NULL; 575 } 576 577 dsa->valuemask[0] = state->stencil[0].valuemask; 578 dsa->valuemask[1] = state->stencil[1].valuemask; 579 dsa->writemask[0] = state->stencil[0].writemask; 580 dsa->writemask[1] = state->stencil[1].writemask; 581 582 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 583 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 584 S_028800_ZFUNC(state->depth.func); 585 586 /* stencil */ 587 if (state->stencil[0].enabled) { 588 db_depth_control |= S_028800_STENCIL_ENABLE(1); 589 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); 590 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op)); 591 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op)); 592 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op)); 593 594 if (state->stencil[1].enabled) { 595 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 596 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); 597 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op)); 598 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op)); 599 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op)); 600 } 601 } 602 603 /* alpha */ 604 if (state->alpha.enabled) { 605 dsa->alpha_func = state->alpha.func; 606 dsa->alpha_ref = state->alpha.ref_value; 607 } else { 608 dsa->alpha_func = PIPE_FUNC_ALWAYS; 609 } 610 611 /* misc */ 612 db_render_control = 0; 613 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) | 614 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 615 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); 616 /* TODO db_render_override depends on query */ 617 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000); 618 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000); 619 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000); 620 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000); 621 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control); 622 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); 623 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control); 624 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override); 625 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); 626 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); 627 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); 628 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); 629 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00); 630 dsa->db_render_override = db_render_override; 631 632 return dsa; 633} 634 635static void si_bind_dsa_state(struct pipe_context *ctx, void *state) 636{ 637 struct r600_context *rctx = (struct r600_context *)ctx; 638 struct si_state_dsa *dsa = state; 639 640 if (state == NULL) 641 return; 642 643 si_pm4_bind_state(rctx, dsa, dsa); 644 si_update_dsa_stencil_ref(rctx); 645} 646 647static void si_delete_dsa_state(struct pipe_context *ctx, void *state) 648{ 649 struct r600_context *rctx = (struct r600_context *)ctx; 650 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state); 651} 652 653static void *si_create_db_flush_dsa(struct r600_context *rctx) 654{ 655 struct pipe_depth_stencil_alpha_state dsa; 656 struct si_state_dsa *state; 657 658 memset(&dsa, 0, sizeof(dsa)); 659 660 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 661 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, 662 S_028000_DEPTH_COPY(1) | 663 S_028000_STENCIL_COPY(1) | 664 S_028000_COPY_CENTROID(1)); 665 return state; 666} 667 668/* 669 * format translation 670 */ 671static uint32_t si_translate_colorformat(enum pipe_format format) 672{ 673 switch (format) { 674 /* 8-bit buffers. */ 675 case PIPE_FORMAT_A8_UNORM: 676 case PIPE_FORMAT_A8_SNORM: 677 case PIPE_FORMAT_A8_UINT: 678 case PIPE_FORMAT_A8_SINT: 679 case PIPE_FORMAT_I8_UNORM: 680 case PIPE_FORMAT_I8_SNORM: 681 case PIPE_FORMAT_I8_UINT: 682 case PIPE_FORMAT_I8_SINT: 683 case PIPE_FORMAT_L8_UNORM: 684 case PIPE_FORMAT_L8_SNORM: 685 case PIPE_FORMAT_L8_UINT: 686 case PIPE_FORMAT_L8_SINT: 687 case PIPE_FORMAT_L8_SRGB: 688 case PIPE_FORMAT_R8_UNORM: 689 case PIPE_FORMAT_R8_SNORM: 690 case PIPE_FORMAT_R8_UINT: 691 case PIPE_FORMAT_R8_SINT: 692 return V_028C70_COLOR_8; 693 694 /* 16-bit buffers. */ 695 case PIPE_FORMAT_B5G6R5_UNORM: 696 return V_028C70_COLOR_5_6_5; 697 698 case PIPE_FORMAT_B5G5R5A1_UNORM: 699 case PIPE_FORMAT_B5G5R5X1_UNORM: 700 return V_028C70_COLOR_1_5_5_5; 701 702 case PIPE_FORMAT_B4G4R4A4_UNORM: 703 case PIPE_FORMAT_B4G4R4X4_UNORM: 704 return V_028C70_COLOR_4_4_4_4; 705 706 case PIPE_FORMAT_L8A8_UNORM: 707 case PIPE_FORMAT_L8A8_SNORM: 708 case PIPE_FORMAT_L8A8_UINT: 709 case PIPE_FORMAT_L8A8_SINT: 710 case PIPE_FORMAT_L8A8_SRGB: 711 case PIPE_FORMAT_R8G8_SNORM: 712 case PIPE_FORMAT_R8G8_UNORM: 713 case PIPE_FORMAT_R8G8_UINT: 714 case PIPE_FORMAT_R8G8_SINT: 715 return V_028C70_COLOR_8_8; 716 717 case PIPE_FORMAT_Z16_UNORM: 718 case PIPE_FORMAT_R16_UNORM: 719 case PIPE_FORMAT_R16_SNORM: 720 case PIPE_FORMAT_R16_UINT: 721 case PIPE_FORMAT_R16_SINT: 722 case PIPE_FORMAT_R16_FLOAT: 723 case PIPE_FORMAT_L16_UNORM: 724 case PIPE_FORMAT_L16_SNORM: 725 case PIPE_FORMAT_L16_FLOAT: 726 case PIPE_FORMAT_I16_UNORM: 727 case PIPE_FORMAT_I16_SNORM: 728 case PIPE_FORMAT_I16_FLOAT: 729 case PIPE_FORMAT_A16_UNORM: 730 case PIPE_FORMAT_A16_SNORM: 731 case PIPE_FORMAT_A16_FLOAT: 732 return V_028C70_COLOR_16; 733 734 /* 32-bit buffers. */ 735 case PIPE_FORMAT_A8B8G8R8_SRGB: 736 case PIPE_FORMAT_A8B8G8R8_UNORM: 737 case PIPE_FORMAT_A8R8G8B8_UNORM: 738 case PIPE_FORMAT_B8G8R8A8_SRGB: 739 case PIPE_FORMAT_B8G8R8A8_UNORM: 740 case PIPE_FORMAT_B8G8R8X8_UNORM: 741 case PIPE_FORMAT_R8G8B8A8_SNORM: 742 case PIPE_FORMAT_R8G8B8A8_UNORM: 743 case PIPE_FORMAT_R8G8B8X8_UNORM: 744 case PIPE_FORMAT_R8SG8SB8UX8U_NORM: 745 case PIPE_FORMAT_X8B8G8R8_UNORM: 746 case PIPE_FORMAT_X8R8G8B8_UNORM: 747 case PIPE_FORMAT_R8G8B8_UNORM: 748 case PIPE_FORMAT_R8G8B8A8_SSCALED: 749 case PIPE_FORMAT_R8G8B8A8_USCALED: 750 case PIPE_FORMAT_R8G8B8A8_SINT: 751 case PIPE_FORMAT_R8G8B8A8_UINT: 752 return V_028C70_COLOR_8_8_8_8; 753 754 case PIPE_FORMAT_R10G10B10A2_UNORM: 755 case PIPE_FORMAT_R10G10B10X2_SNORM: 756 case PIPE_FORMAT_B10G10R10A2_UNORM: 757 case PIPE_FORMAT_B10G10R10A2_UINT: 758 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 759 return V_028C70_COLOR_2_10_10_10; 760 761 case PIPE_FORMAT_Z24X8_UNORM: 762 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 763 return V_028C70_COLOR_8_24; 764 765 case PIPE_FORMAT_X8Z24_UNORM: 766 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 767 return V_028C70_COLOR_24_8; 768 769 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 770 return V_028C70_COLOR_X24_8_32_FLOAT; 771 772 case PIPE_FORMAT_I32_FLOAT: 773 case PIPE_FORMAT_L32_FLOAT: 774 case PIPE_FORMAT_R32_FLOAT: 775 case PIPE_FORMAT_A32_FLOAT: 776 case PIPE_FORMAT_Z32_FLOAT: 777 return V_028C70_COLOR_32; 778 779 case PIPE_FORMAT_L16A16_UNORM: 780 case PIPE_FORMAT_L16A16_SNORM: 781 case PIPE_FORMAT_L16A16_FLOAT: 782 case PIPE_FORMAT_R16G16_SSCALED: 783 case PIPE_FORMAT_R16G16_UNORM: 784 case PIPE_FORMAT_R16G16_SNORM: 785 case PIPE_FORMAT_R16G16_UINT: 786 case PIPE_FORMAT_R16G16_SINT: 787 case PIPE_FORMAT_R16G16_FLOAT: 788 return V_028C70_COLOR_16_16; 789 790 case PIPE_FORMAT_R11G11B10_FLOAT: 791 return V_028C70_COLOR_10_11_11; 792 793 /* 64-bit buffers. */ 794 case PIPE_FORMAT_R16G16B16_USCALED: 795 case PIPE_FORMAT_R16G16B16_SSCALED: 796 case PIPE_FORMAT_R16G16B16A16_UINT: 797 case PIPE_FORMAT_R16G16B16A16_SINT: 798 case PIPE_FORMAT_R16G16B16A16_USCALED: 799 case PIPE_FORMAT_R16G16B16A16_SSCALED: 800 case PIPE_FORMAT_R16G16B16A16_UNORM: 801 case PIPE_FORMAT_R16G16B16A16_SNORM: 802 case PIPE_FORMAT_R16G16B16_FLOAT: 803 case PIPE_FORMAT_R16G16B16A16_FLOAT: 804 return V_028C70_COLOR_16_16_16_16; 805 806 case PIPE_FORMAT_L32A32_FLOAT: 807 case PIPE_FORMAT_R32G32_FLOAT: 808 case PIPE_FORMAT_R32G32_USCALED: 809 case PIPE_FORMAT_R32G32_SSCALED: 810 case PIPE_FORMAT_R32G32_SINT: 811 case PIPE_FORMAT_R32G32_UINT: 812 return V_028C70_COLOR_32_32; 813 814 /* 128-bit buffers. */ 815 case PIPE_FORMAT_R32G32B32A32_SNORM: 816 case PIPE_FORMAT_R32G32B32A32_UNORM: 817 case PIPE_FORMAT_R32G32B32A32_SSCALED: 818 case PIPE_FORMAT_R32G32B32A32_USCALED: 819 case PIPE_FORMAT_R32G32B32A32_SINT: 820 case PIPE_FORMAT_R32G32B32A32_UINT: 821 case PIPE_FORMAT_R32G32B32A32_FLOAT: 822 return V_028C70_COLOR_32_32_32_32; 823 824 /* YUV buffers. */ 825 case PIPE_FORMAT_UYVY: 826 case PIPE_FORMAT_YUYV: 827 /* 96-bit buffers. */ 828 case PIPE_FORMAT_R32G32B32_FLOAT: 829 /* 8-bit buffers. */ 830 case PIPE_FORMAT_L4A4_UNORM: 831 case PIPE_FORMAT_R4A4_UNORM: 832 case PIPE_FORMAT_A4R4_UNORM: 833 default: 834 return V_028C70_COLOR_INVALID; /* Unsupported. */ 835 } 836} 837 838static uint32_t si_translate_colorswap(enum pipe_format format) 839{ 840 switch (format) { 841 /* 8-bit buffers. */ 842 case PIPE_FORMAT_L4A4_UNORM: 843 case PIPE_FORMAT_A4R4_UNORM: 844 return V_028C70_SWAP_ALT; 845 846 case PIPE_FORMAT_A8_UNORM: 847 case PIPE_FORMAT_A8_SNORM: 848 case PIPE_FORMAT_A8_UINT: 849 case PIPE_FORMAT_A8_SINT: 850 case PIPE_FORMAT_R4A4_UNORM: 851 return V_028C70_SWAP_ALT_REV; 852 case PIPE_FORMAT_I8_UNORM: 853 case PIPE_FORMAT_I8_SNORM: 854 case PIPE_FORMAT_L8_UNORM: 855 case PIPE_FORMAT_L8_SNORM: 856 case PIPE_FORMAT_I8_UINT: 857 case PIPE_FORMAT_I8_SINT: 858 case PIPE_FORMAT_L8_UINT: 859 case PIPE_FORMAT_L8_SINT: 860 case PIPE_FORMAT_L8_SRGB: 861 case PIPE_FORMAT_R8_UNORM: 862 case PIPE_FORMAT_R8_SNORM: 863 case PIPE_FORMAT_R8_UINT: 864 case PIPE_FORMAT_R8_SINT: 865 return V_028C70_SWAP_STD; 866 867 /* 16-bit buffers. */ 868 case PIPE_FORMAT_B5G6R5_UNORM: 869 return V_028C70_SWAP_STD_REV; 870 871 case PIPE_FORMAT_B5G5R5A1_UNORM: 872 case PIPE_FORMAT_B5G5R5X1_UNORM: 873 return V_028C70_SWAP_ALT; 874 875 case PIPE_FORMAT_B4G4R4A4_UNORM: 876 case PIPE_FORMAT_B4G4R4X4_UNORM: 877 return V_028C70_SWAP_ALT; 878 879 case PIPE_FORMAT_Z16_UNORM: 880 return V_028C70_SWAP_STD; 881 882 case PIPE_FORMAT_L8A8_UNORM: 883 case PIPE_FORMAT_L8A8_SNORM: 884 case PIPE_FORMAT_L8A8_UINT: 885 case PIPE_FORMAT_L8A8_SINT: 886 case PIPE_FORMAT_L8A8_SRGB: 887 return V_028C70_SWAP_ALT; 888 case PIPE_FORMAT_R8G8_SNORM: 889 case PIPE_FORMAT_R8G8_UNORM: 890 case PIPE_FORMAT_R8G8_UINT: 891 case PIPE_FORMAT_R8G8_SINT: 892 return V_028C70_SWAP_STD; 893 894 case PIPE_FORMAT_I16_UNORM: 895 case PIPE_FORMAT_I16_SNORM: 896 case PIPE_FORMAT_I16_FLOAT: 897 case PIPE_FORMAT_L16_UNORM: 898 case PIPE_FORMAT_L16_SNORM: 899 case PIPE_FORMAT_L16_FLOAT: 900 case PIPE_FORMAT_R16_UNORM: 901 case PIPE_FORMAT_R16_SNORM: 902 case PIPE_FORMAT_R16_UINT: 903 case PIPE_FORMAT_R16_SINT: 904 case PIPE_FORMAT_R16_FLOAT: 905 return V_028C70_SWAP_STD; 906 907 case PIPE_FORMAT_A16_UNORM: 908 case PIPE_FORMAT_A16_SNORM: 909 case PIPE_FORMAT_A16_FLOAT: 910 return V_028C70_SWAP_ALT_REV; 911 912 /* 32-bit buffers. */ 913 case PIPE_FORMAT_A8B8G8R8_SRGB: 914 return V_028C70_SWAP_STD_REV; 915 case PIPE_FORMAT_B8G8R8A8_SRGB: 916 return V_028C70_SWAP_ALT; 917 918 case PIPE_FORMAT_B8G8R8A8_UNORM: 919 case PIPE_FORMAT_B8G8R8X8_UNORM: 920 return V_028C70_SWAP_ALT; 921 922 case PIPE_FORMAT_A8R8G8B8_UNORM: 923 case PIPE_FORMAT_X8R8G8B8_UNORM: 924 return V_028C70_SWAP_ALT_REV; 925 case PIPE_FORMAT_R8G8B8A8_SNORM: 926 case PIPE_FORMAT_R8G8B8A8_UNORM: 927 case PIPE_FORMAT_R8G8B8A8_SSCALED: 928 case PIPE_FORMAT_R8G8B8A8_USCALED: 929 case PIPE_FORMAT_R8G8B8A8_SINT: 930 case PIPE_FORMAT_R8G8B8A8_UINT: 931 case PIPE_FORMAT_R8G8B8X8_UNORM: 932 return V_028C70_SWAP_STD; 933 934 case PIPE_FORMAT_A8B8G8R8_UNORM: 935 case PIPE_FORMAT_X8B8G8R8_UNORM: 936 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */ 937 return V_028C70_SWAP_STD_REV; 938 939 case PIPE_FORMAT_Z24X8_UNORM: 940 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 941 return V_028C70_SWAP_STD; 942 943 case PIPE_FORMAT_X8Z24_UNORM: 944 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 945 return V_028C70_SWAP_STD; 946 947 case PIPE_FORMAT_R10G10B10A2_UNORM: 948 case PIPE_FORMAT_R10G10B10X2_SNORM: 949 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 950 return V_028C70_SWAP_STD; 951 952 case PIPE_FORMAT_B10G10R10A2_UNORM: 953 case PIPE_FORMAT_B10G10R10A2_UINT: 954 return V_028C70_SWAP_ALT; 955 956 case PIPE_FORMAT_R11G11B10_FLOAT: 957 case PIPE_FORMAT_I32_FLOAT: 958 case PIPE_FORMAT_L32_FLOAT: 959 case PIPE_FORMAT_R32_FLOAT: 960 case PIPE_FORMAT_R32_UINT: 961 case PIPE_FORMAT_R32_SINT: 962 case PIPE_FORMAT_Z32_FLOAT: 963 case PIPE_FORMAT_R16G16_FLOAT: 964 case PIPE_FORMAT_R16G16_UNORM: 965 case PIPE_FORMAT_R16G16_SNORM: 966 case PIPE_FORMAT_R16G16_UINT: 967 case PIPE_FORMAT_R16G16_SINT: 968 return V_028C70_SWAP_STD; 969 970 case PIPE_FORMAT_L16A16_UNORM: 971 case PIPE_FORMAT_L16A16_SNORM: 972 case PIPE_FORMAT_L16A16_FLOAT: 973 return V_028C70_SWAP_ALT; 974 975 case PIPE_FORMAT_A32_FLOAT: 976 return V_028C70_SWAP_ALT_REV; 977 978 /* 64-bit buffers. */ 979 case PIPE_FORMAT_R32G32_FLOAT: 980 case PIPE_FORMAT_R32G32_UINT: 981 case PIPE_FORMAT_R32G32_SINT: 982 case PIPE_FORMAT_R16G16B16A16_UNORM: 983 case PIPE_FORMAT_R16G16B16A16_SNORM: 984 case PIPE_FORMAT_R16G16B16A16_USCALED: 985 case PIPE_FORMAT_R16G16B16A16_SSCALED: 986 case PIPE_FORMAT_R16G16B16A16_UINT: 987 case PIPE_FORMAT_R16G16B16A16_SINT: 988 case PIPE_FORMAT_R16G16B16A16_FLOAT: 989 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 990 return V_028C70_SWAP_STD; 991 992 case PIPE_FORMAT_L32A32_FLOAT: 993 return V_028C70_SWAP_ALT; 994 995 /* 128-bit buffers. */ 996 case PIPE_FORMAT_R32G32B32A32_FLOAT: 997 case PIPE_FORMAT_R32G32B32A32_SNORM: 998 case PIPE_FORMAT_R32G32B32A32_UNORM: 999 case PIPE_FORMAT_R32G32B32A32_SSCALED: 1000 case PIPE_FORMAT_R32G32B32A32_USCALED: 1001 case PIPE_FORMAT_R32G32B32A32_SINT: 1002 case PIPE_FORMAT_R32G32B32A32_UINT: 1003 return V_028C70_SWAP_STD; 1004 default: 1005 R600_ERR("unsupported colorswap format %d\n", format); 1006 return ~0U; 1007 } 1008 return ~0U; 1009} 1010 1011static uint32_t si_colorformat_endian_swap(uint32_t colorformat) 1012{ 1013 if (R600_BIG_ENDIAN) { 1014 switch(colorformat) { 1015 /* 8-bit buffers. */ 1016 case V_028C70_COLOR_8: 1017 return V_028C70_ENDIAN_NONE; 1018 1019 /* 16-bit buffers. */ 1020 case V_028C70_COLOR_5_6_5: 1021 case V_028C70_COLOR_1_5_5_5: 1022 case V_028C70_COLOR_4_4_4_4: 1023 case V_028C70_COLOR_16: 1024 case V_028C70_COLOR_8_8: 1025 return V_028C70_ENDIAN_8IN16; 1026 1027 /* 32-bit buffers. */ 1028 case V_028C70_COLOR_8_8_8_8: 1029 case V_028C70_COLOR_2_10_10_10: 1030 case V_028C70_COLOR_8_24: 1031 case V_028C70_COLOR_24_8: 1032 case V_028C70_COLOR_16_16: 1033 return V_028C70_ENDIAN_8IN32; 1034 1035 /* 64-bit buffers. */ 1036 case V_028C70_COLOR_16_16_16_16: 1037 return V_028C70_ENDIAN_8IN16; 1038 1039 case V_028C70_COLOR_32_32: 1040 return V_028C70_ENDIAN_8IN32; 1041 1042 /* 128-bit buffers. */ 1043 case V_028C70_COLOR_32_32_32_32: 1044 return V_028C70_ENDIAN_8IN32; 1045 default: 1046 return V_028C70_ENDIAN_NONE; /* Unsupported. */ 1047 } 1048 } else { 1049 return V_028C70_ENDIAN_NONE; 1050 } 1051} 1052 1053/* Returns the size in bits of the widest component of a CB format */ 1054static unsigned si_colorformat_max_comp_size(uint32_t colorformat) 1055{ 1056 switch(colorformat) { 1057 case V_028C70_COLOR_4_4_4_4: 1058 return 4; 1059 1060 case V_028C70_COLOR_1_5_5_5: 1061 case V_028C70_COLOR_5_5_5_1: 1062 return 5; 1063 1064 case V_028C70_COLOR_5_6_5: 1065 return 6; 1066 1067 case V_028C70_COLOR_8: 1068 case V_028C70_COLOR_8_8: 1069 case V_028C70_COLOR_8_8_8_8: 1070 return 8; 1071 1072 case V_028C70_COLOR_10_10_10_2: 1073 case V_028C70_COLOR_2_10_10_10: 1074 return 10; 1075 1076 case V_028C70_COLOR_10_11_11: 1077 case V_028C70_COLOR_11_11_10: 1078 return 11; 1079 1080 case V_028C70_COLOR_16: 1081 case V_028C70_COLOR_16_16: 1082 case V_028C70_COLOR_16_16_16_16: 1083 return 16; 1084 1085 case V_028C70_COLOR_8_24: 1086 case V_028C70_COLOR_24_8: 1087 return 24; 1088 1089 case V_028C70_COLOR_32: 1090 case V_028C70_COLOR_32_32: 1091 case V_028C70_COLOR_32_32_32_32: 1092 case V_028C70_COLOR_X24_8_32_FLOAT: 1093 return 32; 1094 } 1095 1096 assert(!"Unknown maximum component size"); 1097 return 0; 1098} 1099 1100static uint32_t si_translate_dbformat(enum pipe_format format) 1101{ 1102 switch (format) { 1103 case PIPE_FORMAT_Z16_UNORM: 1104 return V_028040_Z_16; 1105 case PIPE_FORMAT_Z24X8_UNORM: 1106 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1107 return V_028040_Z_24; /* XXX no longer supported on SI */ 1108 case PIPE_FORMAT_Z32_FLOAT: 1109 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1110 return V_028040_Z_32_FLOAT; 1111 default: 1112 return V_028040_Z_INVALID; 1113 } 1114} 1115 1116/* 1117 * Texture translation 1118 */ 1119 1120static uint32_t si_translate_texformat(struct pipe_screen *screen, 1121 enum pipe_format format, 1122 const struct util_format_description *desc, 1123 int first_non_void) 1124{ 1125 boolean uniform = TRUE; 1126 int i; 1127 1128 /* Colorspace (return non-RGB formats directly). */ 1129 switch (desc->colorspace) { 1130 /* Depth stencil formats */ 1131 case UTIL_FORMAT_COLORSPACE_ZS: 1132 switch (format) { 1133 case PIPE_FORMAT_Z16_UNORM: 1134 return V_008F14_IMG_DATA_FORMAT_16; 1135 case PIPE_FORMAT_X24S8_UINT: 1136 case PIPE_FORMAT_Z24X8_UNORM: 1137 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1138 return V_008F14_IMG_DATA_FORMAT_24_8; 1139 case PIPE_FORMAT_S8X24_UINT: 1140 case PIPE_FORMAT_X8Z24_UNORM: 1141 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1142 return V_008F14_IMG_DATA_FORMAT_8_24; 1143 case PIPE_FORMAT_S8_UINT: 1144 return V_008F14_IMG_DATA_FORMAT_8; 1145 case PIPE_FORMAT_Z32_FLOAT: 1146 return V_008F14_IMG_DATA_FORMAT_32; 1147 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1148 return V_008F14_IMG_DATA_FORMAT_X24_8_32; 1149 default: 1150 goto out_unknown; 1151 } 1152 1153 case UTIL_FORMAT_COLORSPACE_YUV: 1154 goto out_unknown; /* TODO */ 1155 1156 case UTIL_FORMAT_COLORSPACE_SRGB: 1157 break; 1158 1159 default: 1160 break; 1161 } 1162 1163 /* TODO compressed formats */ 1164 1165 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 1166 return V_008F14_IMG_DATA_FORMAT_5_9_9_9; 1167 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 1168 return V_008F14_IMG_DATA_FORMAT_10_11_11; 1169 } 1170 1171 /* R8G8Bx_SNORM - TODO CxV8U8 */ 1172 1173 /* See whether the components are of the same size. */ 1174 for (i = 1; i < desc->nr_channels; i++) { 1175 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1176 } 1177 1178 /* Non-uniform formats. */ 1179 if (!uniform) { 1180 switch(desc->nr_channels) { 1181 case 3: 1182 if (desc->channel[0].size == 5 && 1183 desc->channel[1].size == 6 && 1184 desc->channel[2].size == 5) { 1185 return V_008F14_IMG_DATA_FORMAT_5_6_5; 1186 } 1187 goto out_unknown; 1188 case 4: 1189 if (desc->channel[0].size == 5 && 1190 desc->channel[1].size == 5 && 1191 desc->channel[2].size == 5 && 1192 desc->channel[3].size == 1) { 1193 return V_008F14_IMG_DATA_FORMAT_1_5_5_5; 1194 } 1195 if (desc->channel[0].size == 10 && 1196 desc->channel[1].size == 10 && 1197 desc->channel[2].size == 10 && 1198 desc->channel[3].size == 2) { 1199 return V_008F14_IMG_DATA_FORMAT_2_10_10_10; 1200 } 1201 goto out_unknown; 1202 } 1203 goto out_unknown; 1204 } 1205 1206 if (first_non_void < 0 || first_non_void > 3) 1207 goto out_unknown; 1208 1209 /* uniform formats */ 1210 switch (desc->channel[first_non_void].size) { 1211 case 4: 1212 switch (desc->nr_channels) { 1213#if 0 /* Not supported for render targets */ 1214 case 2: 1215 return V_008F14_IMG_DATA_FORMAT_4_4; 1216#endif 1217 case 4: 1218 return V_008F14_IMG_DATA_FORMAT_4_4_4_4; 1219 } 1220 break; 1221 case 8: 1222 switch (desc->nr_channels) { 1223 case 1: 1224 return V_008F14_IMG_DATA_FORMAT_8; 1225 case 2: 1226 return V_008F14_IMG_DATA_FORMAT_8_8; 1227 case 4: 1228 return V_008F14_IMG_DATA_FORMAT_8_8_8_8; 1229 } 1230 break; 1231 case 16: 1232 switch (desc->nr_channels) { 1233 case 1: 1234 return V_008F14_IMG_DATA_FORMAT_16; 1235 case 2: 1236 return V_008F14_IMG_DATA_FORMAT_16_16; 1237 case 4: 1238 return V_008F14_IMG_DATA_FORMAT_16_16_16_16; 1239 } 1240 break; 1241 case 32: 1242 switch (desc->nr_channels) { 1243 case 1: 1244 return V_008F14_IMG_DATA_FORMAT_32; 1245 case 2: 1246 return V_008F14_IMG_DATA_FORMAT_32_32; 1247#if 0 /* Not supported for render targets */ 1248 case 3: 1249 return V_008F14_IMG_DATA_FORMAT_32_32_32; 1250#endif 1251 case 4: 1252 return V_008F14_IMG_DATA_FORMAT_32_32_32_32; 1253 } 1254 } 1255 1256out_unknown: 1257 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1258 return ~0; 1259} 1260 1261static unsigned si_tex_wrap(unsigned wrap) 1262{ 1263 switch (wrap) { 1264 default: 1265 case PIPE_TEX_WRAP_REPEAT: 1266 return V_008F30_SQ_TEX_WRAP; 1267 case PIPE_TEX_WRAP_CLAMP: 1268 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER; 1269 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 1270 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL; 1271 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 1272 return V_008F30_SQ_TEX_CLAMP_BORDER; 1273 case PIPE_TEX_WRAP_MIRROR_REPEAT: 1274 return V_008F30_SQ_TEX_MIRROR; 1275 case PIPE_TEX_WRAP_MIRROR_CLAMP: 1276 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 1277 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 1278 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 1279 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 1280 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER; 1281 } 1282} 1283 1284static unsigned si_tex_filter(unsigned filter) 1285{ 1286 switch (filter) { 1287 default: 1288 case PIPE_TEX_FILTER_NEAREST: 1289 return V_008F38_SQ_TEX_XY_FILTER_POINT; 1290 case PIPE_TEX_FILTER_LINEAR: 1291 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR; 1292 } 1293} 1294 1295static unsigned si_tex_mipfilter(unsigned filter) 1296{ 1297 switch (filter) { 1298 case PIPE_TEX_MIPFILTER_NEAREST: 1299 return V_008F38_SQ_TEX_Z_FILTER_POINT; 1300 case PIPE_TEX_MIPFILTER_LINEAR: 1301 return V_008F38_SQ_TEX_Z_FILTER_LINEAR; 1302 default: 1303 case PIPE_TEX_MIPFILTER_NONE: 1304 return V_008F38_SQ_TEX_Z_FILTER_NONE; 1305 } 1306} 1307 1308static unsigned si_tex_compare(unsigned compare) 1309{ 1310 switch (compare) { 1311 default: 1312 case PIPE_FUNC_NEVER: 1313 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER; 1314 case PIPE_FUNC_LESS: 1315 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS; 1316 case PIPE_FUNC_EQUAL: 1317 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL; 1318 case PIPE_FUNC_LEQUAL: 1319 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 1320 case PIPE_FUNC_GREATER: 1321 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER; 1322 case PIPE_FUNC_NOTEQUAL: 1323 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 1324 case PIPE_FUNC_GEQUAL: 1325 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 1326 case PIPE_FUNC_ALWAYS: 1327 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS; 1328 } 1329} 1330 1331static unsigned si_tex_dim(unsigned dim) 1332{ 1333 switch (dim) { 1334 default: 1335 case PIPE_TEXTURE_1D: 1336 return V_008F1C_SQ_RSRC_IMG_1D; 1337 case PIPE_TEXTURE_1D_ARRAY: 1338 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY; 1339 case PIPE_TEXTURE_2D: 1340 case PIPE_TEXTURE_RECT: 1341 return V_008F1C_SQ_RSRC_IMG_2D; 1342 case PIPE_TEXTURE_2D_ARRAY: 1343 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY; 1344 case PIPE_TEXTURE_3D: 1345 return V_008F1C_SQ_RSRC_IMG_3D; 1346 case PIPE_TEXTURE_CUBE: 1347 return V_008F1C_SQ_RSRC_IMG_CUBE; 1348 } 1349} 1350 1351/* 1352 * Format support testing 1353 */ 1354 1355static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 1356{ 1357 return si_translate_texformat(screen, format, util_format_description(format), 1358 util_format_get_first_non_void_channel(format)) != ~0U; 1359} 1360 1361static uint32_t si_translate_vertexformat(struct pipe_screen *screen, 1362 enum pipe_format format, 1363 const struct util_format_description *desc, 1364 int first_non_void) 1365{ 1366 unsigned type = desc->channel[first_non_void].type; 1367 int i; 1368 1369 if (type == UTIL_FORMAT_TYPE_FIXED) 1370 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1371 1372 /* See whether the components are of the same size. */ 1373 for (i = 0; i < desc->nr_channels; i++) { 1374 if (desc->channel[first_non_void].size != desc->channel[i].size) 1375 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1376 } 1377 1378 switch (desc->channel[first_non_void].size) { 1379 case 8: 1380 switch (desc->nr_channels) { 1381 case 1: 1382 return V_008F0C_BUF_DATA_FORMAT_8; 1383 case 2: 1384 return V_008F0C_BUF_DATA_FORMAT_8_8; 1385 case 3: 1386 case 4: 1387 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8; 1388 } 1389 break; 1390 case 16: 1391 switch (desc->nr_channels) { 1392 case 1: 1393 return V_008F0C_BUF_DATA_FORMAT_16; 1394 case 2: 1395 return V_008F0C_BUF_DATA_FORMAT_16_16; 1396 case 3: 1397 case 4: 1398 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16; 1399 } 1400 break; 1401 case 32: 1402 if (type != UTIL_FORMAT_TYPE_FLOAT) 1403 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1404 1405 switch (desc->nr_channels) { 1406 case 1: 1407 return V_008F0C_BUF_DATA_FORMAT_32; 1408 case 2: 1409 return V_008F0C_BUF_DATA_FORMAT_32_32; 1410 case 3: 1411 return V_008F0C_BUF_DATA_FORMAT_32_32_32; 1412 case 4: 1413 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32; 1414 } 1415 break; 1416 } 1417 1418 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1419} 1420 1421static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format) 1422{ 1423 const struct util_format_description *desc; 1424 int first_non_void; 1425 unsigned data_format; 1426 1427 desc = util_format_description(format); 1428 first_non_void = util_format_get_first_non_void_channel(format); 1429 data_format = si_translate_vertexformat(screen, format, desc, first_non_void); 1430 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID; 1431} 1432 1433static bool si_is_colorbuffer_format_supported(enum pipe_format format) 1434{ 1435 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID && 1436 si_translate_colorswap(format) != ~0U; 1437} 1438 1439static bool si_is_zs_format_supported(enum pipe_format format) 1440{ 1441 return si_translate_dbformat(format) != V_028040_Z_INVALID; 1442} 1443 1444boolean si_is_format_supported(struct pipe_screen *screen, 1445 enum pipe_format format, 1446 enum pipe_texture_target target, 1447 unsigned sample_count, 1448 unsigned usage) 1449{ 1450 unsigned retval = 0; 1451 1452 if (target >= PIPE_MAX_TEXTURE_TYPES) { 1453 R600_ERR("r600: unsupported texture type %d\n", target); 1454 return FALSE; 1455 } 1456 1457 if (!util_format_is_supported(format, usage)) 1458 return FALSE; 1459 1460 /* Multisample */ 1461 if (sample_count > 1) 1462 return FALSE; 1463 1464 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 1465 si_is_sampler_format_supported(screen, format)) { 1466 retval |= PIPE_BIND_SAMPLER_VIEW; 1467 } 1468 1469 if ((usage & (PIPE_BIND_RENDER_TARGET | 1470 PIPE_BIND_DISPLAY_TARGET | 1471 PIPE_BIND_SCANOUT | 1472 PIPE_BIND_SHARED)) && 1473 si_is_colorbuffer_format_supported(format)) { 1474 retval |= usage & 1475 (PIPE_BIND_RENDER_TARGET | 1476 PIPE_BIND_DISPLAY_TARGET | 1477 PIPE_BIND_SCANOUT | 1478 PIPE_BIND_SHARED); 1479 } 1480 1481 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 1482 si_is_zs_format_supported(format)) { 1483 retval |= PIPE_BIND_DEPTH_STENCIL; 1484 } 1485 1486 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 1487 si_is_vertex_format_supported(screen, format)) { 1488 retval |= PIPE_BIND_VERTEX_BUFFER; 1489 } 1490 1491 if (usage & PIPE_BIND_TRANSFER_READ) 1492 retval |= PIPE_BIND_TRANSFER_READ; 1493 if (usage & PIPE_BIND_TRANSFER_WRITE) 1494 retval |= PIPE_BIND_TRANSFER_WRITE; 1495 1496 return retval == usage; 1497} 1498 1499static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level) 1500{ 1501 if (util_format_is_depth_or_stencil(rtex->real_format)) { 1502 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) { 1503 return 4; 1504 } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) { 1505 switch (rtex->real_format) { 1506 case PIPE_FORMAT_Z16_UNORM: 1507 return 5; 1508 case PIPE_FORMAT_Z24X8_UNORM: 1509 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1510 case PIPE_FORMAT_Z32_FLOAT: 1511 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1512 return 6; 1513 default: 1514 return 7; 1515 } 1516 } 1517 } 1518 1519 switch (rtex->surface.level[level].mode) { 1520 default: 1521 assert(!"Invalid surface mode"); 1522 /* Fall through */ 1523 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1524 return 8; 1525 case RADEON_SURF_MODE_1D: 1526 return 9; 1527 case RADEON_SURF_MODE_2D: 1528 if (rtex->surface.flags & RADEON_SURF_SCANOUT) { 1529 switch (util_format_get_blocksize(rtex->real_format)) { 1530 case 1: 1531 return 10; 1532 case 2: 1533 return 11; 1534 default: 1535 assert(!"Invalid block size"); 1536 /* Fall through */ 1537 case 4: 1538 return 12; 1539 } 1540 } else { 1541 switch (util_format_get_blocksize(rtex->real_format)) { 1542 case 1: 1543 return 14; 1544 case 2: 1545 return 15; 1546 case 4: 1547 return 16; 1548 case 8: 1549 return 17; 1550 default: 1551 return 13; 1552 } 1553 } 1554 } 1555} 1556 1557/* 1558 * framebuffer handling 1559 */ 1560 1561static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, 1562 const struct pipe_framebuffer_state *state, int cb) 1563{ 1564 struct r600_resource_texture *rtex; 1565 struct r600_surface *surf; 1566 unsigned level = state->cbufs[cb]->u.tex.level; 1567 unsigned pitch, slice; 1568 unsigned color_info; 1569 unsigned tile_mode_index; 1570 unsigned format, swap, ntype, endian; 1571 uint64_t offset; 1572 const struct util_format_description *desc; 1573 int i; 1574 unsigned blend_clamp = 0, blend_bypass = 0; 1575 unsigned max_comp_size; 1576 1577 surf = (struct r600_surface *)state->cbufs[cb]; 1578 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; 1579 1580 if (rtex->depth) 1581 rctx->have_depth_fb = TRUE; 1582 1583 if (rtex->depth && !rtex->is_flushing_texture) { 1584 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE); 1585 rtex = rtex->flushed_depth_texture; 1586 } 1587 1588 offset = rtex->surface.level[level].offset; 1589 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1590 offset += rtex->surface.level[level].slice_size * 1591 state->cbufs[cb]->u.tex.first_layer; 1592 } 1593 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; 1594 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1595 if (slice) { 1596 slice = slice - 1; 1597 } 1598 1599 tile_mode_index = si_tile_mode_index(rtex, level); 1600 1601 desc = util_format_description(surf->base.format); 1602 for (i = 0; i < 4; i++) { 1603 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1604 break; 1605 } 1606 } 1607 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { 1608 ntype = V_028C70_NUMBER_FLOAT; 1609 } else { 1610 ntype = V_028C70_NUMBER_UNORM; 1611 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1612 ntype = V_028C70_NUMBER_SRGB; 1613 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1614 if (desc->channel[i].normalized) 1615 ntype = V_028C70_NUMBER_SNORM; 1616 else if (desc->channel[i].pure_integer) 1617 ntype = V_028C70_NUMBER_SINT; 1618 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1619 if (desc->channel[i].normalized) 1620 ntype = V_028C70_NUMBER_UNORM; 1621 else if (desc->channel[i].pure_integer) 1622 ntype = V_028C70_NUMBER_UINT; 1623 } 1624 } 1625 1626 format = si_translate_colorformat(surf->base.format); 1627 if (format == V_028C70_COLOR_INVALID) { 1628 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format); 1629 } 1630 assert(format != V_028C70_COLOR_INVALID); 1631 swap = si_translate_colorswap(surf->base.format); 1632 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { 1633 endian = V_028C70_ENDIAN_NONE; 1634 } else { 1635 endian = si_colorformat_endian_swap(format); 1636 } 1637 1638 /* blend clamp should be set for all NORM/SRGB types */ 1639 if (ntype == V_028C70_NUMBER_UNORM || 1640 ntype == V_028C70_NUMBER_SNORM || 1641 ntype == V_028C70_NUMBER_SRGB) 1642 blend_clamp = 1; 1643 1644 /* set blend bypass according to docs if SINT/UINT or 1645 8/24 COLOR variants */ 1646 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT || 1647 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 || 1648 format == V_028C70_COLOR_X24_8_32_FLOAT) { 1649 blend_clamp = 0; 1650 blend_bypass = 1; 1651 } 1652 1653 color_info = S_028C70_FORMAT(format) | 1654 S_028C70_COMP_SWAP(swap) | 1655 S_028C70_BLEND_CLAMP(blend_clamp) | 1656 S_028C70_BLEND_BYPASS(blend_bypass) | 1657 S_028C70_NUMBER_TYPE(ntype) | 1658 S_028C70_ENDIAN(endian); 1659 1660 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture); 1661 offset >>= 8; 1662 1663 /* FIXME handle enabling of CB beyond BASE8 which has different offset */ 1664 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); 1665 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset); 1666 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch)); 1667 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice)); 1668 1669 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1670 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000); 1671 } else { 1672 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 1673 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) | 1674 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer)); 1675 } 1676 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info); 1677 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, 1678 S_028C74_TILE_MODE_INDEX(tile_mode_index)); 1679 1680 /* Determine pixel shader export format */ 1681 max_comp_size = si_colorformat_max_comp_size(format); 1682 if (ntype == V_028C70_NUMBER_SRGB || 1683 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) && 1684 max_comp_size <= 10) || 1685 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) { 1686 rctx->export_16bpc |= 1 << cb; 1687 rctx->spi_shader_col_format |= V_028714_SPI_SHADER_FP16_ABGR << (4 * cb); 1688 } else 1689 rctx->spi_shader_col_format |= V_028714_SPI_SHADER_32_ABGR << (4 * cb); 1690} 1691 1692static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, 1693 const struct pipe_framebuffer_state *state) 1694{ 1695 struct r600_resource_texture *rtex; 1696 struct r600_surface *surf; 1697 unsigned level, pitch, slice, format, tile_mode_index; 1698 uint32_t z_info, s_info; 1699 uint64_t z_offs, s_offs; 1700 1701 if (state->zsbuf == NULL) { 1702 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID)); 1703 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID)); 1704 return; 1705 } 1706 1707 surf = (struct r600_surface *)state->zsbuf; 1708 level = surf->base.u.tex.level; 1709 rtex = (struct r600_resource_texture*)surf->base.texture; 1710 1711 format = si_translate_dbformat(rtex->real_format); 1712 1713 if (format == V_028040_Z_INVALID) { 1714 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format); 1715 } 1716 assert(format != V_028040_Z_INVALID); 1717 1718 s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture); 1719 z_offs += rtex->surface.level[level].offset; 1720 s_offs += rtex->surface.stencil_level[level].offset; 1721 1722 z_offs >>= 8; 1723 s_offs >>= 8; 1724 1725 pitch = (rtex->surface.level[level].nblk_x / 8) - 1; 1726 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1727 if (slice) { 1728 slice = slice - 1; 1729 } 1730 1731 z_info = S_028040_FORMAT(format); 1732 if (rtex->surface.flags & RADEON_SURF_SBUFFER) 1733 s_info = S_028044_FORMAT(V_028044_STENCIL_8); 1734 else 1735 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID); 1736 1737 tile_mode_index = si_tile_mode_index(rtex, level); 1738 if (tile_mode_index < 4 || tile_mode_index > 7) { 1739 R600_ERR("Invalid DB tiling mode %d!\n", 1740 rtex->surface.level[level].mode); 1741 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID)); 1742 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID)); 1743 return; 1744 } 1745 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); 1746 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index); 1747 1748 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, 1749 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) | 1750 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer)); 1751 1752 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, S_02803C_ADDR5_SWIZZLE_MASK(1)); 1753 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info); 1754 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info); 1755 1756 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); 1757 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs); 1758 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs); 1759 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs); 1760 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs); 1761 1762 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch)); 1763 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice)); 1764} 1765 1766static void si_set_framebuffer_state(struct pipe_context *ctx, 1767 const struct pipe_framebuffer_state *state) 1768{ 1769 struct r600_context *rctx = (struct r600_context *)ctx; 1770 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 1771 uint32_t shader_mask, tl, br; 1772 int tl_x, tl_y, br_x, br_y; 1773 1774 if (pm4 == NULL) 1775 return; 1776 1777 si_pm4_inval_fb_cache(pm4, state->nr_cbufs); 1778 1779 if (state->zsbuf) 1780 si_pm4_inval_zsbuf_cache(pm4); 1781 1782 util_copy_framebuffer_state(&rctx->framebuffer, state); 1783 1784 /* build states */ 1785 rctx->have_depth_fb = 0; 1786 rctx->export_16bpc = 0; 1787 rctx->spi_shader_col_format = 0; 1788 for (int i = 0; i < state->nr_cbufs; i++) { 1789 si_cb(rctx, pm4, state, i); 1790 } 1791 assert(!(rctx->export_16bpc & ~0xff)); 1792 si_db(rctx, pm4, state); 1793 1794 shader_mask = 0; 1795 for (int i = 0; i < state->nr_cbufs; i++) { 1796 shader_mask |= 0xf << (i * 4); 1797 } 1798 tl_x = 0; 1799 tl_y = 0; 1800 br_x = state->width; 1801 br_y = state->height; 1802 1803 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y); 1804 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y); 1805 1806 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl); 1807 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br); 1808 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl); 1809 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br); 1810 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl); 1811 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br); 1812 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl); 1813 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br); 1814 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000); 1815 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 1816 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask); 1817 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, 1818 rctx->spi_shader_col_format); 1819 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000); 1820 1821 si_pm4_set_state(rctx, framebuffer, pm4); 1822 si_update_fb_rs_state(rctx); 1823 si_update_fb_blend_state(rctx); 1824} 1825 1826/* 1827 * shaders 1828 */ 1829 1830/* Compute the key for the hw shader variant */ 1831static INLINE struct si_shader_key si_shader_selector_key(struct pipe_context *ctx, 1832 struct si_pipe_shader_selector *sel) 1833{ 1834 struct r600_context *rctx = (struct r600_context *)ctx; 1835 struct si_shader_key key; 1836 memset(&key, 0, sizeof(key)); 1837 1838 if (sel->type == PIPE_SHADER_FRAGMENT) { 1839 if (sel->fs_write_all) 1840 key.nr_cbufs = rctx->framebuffer.nr_cbufs; 1841 key.export_16bpc = rctx->export_16bpc; 1842 if (rctx->queued.named.rasterizer) { 1843 key.color_two_side = rctx->queued.named.rasterizer->two_side; 1844 /*key.flatshade = rctx->queued.named.rasterizer->flatshade;*/ 1845 } 1846 if (rctx->queued.named.dsa) { 1847 key.alpha_func = rctx->queued.named.dsa->alpha_func; 1848 key.alpha_ref = rctx->queued.named.dsa->alpha_ref; 1849 } else { 1850 key.alpha_func = PIPE_FUNC_ALWAYS; 1851 } 1852 } 1853 1854 return key; 1855} 1856 1857/* Select the hw shader variant depending on the current state. 1858 * (*dirty) is set to 1 if current variant was changed */ 1859int si_shader_select(struct pipe_context *ctx, 1860 struct si_pipe_shader_selector *sel, 1861 unsigned *dirty) 1862{ 1863 struct si_shader_key key; 1864 struct si_pipe_shader * shader = NULL; 1865 int r; 1866 1867 key = si_shader_selector_key(ctx, sel); 1868 1869 /* Check if we don't need to change anything. 1870 * This path is also used for most shaders that don't need multiple 1871 * variants, it will cost just a computation of the key and this 1872 * test. */ 1873 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) { 1874 return 0; 1875 } 1876 1877 /* lookup if we have other variants in the list */ 1878 if (sel->num_shaders > 1) { 1879 struct si_pipe_shader *p = sel->current, *c = p->next_variant; 1880 1881 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) { 1882 p = c; 1883 c = c->next_variant; 1884 } 1885 1886 if (c) { 1887 p->next_variant = c->next_variant; 1888 shader = c; 1889 } 1890 } 1891 1892 if (unlikely(!shader)) { 1893 shader = CALLOC(1, sizeof(struct si_pipe_shader)); 1894 shader->selector = sel; 1895 1896 r = si_pipe_shader_create(ctx, shader, key); 1897 if (unlikely(r)) { 1898 R600_ERR("Failed to build shader variant (type=%u) %d\n", 1899 sel->type, r); 1900 sel->current = NULL; 1901 return r; 1902 } 1903 1904 /* We don't know the value of fs_write_all property until we built 1905 * at least one variant, so we may need to recompute the key (include 1906 * rctx->framebuffer.nr_cbufs) after building first variant. */ 1907 if (sel->type == PIPE_SHADER_FRAGMENT && 1908 sel->num_shaders == 0 && 1909 shader->shader.fs_write_all) { 1910 sel->fs_write_all = 1; 1911 key = si_shader_selector_key(ctx, sel); 1912 } 1913 1914 shader->key = key; 1915 sel->num_shaders++; 1916 } 1917 1918 if (dirty) 1919 *dirty = 1; 1920 1921 shader->next_variant = sel->current; 1922 sel->current = shader; 1923 1924 return 0; 1925} 1926 1927static void *si_create_shader_state(struct pipe_context *ctx, 1928 const struct pipe_shader_state *state, 1929 unsigned pipe_shader_type) 1930{ 1931 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector); 1932 int r; 1933 1934 sel->type = pipe_shader_type; 1935 sel->tokens = tgsi_dup_tokens(state->tokens); 1936 sel->so = state->stream_output; 1937 1938 r = si_shader_select(ctx, sel, NULL); 1939 if (r) { 1940 free(sel); 1941 return NULL; 1942 } 1943 1944 return sel; 1945} 1946 1947static void *si_create_fs_state(struct pipe_context *ctx, 1948 const struct pipe_shader_state *state) 1949{ 1950 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT); 1951} 1952 1953static void *si_create_vs_state(struct pipe_context *ctx, 1954 const struct pipe_shader_state *state) 1955{ 1956 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX); 1957} 1958 1959static void si_bind_vs_shader(struct pipe_context *ctx, void *state) 1960{ 1961 struct r600_context *rctx = (struct r600_context *)ctx; 1962 struct si_pipe_shader_selector *sel = state; 1963 1964 if (rctx->vs_shader == sel) 1965 return; 1966 1967 rctx->vs_shader = sel; 1968 1969 if (sel && sel->current) 1970 si_pm4_bind_state(rctx, vs, sel->current->pm4); 1971 else 1972 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4); 1973} 1974 1975static void si_bind_ps_shader(struct pipe_context *ctx, void *state) 1976{ 1977 struct r600_context *rctx = (struct r600_context *)ctx; 1978 struct si_pipe_shader_selector *sel = state; 1979 1980 if (rctx->ps_shader == sel) 1981 return; 1982 1983 rctx->ps_shader = sel; 1984 1985 if (sel && sel->current) 1986 si_pm4_bind_state(rctx, ps, sel->current->pm4); 1987 else 1988 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4); 1989} 1990 1991static void si_delete_shader_selector(struct pipe_context *ctx, 1992 struct si_pipe_shader_selector *sel) 1993{ 1994 struct r600_context *rctx = (struct r600_context *)ctx; 1995 struct si_pipe_shader *p = sel->current, *c; 1996 1997 while (p) { 1998 c = p->next_variant; 1999 si_pm4_delete_state(rctx, vs, p->pm4); 2000 si_pipe_shader_destroy(ctx, p); 2001 free(p); 2002 p = c; 2003 } 2004 2005 free(sel->tokens); 2006 free(sel); 2007 } 2008 2009static void si_delete_vs_shader(struct pipe_context *ctx, void *state) 2010{ 2011 struct r600_context *rctx = (struct r600_context *)ctx; 2012 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; 2013 2014 if (rctx->vs_shader == sel) { 2015 rctx->vs_shader = NULL; 2016 } 2017 2018 si_delete_shader_selector(ctx, sel); 2019} 2020 2021static void si_delete_ps_shader(struct pipe_context *ctx, void *state) 2022{ 2023 struct r600_context *rctx = (struct r600_context *)ctx; 2024 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; 2025 2026 if (rctx->ps_shader == sel) { 2027 rctx->ps_shader = NULL; 2028 } 2029 2030 si_delete_shader_selector(ctx, sel); 2031} 2032 2033/* 2034 * Samplers 2035 */ 2036 2037static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx, 2038 struct pipe_resource *texture, 2039 const struct pipe_sampler_view *state) 2040{ 2041 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view); 2042 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; 2043 const struct util_format_description *desc = util_format_description(state->format); 2044 unsigned format, num_format; 2045 uint32_t pitch = 0; 2046 unsigned char state_swizzle[4], swizzle[4]; 2047 unsigned height, depth, width; 2048 int first_non_void; 2049 uint64_t va; 2050 2051 if (view == NULL) 2052 return NULL; 2053 2054 /* initialize base object */ 2055 view->base = *state; 2056 view->base.texture = NULL; 2057 pipe_reference(NULL, &texture->reference); 2058 view->base.texture = texture; 2059 view->base.reference.count = 1; 2060 view->base.context = ctx; 2061 2062 state_swizzle[0] = state->swizzle_r; 2063 state_swizzle[1] = state->swizzle_g; 2064 state_swizzle[2] = state->swizzle_b; 2065 state_swizzle[3] = state->swizzle_a; 2066 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle); 2067 2068 first_non_void = util_format_get_first_non_void_channel(state->format); 2069 switch (desc->channel[first_non_void].type) { 2070 case UTIL_FORMAT_TYPE_FLOAT: 2071 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2072 break; 2073 case UTIL_FORMAT_TYPE_SIGNED: 2074 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 2075 break; 2076 case UTIL_FORMAT_TYPE_UNSIGNED: 2077 default: 2078 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2079 } 2080 2081 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void); 2082 if (format == ~0) { 2083 format = 0; 2084 } 2085 2086 if (tmp->depth && !tmp->is_flushing_texture) { 2087 r600_texture_depth_flush(ctx, texture, TRUE); 2088 tmp = tmp->flushed_depth_texture; 2089 texture = &tmp->resource.b.b; 2090 } 2091 2092 view->resource = &tmp->resource; 2093 2094 /* not supported any more */ 2095 //endian = si_colorformat_endian_swap(format); 2096 2097 width = tmp->surface.level[0].npix_x; 2098 height = tmp->surface.level[0].npix_y; 2099 depth = tmp->surface.level[0].npix_z; 2100 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format); 2101 2102 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 2103 height = 1; 2104 depth = texture->array_size; 2105 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 2106 depth = texture->array_size; 2107 } 2108 2109 va = r600_resource_va(ctx->screen, texture); 2110 va += tmp->surface.level[0].offset; 2111 view->state[0] = va >> 8; 2112 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) | 2113 S_008F14_DATA_FORMAT(format) | 2114 S_008F14_NUM_FORMAT(num_format)); 2115 view->state[2] = (S_008F18_WIDTH(width - 1) | 2116 S_008F18_HEIGHT(height - 1)); 2117 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) | 2118 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | 2119 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | 2120 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | 2121 S_008F1C_BASE_LEVEL(state->u.tex.first_level) | 2122 S_008F1C_LAST_LEVEL(state->u.tex.last_level) | 2123 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0)) | 2124 S_008F1C_POW2_PAD(texture->last_level > 0) | 2125 S_008F1C_TYPE(si_tex_dim(texture->target))); 2126 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1)); 2127 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) | 2128 S_008F24_LAST_ARRAY(state->u.tex.last_layer)); 2129 view->state[6] = 0; 2130 view->state[7] = 0; 2131 2132 return &view->base; 2133} 2134 2135static void si_sampler_view_destroy(struct pipe_context *ctx, 2136 struct pipe_sampler_view *state) 2137{ 2138 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; 2139 2140 pipe_resource_reference(&state->texture, NULL); 2141 FREE(resource); 2142} 2143 2144static void *si_create_sampler_state(struct pipe_context *ctx, 2145 const struct pipe_sampler_state *state) 2146{ 2147 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state); 2148 union util_color uc; 2149 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; 2150 unsigned border_color_type; 2151 2152 if (rstate == NULL) { 2153 return NULL; 2154 } 2155 2156 util_pack_color(state->border_color.f, PIPE_FORMAT_A8R8G8B8_UNORM, &uc); 2157 switch (uc.ui) { 2158 case 0x000000FF: 2159 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK; 2160 break; 2161 case 0x00000000: 2162 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; 2163 break; 2164 case 0xFFFFFFFF: 2165 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE; 2166 break; 2167 default: /* Use border color pointer */ 2168 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER; 2169 } 2170 2171 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | 2172 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) | 2173 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) | 2174 (state->max_anisotropy & 0x7) << 9 | /* XXX */ 2175 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) | 2176 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) | 2177 aniso_flag_offset << 16 | /* XXX */ 2178 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map)); 2179 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | 2180 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8))); 2181 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) | 2182 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) | 2183 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) | 2184 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter))); 2185 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type); 2186 2187 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) { 2188 memcpy(rstate->border_color, state->border_color.f, 2189 sizeof(rstate->border_color)); 2190 } 2191 2192 return rstate; 2193} 2194 2195static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx, 2196 unsigned count, 2197 struct pipe_sampler_view **views, 2198 struct r600_textures_info *samplers, 2199 unsigned user_data_reg) 2200{ 2201 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views; 2202 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2203 int i, j; 2204 int has_depth = 0; 2205 2206 if (!count) 2207 goto out; 2208 2209 si_pm4_inval_texture_cache(pm4); 2210 2211 si_pm4_sh_data_begin(pm4); 2212 for (i = 0; i < count; i++) { 2213 pipe_sampler_view_reference( 2214 (struct pipe_sampler_view **)&samplers->views[i], 2215 views[i]); 2216 2217 if (views[i]) 2218 si_pm4_add_bo(pm4, resource[i]->resource, RADEON_USAGE_READ); 2219 2220 for (j = 0; j < Elements(resource[i]->state); ++j) { 2221 si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0); 2222 } 2223 } 2224 2225 for (i = count; i < NUM_TEX_UNITS; i++) { 2226 if (samplers->views[i]) 2227 pipe_sampler_view_reference((struct pipe_sampler_view **)&samplers->views[i], NULL); 2228 } 2229 2230 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_RESOURCE); 2231 2232out: 2233 rctx->have_depth_texture = has_depth; 2234 rctx->ps_samplers.n_views = count; 2235 return pm4; 2236} 2237 2238static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count, 2239 struct pipe_sampler_view **views) 2240{ 2241 struct r600_context *rctx = (struct r600_context *)ctx; 2242 struct si_pm4_state *pm4; 2243 2244 pm4 = si_set_sampler_view(rctx, count, views, &rctx->vs_samplers, 2245 R_00B130_SPI_SHADER_USER_DATA_VS_0); 2246 si_pm4_set_state(rctx, vs_sampler_views, pm4); 2247} 2248 2249static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count, 2250 struct pipe_sampler_view **views) 2251{ 2252 struct r600_context *rctx = (struct r600_context *)ctx; 2253 struct si_pm4_state *pm4; 2254 2255 pm4 = si_set_sampler_view(rctx, count, views, &rctx->ps_samplers, 2256 R_00B030_SPI_SHADER_USER_DATA_PS_0); 2257 si_pm4_set_state(rctx, ps_sampler_views, pm4); 2258} 2259 2260static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned count, 2261 void **states, 2262 struct r600_textures_info *samplers, 2263 unsigned user_data_reg) 2264{ 2265 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states; 2266 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2267 uint32_t *border_color_table = NULL; 2268 int i, j; 2269 2270 if (!count) 2271 goto out; 2272 2273 si_pm4_inval_texture_cache(pm4); 2274 2275 si_pm4_sh_data_begin(pm4); 2276 for (i = 0; i < count; i++) { 2277 if (rstates[i] && 2278 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) == 2279 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) { 2280 if (!rctx->border_color_table || 2281 ((rctx->border_color_offset + count - i) & 2282 C_008F3C_BORDER_COLOR_PTR)) { 2283 si_resource_reference(&rctx->border_color_table, NULL); 2284 rctx->border_color_offset = 0; 2285 2286 rctx->border_color_table = 2287 si_resource_create_custom(&rctx->screen->screen, 2288 PIPE_USAGE_STAGING, 2289 4096 * 4 * 4); 2290 } 2291 2292 if (!border_color_table) { 2293 border_color_table = 2294 rctx->ws->buffer_map(rctx->border_color_table->cs_buf, 2295 rctx->cs, 2296 PIPE_TRANSFER_WRITE | 2297 PIPE_TRANSFER_UNSYNCHRONIZED); 2298 } 2299 2300 for (j = 0; j < 4; j++) { 2301 union fi border_color; 2302 2303 border_color.f = rstates[i]->border_color[j]; 2304 border_color_table[4 * rctx->border_color_offset + j] = 2305 util_le32_to_cpu(border_color.i); 2306 } 2307 2308 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR; 2309 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++); 2310 } 2311 2312 for (j = 0; j < Elements(rstates[i]->val); ++j) { 2313 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0); 2314 } 2315 } 2316 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER); 2317 2318 if (border_color_table) { 2319 uint64_t va_offset = 2320 r600_resource_va(&rctx->screen->screen, 2321 (void*)rctx->border_color_table); 2322 2323 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8); 2324 rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf); 2325 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ); 2326 } 2327 2328 memcpy(samplers->samplers, states, sizeof(void*) * count); 2329 2330out: 2331 samplers->n_samplers = count; 2332 return pm4; 2333} 2334 2335static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states) 2336{ 2337 struct r600_context *rctx = (struct r600_context *)ctx; 2338 struct si_pm4_state *pm4; 2339 2340 pm4 = si_bind_sampler(rctx, count, states, &rctx->vs_samplers, 2341 R_00B130_SPI_SHADER_USER_DATA_VS_0); 2342 si_pm4_set_state(rctx, vs_sampler, pm4); 2343} 2344 2345static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states) 2346{ 2347 struct r600_context *rctx = (struct r600_context *)ctx; 2348 struct si_pm4_state *pm4; 2349 2350 pm4 = si_bind_sampler(rctx, count, states, &rctx->ps_samplers, 2351 R_00B030_SPI_SHADER_USER_DATA_PS_0); 2352 si_pm4_set_state(rctx, ps_sampler, pm4); 2353} 2354 2355static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 2356{ 2357} 2358 2359static void si_delete_sampler_state(struct pipe_context *ctx, void *state) 2360{ 2361 free(state); 2362} 2363 2364/* 2365 * Constants 2366 */ 2367static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 2368 struct pipe_constant_buffer *cb) 2369{ 2370 struct r600_context *rctx = (struct r600_context *)ctx; 2371 struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL; 2372 struct si_pm4_state *pm4; 2373 uint64_t va_offset; 2374 uint32_t reg, offset; 2375 2376 /* Note that the state tracker can unbind constant buffers by 2377 * passing NULL here. 2378 */ 2379 if (cb == NULL) 2380 return; 2381 2382 pm4 = CALLOC_STRUCT(si_pm4_state); 2383 si_pm4_inval_shader_cache(pm4); 2384 2385 if (cb->user_buffer) 2386 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset); 2387 else 2388 offset = 0; 2389 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer); 2390 va_offset += offset; 2391 2392 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ); 2393 2394 switch (shader) { 2395 case PIPE_SHADER_VERTEX: 2396 reg = R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_CONST * 4; 2397 si_pm4_set_reg(pm4, reg, va_offset); 2398 si_pm4_set_reg(pm4, reg + 4, va_offset >> 32); 2399 si_pm4_set_state(rctx, vs_const, pm4); 2400 break; 2401 2402 case PIPE_SHADER_FRAGMENT: 2403 reg = R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_CONST * 4; 2404 si_pm4_set_reg(pm4, reg, va_offset); 2405 si_pm4_set_reg(pm4, reg + 4, va_offset >> 32); 2406 si_pm4_set_state(rctx, ps_const, pm4); 2407 break; 2408 2409 default: 2410 R600_ERR("unsupported %d\n", shader); 2411 } 2412 2413 if (cb->buffer != &rbuffer->b.b) 2414 si_resource_reference(&rbuffer, NULL); 2415} 2416 2417/* 2418 * Vertex elements & buffers 2419 */ 2420 2421static void *si_create_vertex_elements(struct pipe_context *ctx, 2422 unsigned count, 2423 const struct pipe_vertex_element *elements) 2424{ 2425 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element); 2426 int i; 2427 2428 assert(count < PIPE_MAX_ATTRIBS); 2429 if (!v) 2430 return NULL; 2431 2432 v->count = count; 2433 for (i = 0; i < count; ++i) { 2434 const struct util_format_description *desc; 2435 unsigned data_format, num_format; 2436 int first_non_void; 2437 2438 desc = util_format_description(elements[i].src_format); 2439 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format); 2440 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format, 2441 desc, first_non_void); 2442 2443 switch (desc->channel[first_non_void].type) { 2444 case UTIL_FORMAT_TYPE_FIXED: 2445 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */ 2446 break; 2447 case UTIL_FORMAT_TYPE_SIGNED: 2448 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM; 2449 break; 2450 case UTIL_FORMAT_TYPE_UNSIGNED: 2451 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM; 2452 break; 2453 case UTIL_FORMAT_TYPE_FLOAT: 2454 default: 2455 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2456 } 2457 2458 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | 2459 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | 2460 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | 2461 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | 2462 S_008F0C_NUM_FORMAT(num_format) | 2463 S_008F0C_DATA_FORMAT(data_format); 2464 } 2465 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); 2466 2467 return v; 2468} 2469 2470static void si_bind_vertex_elements(struct pipe_context *ctx, void *state) 2471{ 2472 struct r600_context *rctx = (struct r600_context *)ctx; 2473 struct si_vertex_element *v = (struct si_vertex_element*)state; 2474 2475 rctx->vertex_elements = v; 2476} 2477 2478static void si_delete_vertex_element(struct pipe_context *ctx, void *state) 2479{ 2480 struct r600_context *rctx = (struct r600_context *)ctx; 2481 2482 if (rctx->vertex_elements == state) 2483 rctx->vertex_elements = NULL; 2484 FREE(state); 2485} 2486 2487static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count, 2488 const struct pipe_vertex_buffer *buffers) 2489{ 2490 struct r600_context *rctx = (struct r600_context *)ctx; 2491 2492 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count); 2493} 2494 2495static void si_set_index_buffer(struct pipe_context *ctx, 2496 const struct pipe_index_buffer *ib) 2497{ 2498 struct r600_context *rctx = (struct r600_context *)ctx; 2499 2500 if (ib) { 2501 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer); 2502 memcpy(&rctx->index_buffer, ib, sizeof(*ib)); 2503 } else { 2504 pipe_resource_reference(&rctx->index_buffer.buffer, NULL); 2505 } 2506} 2507 2508/* 2509 * Misc 2510 */ 2511static void si_set_polygon_stipple(struct pipe_context *ctx, 2512 const struct pipe_poly_stipple *state) 2513{ 2514} 2515 2516static void si_texture_barrier(struct pipe_context *ctx) 2517{ 2518 struct r600_context *rctx = (struct r600_context *)ctx; 2519 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2520 2521 si_pm4_inval_texture_cache(pm4); 2522 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs); 2523 si_pm4_set_state(rctx, texture_barrier, pm4); 2524} 2525 2526void si_init_state_functions(struct r600_context *rctx) 2527{ 2528 rctx->context.create_blend_state = si_create_blend_state; 2529 rctx->context.bind_blend_state = si_bind_blend_state; 2530 rctx->context.delete_blend_state = si_delete_blend_state; 2531 rctx->context.set_blend_color = si_set_blend_color; 2532 2533 rctx->context.create_rasterizer_state = si_create_rs_state; 2534 rctx->context.bind_rasterizer_state = si_bind_rs_state; 2535 rctx->context.delete_rasterizer_state = si_delete_rs_state; 2536 2537 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state; 2538 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state; 2539 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state; 2540 rctx->custom_dsa_flush = si_create_db_flush_dsa(rctx); 2541 2542 rctx->context.set_clip_state = si_set_clip_state; 2543 rctx->context.set_scissor_state = si_set_scissor_state; 2544 rctx->context.set_viewport_state = si_set_viewport_state; 2545 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref; 2546 2547 rctx->context.set_framebuffer_state = si_set_framebuffer_state; 2548 2549 rctx->context.create_vs_state = si_create_vs_state; 2550 rctx->context.create_fs_state = si_create_fs_state; 2551 rctx->context.bind_vs_state = si_bind_vs_shader; 2552 rctx->context.bind_fs_state = si_bind_ps_shader; 2553 rctx->context.delete_vs_state = si_delete_vs_shader; 2554 rctx->context.delete_fs_state = si_delete_ps_shader; 2555 2556 rctx->context.create_sampler_state = si_create_sampler_state; 2557 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler; 2558 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler; 2559 rctx->context.delete_sampler_state = si_delete_sampler_state; 2560 2561 rctx->context.create_sampler_view = si_create_sampler_view; 2562 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view; 2563 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view; 2564 rctx->context.sampler_view_destroy = si_sampler_view_destroy; 2565 2566 rctx->context.set_sample_mask = si_set_sample_mask; 2567 2568 rctx->context.set_constant_buffer = si_set_constant_buffer; 2569 2570 rctx->context.create_vertex_elements_state = si_create_vertex_elements; 2571 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements; 2572 rctx->context.delete_vertex_elements_state = si_delete_vertex_element; 2573 rctx->context.set_vertex_buffers = si_set_vertex_buffers; 2574 rctx->context.set_index_buffer = si_set_index_buffer; 2575 2576 rctx->context.create_stream_output_target = si_create_so_target; 2577 rctx->context.stream_output_target_destroy = si_so_target_destroy; 2578 rctx->context.set_stream_output_targets = si_set_so_targets; 2579 2580 rctx->context.texture_barrier = si_texture_barrier; 2581 rctx->context.set_polygon_stipple = si_set_polygon_stipple; 2582 2583 rctx->context.draw_vbo = si_draw_vbo; 2584} 2585 2586void si_init_config(struct r600_context *rctx) 2587{ 2588 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2589 2590 si_cmd_context_control(pm4); 2591 2592 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0); 2593 2594 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0); 2595 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0); 2596 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0); 2597 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0); 2598 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0); 2599 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0); 2600 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0); 2601 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0); 2602 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0); 2603 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0); 2604 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0); 2605 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0); 2606 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0); 2607 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0); 2608 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); 2609 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0); 2610 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); 2611 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, 2612 S_028AA8_SWITCH_ON_EOP(1) | 2613 S_028AA8_PARTIAL_VS_WAVE_ON(1) | 2614 S_028AA8_PRIMGROUP_SIZE(63)); 2615 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000); 2616 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); 2617 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | 2618 S_008A14_CLIP_VTX_REORDER_ENA(1)); 2619 2620 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0); 2621 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210); 2622 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98); 2623 2624 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000); 2625 2626 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0); 2627 2628 switch (rctx->screen->family) { 2629 case CHIP_TAHITI: 2630 case CHIP_PITCAIRN: 2631 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a); 2632 break; 2633 case CHIP_VERDE: 2634 default: 2635 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a); 2636 break; 2637 } 2638 2639 si_pm4_set_state(rctx, init, pm4); 2640} 2641