si_state.c revision cd9c07e7cdff5a38fd0de48626baecb5a9013846
1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Christian König <christian.koenig@amd.com> 25 */ 26 27#include "si_pipe.h" 28#include "si_shader.h" 29#include "sid.h" 30#include "radeon/r600_cs.h" 31 32#include "util/u_dual_blend.h" 33#include "util/u_format.h" 34#include "util/u_format_s3tc.h" 35#include "util/u_memory.h" 36#include "util/u_pstipple.h" 37 38/* Initialize an external atom (owned by ../radeon). */ 39static void 40si_init_external_atom(struct si_context *sctx, struct r600_atom *atom, 41 struct r600_atom **list_elem) 42{ 43 atom->id = list_elem - sctx->atoms.array + 1; 44 *list_elem = atom; 45} 46 47/* Initialize an atom owned by radeonsi. */ 48void si_init_atom(struct si_context *sctx, struct r600_atom *atom, 49 struct r600_atom **list_elem, 50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state)) 51{ 52 atom->emit = (void*)emit_func; 53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */ 54 *list_elem = atom; 55} 56 57unsigned si_array_mode(unsigned mode) 58{ 59 switch (mode) { 60 case RADEON_SURF_MODE_LINEAR_ALIGNED: 61 return V_009910_ARRAY_LINEAR_ALIGNED; 62 case RADEON_SURF_MODE_1D: 63 return V_009910_ARRAY_1D_TILED_THIN1; 64 case RADEON_SURF_MODE_2D: 65 return V_009910_ARRAY_2D_TILED_THIN1; 66 default: 67 case RADEON_SURF_MODE_LINEAR: 68 return V_009910_ARRAY_LINEAR_GENERAL; 69 } 70} 71 72uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex) 73{ 74 if (sscreen->b.chip_class >= CIK && 75 sscreen->b.info.cik_macrotile_mode_array_valid) { 76 unsigned index, tileb; 77 78 tileb = 8 * 8 * tex->surface.bpe; 79 tileb = MIN2(tex->surface.tile_split, tileb); 80 81 for (index = 0; tileb > 64; index++) { 82 tileb >>= 1; 83 } 84 assert(index < 16); 85 86 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3; 87 } 88 89 if (sscreen->b.chip_class == SI && 90 sscreen->b.info.si_tile_mode_array_valid) { 91 /* Don't use stencil_tiling_index, because num_banks is always 92 * read from the depth mode. */ 93 unsigned tile_mode_index = tex->surface.tiling_index[0]; 94 assert(tile_mode_index < 32); 95 96 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]); 97 } 98 99 /* The old way. */ 100 switch (sscreen->b.tiling_info.num_banks) { 101 case 2: 102 return V_02803C_ADDR_SURF_2_BANK; 103 case 4: 104 return V_02803C_ADDR_SURF_4_BANK; 105 case 8: 106 default: 107 return V_02803C_ADDR_SURF_8_BANK; 108 case 16: 109 return V_02803C_ADDR_SURF_16_BANK; 110 } 111} 112 113unsigned cik_tile_split(unsigned tile_split) 114{ 115 switch (tile_split) { 116 case 64: 117 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B; 118 break; 119 case 128: 120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B; 121 break; 122 case 256: 123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B; 124 break; 125 case 512: 126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B; 127 break; 128 default: 129 case 1024: 130 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB; 131 break; 132 case 2048: 133 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB; 134 break; 135 case 4096: 136 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB; 137 break; 138 } 139 return tile_split; 140} 141 142unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect) 143{ 144 switch (macro_tile_aspect) { 145 default: 146 case 1: 147 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1; 148 break; 149 case 2: 150 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2; 151 break; 152 case 4: 153 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4; 154 break; 155 case 8: 156 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8; 157 break; 158 } 159 return macro_tile_aspect; 160} 161 162unsigned cik_bank_wh(unsigned bankwh) 163{ 164 switch (bankwh) { 165 default: 166 case 1: 167 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1; 168 break; 169 case 2: 170 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2; 171 break; 172 case 4: 173 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4; 174 break; 175 case 8: 176 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8; 177 break; 178 } 179 return bankwh; 180} 181 182unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode) 183{ 184 if (sscreen->b.info.si_tile_mode_array_valid) { 185 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode]; 186 187 return G_009910_PIPE_CONFIG(gb_tile_mode); 188 } 189 190 /* This is probably broken for a lot of chips, but it's only used 191 * if the kernel cannot return the tile mode array for CIK. */ 192 switch (sscreen->b.info.r600_num_tile_pipes) { 193 case 16: 194 return V_02803C_X_ADDR_SURF_P16_32X32_16X16; 195 case 8: 196 return V_02803C_X_ADDR_SURF_P8_32X32_16X16; 197 case 4: 198 default: 199 if (sscreen->b.info.r600_num_backends == 4) 200 return V_02803C_X_ADDR_SURF_P4_16X16; 201 else 202 return V_02803C_X_ADDR_SURF_P4_8X16; 203 case 2: 204 return V_02803C_ADDR_SURF_P2; 205 } 206} 207 208static unsigned si_map_swizzle(unsigned swizzle) 209{ 210 switch (swizzle) { 211 case UTIL_FORMAT_SWIZZLE_Y: 212 return V_008F0C_SQ_SEL_Y; 213 case UTIL_FORMAT_SWIZZLE_Z: 214 return V_008F0C_SQ_SEL_Z; 215 case UTIL_FORMAT_SWIZZLE_W: 216 return V_008F0C_SQ_SEL_W; 217 case UTIL_FORMAT_SWIZZLE_0: 218 return V_008F0C_SQ_SEL_0; 219 case UTIL_FORMAT_SWIZZLE_1: 220 return V_008F0C_SQ_SEL_1; 221 default: /* UTIL_FORMAT_SWIZZLE_X */ 222 return V_008F0C_SQ_SEL_X; 223 } 224} 225 226static uint32_t S_FIXED(float value, uint32_t frac_bits) 227{ 228 return value * (1 << frac_bits); 229} 230 231/* 12.4 fixed-point */ 232static unsigned si_pack_float_12p4(float x) 233{ 234 return x <= 0 ? 0 : 235 x >= 4096 ? 0xffff : x * 16; 236} 237 238/* 239 * Inferred framebuffer and blender state. 240 * 241 * One of the reasons this must be derived from the framebuffer state is that: 242 * - The blend state mask is 0xf most of the time. 243 * - The COLOR1 format isn't INVALID because of possible dual-source blending, 244 * so COLOR1 is enabled pretty much all the time. 245 * So CB_TARGET_MASK is the only register that can disable COLOR1. 246 * 247 * Another reason is to avoid a hang with dual source blending. 248 */ 249static void si_emit_cb_target_mask(struct si_context *sctx, struct r600_atom *atom) 250{ 251 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 252 struct si_state_blend *blend = sctx->queued.named.blend; 253 uint32_t mask = 0, i; 254 255 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) 256 if (sctx->framebuffer.state.cbufs[i]) 257 mask |= 0xf << (4*i); 258 259 if (blend) 260 mask &= blend->cb_target_mask; 261 262 /* Avoid a hang that happens when dual source blending is enabled 263 * but there is not enough color outputs. This is undefined behavior, 264 * so disable color writes completely. 265 * 266 * Reproducible with Unigine Heaven 4.0 and drirc missing. 267 */ 268 if (blend && blend->dual_src_blend && 269 sctx->ps_shader.cso && 270 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3) 271 mask = 0; 272 273 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, mask); 274} 275 276/* 277 * Blender functions 278 */ 279 280static uint32_t si_translate_blend_function(int blend_func) 281{ 282 switch (blend_func) { 283 case PIPE_BLEND_ADD: 284 return V_028780_COMB_DST_PLUS_SRC; 285 case PIPE_BLEND_SUBTRACT: 286 return V_028780_COMB_SRC_MINUS_DST; 287 case PIPE_BLEND_REVERSE_SUBTRACT: 288 return V_028780_COMB_DST_MINUS_SRC; 289 case PIPE_BLEND_MIN: 290 return V_028780_COMB_MIN_DST_SRC; 291 case PIPE_BLEND_MAX: 292 return V_028780_COMB_MAX_DST_SRC; 293 default: 294 R600_ERR("Unknown blend function %d\n", blend_func); 295 assert(0); 296 break; 297 } 298 return 0; 299} 300 301static uint32_t si_translate_blend_factor(int blend_fact) 302{ 303 switch (blend_fact) { 304 case PIPE_BLENDFACTOR_ONE: 305 return V_028780_BLEND_ONE; 306 case PIPE_BLENDFACTOR_SRC_COLOR: 307 return V_028780_BLEND_SRC_COLOR; 308 case PIPE_BLENDFACTOR_SRC_ALPHA: 309 return V_028780_BLEND_SRC_ALPHA; 310 case PIPE_BLENDFACTOR_DST_ALPHA: 311 return V_028780_BLEND_DST_ALPHA; 312 case PIPE_BLENDFACTOR_DST_COLOR: 313 return V_028780_BLEND_DST_COLOR; 314 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 315 return V_028780_BLEND_SRC_ALPHA_SATURATE; 316 case PIPE_BLENDFACTOR_CONST_COLOR: 317 return V_028780_BLEND_CONSTANT_COLOR; 318 case PIPE_BLENDFACTOR_CONST_ALPHA: 319 return V_028780_BLEND_CONSTANT_ALPHA; 320 case PIPE_BLENDFACTOR_ZERO: 321 return V_028780_BLEND_ZERO; 322 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 323 return V_028780_BLEND_ONE_MINUS_SRC_COLOR; 324 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 325 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; 326 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 327 return V_028780_BLEND_ONE_MINUS_DST_ALPHA; 328 case PIPE_BLENDFACTOR_INV_DST_COLOR: 329 return V_028780_BLEND_ONE_MINUS_DST_COLOR; 330 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 331 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; 332 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 333 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; 334 case PIPE_BLENDFACTOR_SRC1_COLOR: 335 return V_028780_BLEND_SRC1_COLOR; 336 case PIPE_BLENDFACTOR_SRC1_ALPHA: 337 return V_028780_BLEND_SRC1_ALPHA; 338 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 339 return V_028780_BLEND_INV_SRC1_COLOR; 340 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 341 return V_028780_BLEND_INV_SRC1_ALPHA; 342 default: 343 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 344 assert(0); 345 break; 346 } 347 return 0; 348} 349 350static uint32_t si_translate_blend_opt_function(int blend_func) 351{ 352 switch (blend_func) { 353 case PIPE_BLEND_ADD: 354 return V_028760_OPT_COMB_ADD; 355 case PIPE_BLEND_SUBTRACT: 356 return V_028760_OPT_COMB_SUBTRACT; 357 case PIPE_BLEND_REVERSE_SUBTRACT: 358 return V_028760_OPT_COMB_REVSUBTRACT; 359 case PIPE_BLEND_MIN: 360 return V_028760_OPT_COMB_MIN; 361 case PIPE_BLEND_MAX: 362 return V_028760_OPT_COMB_MAX; 363 default: 364 return V_028760_OPT_COMB_BLEND_DISABLED; 365 } 366} 367 368static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha) 369{ 370 switch (blend_fact) { 371 case PIPE_BLENDFACTOR_ZERO: 372 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL; 373 case PIPE_BLENDFACTOR_ONE: 374 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE; 375 case PIPE_BLENDFACTOR_SRC_COLOR: 376 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0 377 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0; 378 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 379 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1 380 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1; 381 case PIPE_BLENDFACTOR_SRC_ALPHA: 382 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0; 383 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 384 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1; 385 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 386 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE 387 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0; 388 default: 389 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE; 390 } 391} 392 393static void *si_create_blend_state_mode(struct pipe_context *ctx, 394 const struct pipe_blend_state *state, 395 unsigned mode) 396{ 397 struct si_context *sctx = (struct si_context*)ctx; 398 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend); 399 struct si_pm4_state *pm4 = &blend->pm4; 400 401 uint32_t color_control = 0; 402 403 if (!blend) 404 return NULL; 405 406 blend->alpha_to_coverage = state->alpha_to_coverage; 407 blend->alpha_to_one = state->alpha_to_one; 408 blend->dual_src_blend = util_blend_state_is_dual(state, 0); 409 410 if (state->logicop_enable) { 411 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4)); 412 } else { 413 color_control |= S_028808_ROP3(0xcc); 414 } 415 416 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 417 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) | 418 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | 419 S_028B70_ALPHA_TO_MASK_OFFSET1(2) | 420 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | 421 S_028B70_ALPHA_TO_MASK_OFFSET3(2)); 422 423 if (state->alpha_to_coverage) 424 blend->need_src_alpha_4bit |= 0xf; 425 426 blend->cb_target_mask = 0; 427 for (int i = 0; i < 8; i++) { 428 /* state->rt entries > 0 only written if independent blending */ 429 const int j = state->independent_blend_enable ? i : 0; 430 431 unsigned eqRGB = state->rt[j].rgb_func; 432 unsigned srcRGB = state->rt[j].rgb_src_factor; 433 unsigned dstRGB = state->rt[j].rgb_dst_factor; 434 unsigned eqA = state->rt[j].alpha_func; 435 unsigned srcA = state->rt[j].alpha_src_factor; 436 unsigned dstA = state->rt[j].alpha_dst_factor; 437 438 unsigned blend_cntl = 0; 439 440 if (!state->rt[j].colormask) 441 continue; 442 443 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 444 blend->cb_target_mask |= state->rt[j].colormask << (4 * i); 445 446 if (!state->rt[j].blend_enable) { 447 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 448 continue; 449 } 450 451 blend_cntl |= S_028780_ENABLE(1); 452 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); 453 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); 454 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); 455 456 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 457 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); 458 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); 459 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); 460 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); 461 } 462 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 463 464 blend->blend_enable_4bit |= 0xf << (i * 4); 465 466 /* This is only important for formats without alpha. */ 467 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 468 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 469 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 470 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 471 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 472 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA) 473 blend->need_src_alpha_4bit |= 0xf << (i * 4); 474 } 475 476 if (blend->cb_target_mask) { 477 color_control |= S_028808_MODE(mode); 478 } else { 479 color_control |= S_028808_MODE(V_028808_CB_DISABLE); 480 } 481 482 if (sctx->b.family == CHIP_STONEY) { 483 uint32_t sx_blend_opt_control = 0; 484 485 for (int i = 0; i < 8; i++) { 486 const int j = state->independent_blend_enable ? i : 0; 487 488 /* TODO: We can also set this if the surface doesn't contain RGB. */ 489 if (!state->rt[j].blend_enable || 490 !(state->rt[j].colormask & (PIPE_MASK_R | PIPE_MASK_G | PIPE_MASK_B))) 491 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (4 * i); 492 493 /* TODO: We can also set this if the surface doesn't contain alpha. */ 494 if (!state->rt[j].blend_enable || 495 !(state->rt[j].colormask & PIPE_MASK_A)) 496 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (4 * i); 497 498 if (!state->rt[j].blend_enable) { 499 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, 500 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | 501 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED)); 502 continue; 503 } 504 505 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, 506 S_028760_COLOR_SRC_OPT(si_translate_blend_opt_factor(state->rt[j].rgb_src_factor, false)) | 507 S_028760_COLOR_DST_OPT(si_translate_blend_opt_factor(state->rt[j].rgb_dst_factor, false)) | 508 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(state->rt[j].rgb_func)) | 509 S_028760_ALPHA_SRC_OPT(si_translate_blend_opt_factor(state->rt[j].alpha_src_factor, true)) | 510 S_028760_ALPHA_DST_OPT(si_translate_blend_opt_factor(state->rt[j].alpha_dst_factor, true)) | 511 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(state->rt[j].alpha_func))); 512 } 513 514 si_pm4_set_reg(pm4, R_02875C_SX_BLEND_OPT_CONTROL, sx_blend_opt_control); 515 516 /* RB+ doesn't work with dual source blending */ 517 if (blend->dual_src_blend) 518 color_control |= S_028808_DISABLE_DUAL_QUAD(1); 519 } 520 521 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); 522 return blend; 523} 524 525static void *si_create_blend_state(struct pipe_context *ctx, 526 const struct pipe_blend_state *state) 527{ 528 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL); 529} 530 531static void si_bind_blend_state(struct pipe_context *ctx, void *state) 532{ 533 struct si_context *sctx = (struct si_context *)ctx; 534 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state); 535 si_mark_atom_dirty(sctx, &sctx->cb_target_mask); 536} 537 538static void si_delete_blend_state(struct pipe_context *ctx, void *state) 539{ 540 struct si_context *sctx = (struct si_context *)ctx; 541 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state); 542} 543 544static void si_set_blend_color(struct pipe_context *ctx, 545 const struct pipe_blend_color *state) 546{ 547 struct si_context *sctx = (struct si_context *)ctx; 548 549 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0) 550 return; 551 552 sctx->blend_color.state = *state; 553 si_mark_atom_dirty(sctx, &sctx->blend_color.atom); 554} 555 556static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom) 557{ 558 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 559 560 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4); 561 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4); 562} 563 564/* 565 * Clipping, scissors and viewport 566 */ 567 568static void si_set_clip_state(struct pipe_context *ctx, 569 const struct pipe_clip_state *state) 570{ 571 struct si_context *sctx = (struct si_context *)ctx; 572 struct pipe_constant_buffer cb; 573 574 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0) 575 return; 576 577 sctx->clip_state.state = *state; 578 si_mark_atom_dirty(sctx, &sctx->clip_state.atom); 579 580 cb.buffer = NULL; 581 cb.user_buffer = state->ucp; 582 cb.buffer_offset = 0; 583 cb.buffer_size = 4*4*8; 584 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb); 585 pipe_resource_reference(&cb.buffer, NULL); 586} 587 588static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom) 589{ 590 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 591 592 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4); 593 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4); 594} 595 596#define SIX_BITS 0x3F 597 598static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom) 599{ 600 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 601 struct tgsi_shader_info *info = si_get_vs_info(sctx); 602 unsigned window_space = 603 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION]; 604 unsigned clipdist_mask = 605 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask; 606 607 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL, 608 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) | 609 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) | 610 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) | 611 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) | 612 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) | 613 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) | 614 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize || 615 info->writes_edgeflag || 616 info->writes_layer || 617 info->writes_viewport_index) | 618 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) | 619 (sctx->queued.named.rasterizer->clip_plane_enable & 620 clipdist_mask)); 621 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, 622 sctx->queued.named.rasterizer->pa_cl_clip_cntl | 623 (clipdist_mask ? 0 : 624 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) | 625 S_028810_CLIP_DISABLE(window_space)); 626 627 /* reuse needs to be set off if we write oViewport */ 628 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF, 629 S_028AB4_REUSE_OFF(info->writes_viewport_index)); 630} 631 632static void si_set_scissor_states(struct pipe_context *ctx, 633 unsigned start_slot, 634 unsigned num_scissors, 635 const struct pipe_scissor_state *state) 636{ 637 struct si_context *sctx = (struct si_context *)ctx; 638 int i; 639 640 for (i = 0; i < num_scissors; i++) 641 sctx->scissors.states[start_slot + i] = state[i]; 642 643 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot; 644 si_mark_atom_dirty(sctx, &sctx->scissors.atom); 645} 646 647static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom) 648{ 649 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 650 struct pipe_scissor_state *states = sctx->scissors.states; 651 unsigned mask = sctx->scissors.dirty_mask; 652 653 /* The simple case: Only 1 viewport is active. */ 654 if (mask & 1 && 655 !si_get_vs_info(sctx)->writes_viewport_index) { 656 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2); 657 radeon_emit(cs, S_028250_TL_X(states[0].minx) | 658 S_028250_TL_Y(states[0].miny) | 659 S_028250_WINDOW_OFFSET_DISABLE(1)); 660 radeon_emit(cs, S_028254_BR_X(states[0].maxx) | 661 S_028254_BR_Y(states[0].maxy)); 662 sctx->scissors.dirty_mask &= ~1; /* clear one bit */ 663 return; 664 } 665 666 while (mask) { 667 int start, count, i; 668 669 u_bit_scan_consecutive_range(&mask, &start, &count); 670 671 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + 672 start * 4 * 2, count * 2); 673 for (i = start; i < start+count; i++) { 674 radeon_emit(cs, S_028250_TL_X(states[i].minx) | 675 S_028250_TL_Y(states[i].miny) | 676 S_028250_WINDOW_OFFSET_DISABLE(1)); 677 radeon_emit(cs, S_028254_BR_X(states[i].maxx) | 678 S_028254_BR_Y(states[i].maxy)); 679 } 680 } 681 sctx->scissors.dirty_mask = 0; 682} 683 684static void si_set_viewport_states(struct pipe_context *ctx, 685 unsigned start_slot, 686 unsigned num_viewports, 687 const struct pipe_viewport_state *state) 688{ 689 struct si_context *sctx = (struct si_context *)ctx; 690 int i; 691 692 for (i = 0; i < num_viewports; i++) 693 sctx->viewports.states[start_slot + i] = state[i]; 694 695 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot; 696 si_mark_atom_dirty(sctx, &sctx->viewports.atom); 697} 698 699static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom) 700{ 701 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 702 struct pipe_viewport_state *states = sctx->viewports.states; 703 unsigned mask = sctx->viewports.dirty_mask; 704 705 /* The simple case: Only 1 viewport is active. */ 706 if (mask & 1 && 707 !si_get_vs_info(sctx)->writes_viewport_index) { 708 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6); 709 radeon_emit(cs, fui(states[0].scale[0])); 710 radeon_emit(cs, fui(states[0].translate[0])); 711 radeon_emit(cs, fui(states[0].scale[1])); 712 radeon_emit(cs, fui(states[0].translate[1])); 713 radeon_emit(cs, fui(states[0].scale[2])); 714 radeon_emit(cs, fui(states[0].translate[2])); 715 sctx->viewports.dirty_mask &= ~1; /* clear one bit */ 716 return; 717 } 718 719 while (mask) { 720 int start, count, i; 721 722 u_bit_scan_consecutive_range(&mask, &start, &count); 723 724 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE + 725 start * 4 * 6, count * 6); 726 for (i = start; i < start+count; i++) { 727 radeon_emit(cs, fui(states[i].scale[0])); 728 radeon_emit(cs, fui(states[i].translate[0])); 729 radeon_emit(cs, fui(states[i].scale[1])); 730 radeon_emit(cs, fui(states[i].translate[1])); 731 radeon_emit(cs, fui(states[i].scale[2])); 732 radeon_emit(cs, fui(states[i].translate[2])); 733 } 734 } 735 sctx->viewports.dirty_mask = 0; 736} 737 738/* 739 * inferred state between framebuffer and rasterizer 740 */ 741static void si_update_poly_offset_state(struct si_context *sctx) 742{ 743 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 744 745 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) 746 return; 747 748 switch (sctx->framebuffer.state.zsbuf->texture->format) { 749 case PIPE_FORMAT_Z16_UNORM: 750 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]); 751 break; 752 default: /* 24-bit */ 753 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]); 754 break; 755 case PIPE_FORMAT_Z32_FLOAT: 756 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 757 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]); 758 break; 759 } 760} 761 762/* 763 * Rasterizer 764 */ 765 766static uint32_t si_translate_fill(uint32_t func) 767{ 768 switch(func) { 769 case PIPE_POLYGON_MODE_FILL: 770 return V_028814_X_DRAW_TRIANGLES; 771 case PIPE_POLYGON_MODE_LINE: 772 return V_028814_X_DRAW_LINES; 773 case PIPE_POLYGON_MODE_POINT: 774 return V_028814_X_DRAW_POINTS; 775 default: 776 assert(0); 777 return V_028814_X_DRAW_POINTS; 778 } 779} 780 781static void *si_create_rs_state(struct pipe_context *ctx, 782 const struct pipe_rasterizer_state *state) 783{ 784 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer); 785 struct si_pm4_state *pm4 = &rs->pm4; 786 unsigned tmp, i; 787 float psize_min, psize_max; 788 789 if (!rs) { 790 return NULL; 791 } 792 793 rs->two_side = state->light_twoside; 794 rs->multisample_enable = state->multisample; 795 rs->force_persample_interp = state->force_persample_interp; 796 rs->clip_plane_enable = state->clip_plane_enable; 797 rs->line_stipple_enable = state->line_stipple_enable; 798 rs->poly_stipple_enable = state->poly_stipple_enable; 799 rs->line_smooth = state->line_smooth; 800 rs->poly_smooth = state->poly_smooth; 801 rs->uses_poly_offset = state->offset_point || state->offset_line || 802 state->offset_tri; 803 rs->clamp_fragment_color = state->clamp_fragment_color; 804 rs->flatshade = state->flatshade; 805 rs->sprite_coord_enable = state->sprite_coord_enable; 806 rs->rasterizer_discard = state->rasterizer_discard; 807 rs->pa_sc_line_stipple = state->line_stipple_enable ? 808 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 809 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 810 rs->pa_cl_clip_cntl = 811 S_028810_PS_UCP_MODE(3) | 812 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) | 813 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 814 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 815 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) | 816 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 817 818 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, 819 S_0286D4_FLAT_SHADE_ENA(1) | 820 S_0286D4_PNT_SPRITE_ENA(1) | 821 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | 822 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | 823 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | 824 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) | 825 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT)); 826 827 /* point size 12.4 fixed point */ 828 tmp = (unsigned)(state->point_size * 8.0); 829 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 830 831 if (state->point_size_per_vertex) { 832 psize_min = util_get_min_point_size(state); 833 psize_max = 8192; 834 } else { 835 /* Force the point size to be as if the vertex output was disabled. */ 836 psize_min = state->point_size; 837 psize_max = state->point_size; 838 } 839 /* Divide by two, because 0.5 = 1 pixel. */ 840 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX, 841 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) | 842 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2))); 843 844 tmp = (unsigned)state->line_width * 8; 845 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); 846 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0, 847 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) | 848 S_028A48_MSAA_ENABLE(state->multisample || 849 state->poly_smooth || 850 state->line_smooth) | 851 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor)); 852 853 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL, 854 S_028BE4_PIX_CENTER(state->half_pixel_center) | 855 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH)); 856 857 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 858 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, 859 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) | 860 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 861 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 862 S_028814_FACE(!state->front_ccw) | 863 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) | 864 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) | 865 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) | 866 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL || 867 state->fill_back != PIPE_POLYGON_MODE_FILL) | 868 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | 869 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back))); 870 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 + 871 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color); 872 873 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */ 874 for (i = 0; i < 3; i++) { 875 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i]; 876 float offset_units = state->offset_units; 877 float offset_scale = state->offset_scale * 16.0f; 878 879 switch (i) { 880 case 0: /* 16-bit zbuffer */ 881 offset_units *= 4.0f; 882 break; 883 case 1: /* 24-bit zbuffer */ 884 offset_units *= 2.0f; 885 break; 886 case 2: /* 32-bit zbuffer */ 887 offset_units *= 1.0f; 888 break; 889 } 890 891 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 892 fui(offset_scale)); 893 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 894 fui(offset_units)); 895 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 896 fui(offset_scale)); 897 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 898 fui(offset_units)); 899 } 900 901 return rs; 902} 903 904static void si_bind_rs_state(struct pipe_context *ctx, void *state) 905{ 906 struct si_context *sctx = (struct si_context *)ctx; 907 struct si_state_rasterizer *old_rs = 908 (struct si_state_rasterizer*)sctx->queued.named.rasterizer; 909 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state; 910 911 if (!state) 912 return; 913 914 if (sctx->framebuffer.nr_samples > 1 && 915 (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) 916 si_mark_atom_dirty(sctx, &sctx->db_render_state); 917 918 si_pm4_bind_state(sctx, rasterizer, rs); 919 si_update_poly_offset_state(sctx); 920 921 si_mark_atom_dirty(sctx, &sctx->clip_regs); 922} 923 924static void si_delete_rs_state(struct pipe_context *ctx, void *state) 925{ 926 struct si_context *sctx = (struct si_context *)ctx; 927 928 if (sctx->queued.named.rasterizer == state) 929 si_pm4_bind_state(sctx, poly_offset, NULL); 930 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state); 931} 932 933/* 934 * infeered state between dsa and stencil ref 935 */ 936static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom) 937{ 938 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 939 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state; 940 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part; 941 942 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2); 943 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) | 944 S_028430_STENCILMASK(dsa->valuemask[0]) | 945 S_028430_STENCILWRITEMASK(dsa->writemask[0]) | 946 S_028430_STENCILOPVAL(1)); 947 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) | 948 S_028434_STENCILMASK_BF(dsa->valuemask[1]) | 949 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) | 950 S_028434_STENCILOPVAL_BF(1)); 951} 952 953static void si_set_stencil_ref(struct pipe_context *ctx, 954 const struct pipe_stencil_ref *state) 955{ 956 struct si_context *sctx = (struct si_context *)ctx; 957 958 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0) 959 return; 960 961 sctx->stencil_ref.state = *state; 962 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom); 963} 964 965 966/* 967 * DSA 968 */ 969 970static uint32_t si_translate_stencil_op(int s_op) 971{ 972 switch (s_op) { 973 case PIPE_STENCIL_OP_KEEP: 974 return V_02842C_STENCIL_KEEP; 975 case PIPE_STENCIL_OP_ZERO: 976 return V_02842C_STENCIL_ZERO; 977 case PIPE_STENCIL_OP_REPLACE: 978 return V_02842C_STENCIL_REPLACE_TEST; 979 case PIPE_STENCIL_OP_INCR: 980 return V_02842C_STENCIL_ADD_CLAMP; 981 case PIPE_STENCIL_OP_DECR: 982 return V_02842C_STENCIL_SUB_CLAMP; 983 case PIPE_STENCIL_OP_INCR_WRAP: 984 return V_02842C_STENCIL_ADD_WRAP; 985 case PIPE_STENCIL_OP_DECR_WRAP: 986 return V_02842C_STENCIL_SUB_WRAP; 987 case PIPE_STENCIL_OP_INVERT: 988 return V_02842C_STENCIL_INVERT; 989 default: 990 R600_ERR("Unknown stencil op %d", s_op); 991 assert(0); 992 break; 993 } 994 return 0; 995} 996 997static void *si_create_dsa_state(struct pipe_context *ctx, 998 const struct pipe_depth_stencil_alpha_state *state) 999{ 1000 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa); 1001 struct si_pm4_state *pm4 = &dsa->pm4; 1002 unsigned db_depth_control; 1003 uint32_t db_stencil_control = 0; 1004 1005 if (!dsa) { 1006 return NULL; 1007 } 1008 1009 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask; 1010 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask; 1011 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask; 1012 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask; 1013 1014 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 1015 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 1016 S_028800_ZFUNC(state->depth.func) | 1017 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test); 1018 1019 /* stencil */ 1020 if (state->stencil[0].enabled) { 1021 db_depth_control |= S_028800_STENCIL_ENABLE(1); 1022 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); 1023 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op)); 1024 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op)); 1025 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op)); 1026 1027 if (state->stencil[1].enabled) { 1028 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 1029 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); 1030 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op)); 1031 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op)); 1032 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op)); 1033 } 1034 } 1035 1036 /* alpha */ 1037 if (state->alpha.enabled) { 1038 dsa->alpha_func = state->alpha.func; 1039 1040 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 + 1041 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value)); 1042 } else { 1043 dsa->alpha_func = PIPE_FUNC_ALWAYS; 1044 } 1045 1046 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); 1047 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); 1048 if (state->depth.bounds_test) { 1049 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min)); 1050 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max)); 1051 } 1052 1053 return dsa; 1054} 1055 1056static void si_bind_dsa_state(struct pipe_context *ctx, void *state) 1057{ 1058 struct si_context *sctx = (struct si_context *)ctx; 1059 struct si_state_dsa *dsa = state; 1060 1061 if (!state) 1062 return; 1063 1064 si_pm4_bind_state(sctx, dsa, dsa); 1065 1066 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part, 1067 sizeof(struct si_dsa_stencil_ref_part)) != 0) { 1068 sctx->stencil_ref.dsa_part = dsa->stencil_ref; 1069 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom); 1070 } 1071} 1072 1073static void si_delete_dsa_state(struct pipe_context *ctx, void *state) 1074{ 1075 struct si_context *sctx = (struct si_context *)ctx; 1076 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state); 1077} 1078 1079static void *si_create_db_flush_dsa(struct si_context *sctx) 1080{ 1081 struct pipe_depth_stencil_alpha_state dsa = {}; 1082 1083 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa); 1084} 1085 1086/* DB RENDER STATE */ 1087 1088static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable) 1089{ 1090 struct si_context *sctx = (struct si_context*)ctx; 1091 1092 si_mark_atom_dirty(sctx, &sctx->db_render_state); 1093} 1094 1095static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state) 1096{ 1097 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 1098 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; 1099 unsigned db_shader_control; 1100 1101 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2); 1102 1103 /* DB_RENDER_CONTROL */ 1104 if (sctx->dbcb_depth_copy_enabled || 1105 sctx->dbcb_stencil_copy_enabled) { 1106 radeon_emit(cs, 1107 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) | 1108 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) | 1109 S_028000_COPY_CENTROID(1) | 1110 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample)); 1111 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) { 1112 radeon_emit(cs, 1113 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) | 1114 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace)); 1115 } else { 1116 radeon_emit(cs, 1117 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) | 1118 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear)); 1119 } 1120 1121 /* DB_COUNT_CONTROL (occlusion queries) */ 1122 if (sctx->b.num_occlusion_queries > 0) { 1123 if (sctx->b.chip_class >= CIK) { 1124 radeon_emit(cs, 1125 S_028004_PERFECT_ZPASS_COUNTS(1) | 1126 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) | 1127 S_028004_ZPASS_ENABLE(1) | 1128 S_028004_SLICE_EVEN_ENABLE(1) | 1129 S_028004_SLICE_ODD_ENABLE(1)); 1130 } else { 1131 radeon_emit(cs, 1132 S_028004_PERFECT_ZPASS_COUNTS(1) | 1133 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples)); 1134 } 1135 } else { 1136 /* Disable occlusion queries. */ 1137 if (sctx->b.chip_class >= CIK) { 1138 radeon_emit(cs, 0); 1139 } else { 1140 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1)); 1141 } 1142 } 1143 1144 /* DB_RENDER_OVERRIDE2 */ 1145 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 1146 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) | 1147 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear)); 1148 1149 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) | 1150 sctx->ps_db_shader_control; 1151 1152 /* Bug workaround for smoothing (overrasterization) on SI. */ 1153 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) 1154 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z); 1155 else 1156 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 1157 1158 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */ 1159 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable)) 1160 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE; 1161 1162 if (sctx->b.family == CHIP_STONEY && 1163 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) 1164 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1); 1165 1166 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, 1167 db_shader_control); 1168} 1169 1170/* 1171 * format translation 1172 */ 1173static uint32_t si_translate_colorformat(enum pipe_format format) 1174{ 1175 const struct util_format_description *desc = util_format_description(format); 1176 1177#define HAS_SIZE(x,y,z,w) \ 1178 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \ 1179 desc->channel[2].size == (z) && desc->channel[3].size == (w)) 1180 1181 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ 1182 return V_028C70_COLOR_10_11_11; 1183 1184 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) 1185 return V_028C70_COLOR_INVALID; 1186 1187 switch (desc->nr_channels) { 1188 case 1: 1189 switch (desc->channel[0].size) { 1190 case 8: 1191 return V_028C70_COLOR_8; 1192 case 16: 1193 return V_028C70_COLOR_16; 1194 case 32: 1195 return V_028C70_COLOR_32; 1196 } 1197 break; 1198 case 2: 1199 if (desc->channel[0].size == desc->channel[1].size) { 1200 switch (desc->channel[0].size) { 1201 case 8: 1202 return V_028C70_COLOR_8_8; 1203 case 16: 1204 return V_028C70_COLOR_16_16; 1205 case 32: 1206 return V_028C70_COLOR_32_32; 1207 } 1208 } else if (HAS_SIZE(8,24,0,0)) { 1209 return V_028C70_COLOR_24_8; 1210 } else if (HAS_SIZE(24,8,0,0)) { 1211 return V_028C70_COLOR_8_24; 1212 } 1213 break; 1214 case 3: 1215 if (HAS_SIZE(5,6,5,0)) { 1216 return V_028C70_COLOR_5_6_5; 1217 } else if (HAS_SIZE(32,8,24,0)) { 1218 return V_028C70_COLOR_X24_8_32_FLOAT; 1219 } 1220 break; 1221 case 4: 1222 if (desc->channel[0].size == desc->channel[1].size && 1223 desc->channel[0].size == desc->channel[2].size && 1224 desc->channel[0].size == desc->channel[3].size) { 1225 switch (desc->channel[0].size) { 1226 case 4: 1227 return V_028C70_COLOR_4_4_4_4; 1228 case 8: 1229 return V_028C70_COLOR_8_8_8_8; 1230 case 16: 1231 return V_028C70_COLOR_16_16_16_16; 1232 case 32: 1233 return V_028C70_COLOR_32_32_32_32; 1234 } 1235 } else if (HAS_SIZE(5,5,5,1)) { 1236 return V_028C70_COLOR_1_5_5_5; 1237 } else if (HAS_SIZE(10,10,10,2)) { 1238 return V_028C70_COLOR_2_10_10_10; 1239 } 1240 break; 1241 } 1242 return V_028C70_COLOR_INVALID; 1243} 1244 1245static uint32_t si_colorformat_endian_swap(uint32_t colorformat) 1246{ 1247 if (SI_BIG_ENDIAN) { 1248 switch(colorformat) { 1249 /* 8-bit buffers. */ 1250 case V_028C70_COLOR_8: 1251 return V_028C70_ENDIAN_NONE; 1252 1253 /* 16-bit buffers. */ 1254 case V_028C70_COLOR_5_6_5: 1255 case V_028C70_COLOR_1_5_5_5: 1256 case V_028C70_COLOR_4_4_4_4: 1257 case V_028C70_COLOR_16: 1258 case V_028C70_COLOR_8_8: 1259 return V_028C70_ENDIAN_8IN16; 1260 1261 /* 32-bit buffers. */ 1262 case V_028C70_COLOR_8_8_8_8: 1263 case V_028C70_COLOR_2_10_10_10: 1264 case V_028C70_COLOR_8_24: 1265 case V_028C70_COLOR_24_8: 1266 case V_028C70_COLOR_16_16: 1267 return V_028C70_ENDIAN_8IN32; 1268 1269 /* 64-bit buffers. */ 1270 case V_028C70_COLOR_16_16_16_16: 1271 return V_028C70_ENDIAN_8IN16; 1272 1273 case V_028C70_COLOR_32_32: 1274 return V_028C70_ENDIAN_8IN32; 1275 1276 /* 128-bit buffers. */ 1277 case V_028C70_COLOR_32_32_32_32: 1278 return V_028C70_ENDIAN_8IN32; 1279 default: 1280 return V_028C70_ENDIAN_NONE; /* Unsupported. */ 1281 } 1282 } else { 1283 return V_028C70_ENDIAN_NONE; 1284 } 1285} 1286 1287static uint32_t si_translate_dbformat(enum pipe_format format) 1288{ 1289 switch (format) { 1290 case PIPE_FORMAT_Z16_UNORM: 1291 return V_028040_Z_16; 1292 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1293 case PIPE_FORMAT_X8Z24_UNORM: 1294 case PIPE_FORMAT_Z24X8_UNORM: 1295 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1296 return V_028040_Z_24; /* deprecated on SI */ 1297 case PIPE_FORMAT_Z32_FLOAT: 1298 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1299 return V_028040_Z_32_FLOAT; 1300 default: 1301 return V_028040_Z_INVALID; 1302 } 1303} 1304 1305/* 1306 * Texture translation 1307 */ 1308 1309static uint32_t si_translate_texformat(struct pipe_screen *screen, 1310 enum pipe_format format, 1311 const struct util_format_description *desc, 1312 int first_non_void) 1313{ 1314 struct si_screen *sscreen = (struct si_screen*)screen; 1315 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 && 1316 sscreen->b.info.drm_minor >= 31) || 1317 sscreen->b.info.drm_major == 3; 1318 boolean uniform = TRUE; 1319 int i; 1320 1321 /* Colorspace (return non-RGB formats directly). */ 1322 switch (desc->colorspace) { 1323 /* Depth stencil formats */ 1324 case UTIL_FORMAT_COLORSPACE_ZS: 1325 switch (format) { 1326 case PIPE_FORMAT_Z16_UNORM: 1327 return V_008F14_IMG_DATA_FORMAT_16; 1328 case PIPE_FORMAT_X24S8_UINT: 1329 case PIPE_FORMAT_Z24X8_UNORM: 1330 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1331 return V_008F14_IMG_DATA_FORMAT_8_24; 1332 case PIPE_FORMAT_X8Z24_UNORM: 1333 case PIPE_FORMAT_S8X24_UINT: 1334 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1335 return V_008F14_IMG_DATA_FORMAT_24_8; 1336 case PIPE_FORMAT_S8_UINT: 1337 return V_008F14_IMG_DATA_FORMAT_8; 1338 case PIPE_FORMAT_Z32_FLOAT: 1339 return V_008F14_IMG_DATA_FORMAT_32; 1340 case PIPE_FORMAT_X32_S8X24_UINT: 1341 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1342 return V_008F14_IMG_DATA_FORMAT_X24_8_32; 1343 default: 1344 goto out_unknown; 1345 } 1346 1347 case UTIL_FORMAT_COLORSPACE_YUV: 1348 goto out_unknown; /* TODO */ 1349 1350 case UTIL_FORMAT_COLORSPACE_SRGB: 1351 if (desc->nr_channels != 4 && desc->nr_channels != 1) 1352 goto out_unknown; 1353 break; 1354 1355 default: 1356 break; 1357 } 1358 1359 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 1360 if (!enable_compressed_formats) 1361 goto out_unknown; 1362 1363 switch (format) { 1364 case PIPE_FORMAT_RGTC1_SNORM: 1365 case PIPE_FORMAT_LATC1_SNORM: 1366 case PIPE_FORMAT_RGTC1_UNORM: 1367 case PIPE_FORMAT_LATC1_UNORM: 1368 return V_008F14_IMG_DATA_FORMAT_BC4; 1369 case PIPE_FORMAT_RGTC2_SNORM: 1370 case PIPE_FORMAT_LATC2_SNORM: 1371 case PIPE_FORMAT_RGTC2_UNORM: 1372 case PIPE_FORMAT_LATC2_UNORM: 1373 return V_008F14_IMG_DATA_FORMAT_BC5; 1374 default: 1375 goto out_unknown; 1376 } 1377 } 1378 1379 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC && 1380 sscreen->b.family >= CHIP_STONEY) { 1381 switch (format) { 1382 case PIPE_FORMAT_ETC1_RGB8: 1383 case PIPE_FORMAT_ETC2_RGB8: 1384 case PIPE_FORMAT_ETC2_SRGB8: 1385 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB; 1386 case PIPE_FORMAT_ETC2_RGB8A1: 1387 case PIPE_FORMAT_ETC2_SRGB8A1: 1388 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1; 1389 case PIPE_FORMAT_ETC2_RGBA8: 1390 case PIPE_FORMAT_ETC2_SRGBA8: 1391 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA; 1392 case PIPE_FORMAT_ETC2_R11_UNORM: 1393 case PIPE_FORMAT_ETC2_R11_SNORM: 1394 return V_008F14_IMG_DATA_FORMAT_ETC2_R; 1395 case PIPE_FORMAT_ETC2_RG11_UNORM: 1396 case PIPE_FORMAT_ETC2_RG11_SNORM: 1397 return V_008F14_IMG_DATA_FORMAT_ETC2_RG; 1398 default: 1399 goto out_unknown; 1400 } 1401 } 1402 1403 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) { 1404 if (!enable_compressed_formats) 1405 goto out_unknown; 1406 1407 switch (format) { 1408 case PIPE_FORMAT_BPTC_RGBA_UNORM: 1409 case PIPE_FORMAT_BPTC_SRGBA: 1410 return V_008F14_IMG_DATA_FORMAT_BC7; 1411 case PIPE_FORMAT_BPTC_RGB_FLOAT: 1412 case PIPE_FORMAT_BPTC_RGB_UFLOAT: 1413 return V_008F14_IMG_DATA_FORMAT_BC6; 1414 default: 1415 goto out_unknown; 1416 } 1417 } 1418 1419 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) { 1420 switch (format) { 1421 case PIPE_FORMAT_R8G8_B8G8_UNORM: 1422 case PIPE_FORMAT_G8R8_B8R8_UNORM: 1423 return V_008F14_IMG_DATA_FORMAT_GB_GR; 1424 case PIPE_FORMAT_G8R8_G8B8_UNORM: 1425 case PIPE_FORMAT_R8G8_R8B8_UNORM: 1426 return V_008F14_IMG_DATA_FORMAT_BG_RG; 1427 default: 1428 goto out_unknown; 1429 } 1430 } 1431 1432 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 1433 if (!enable_compressed_formats) 1434 goto out_unknown; 1435 1436 if (!util_format_s3tc_enabled) { 1437 goto out_unknown; 1438 } 1439 1440 switch (format) { 1441 case PIPE_FORMAT_DXT1_RGB: 1442 case PIPE_FORMAT_DXT1_RGBA: 1443 case PIPE_FORMAT_DXT1_SRGB: 1444 case PIPE_FORMAT_DXT1_SRGBA: 1445 return V_008F14_IMG_DATA_FORMAT_BC1; 1446 case PIPE_FORMAT_DXT3_RGBA: 1447 case PIPE_FORMAT_DXT3_SRGBA: 1448 return V_008F14_IMG_DATA_FORMAT_BC2; 1449 case PIPE_FORMAT_DXT5_RGBA: 1450 case PIPE_FORMAT_DXT5_SRGBA: 1451 return V_008F14_IMG_DATA_FORMAT_BC3; 1452 default: 1453 goto out_unknown; 1454 } 1455 } 1456 1457 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 1458 return V_008F14_IMG_DATA_FORMAT_5_9_9_9; 1459 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 1460 return V_008F14_IMG_DATA_FORMAT_10_11_11; 1461 } 1462 1463 /* R8G8Bx_SNORM - TODO CxV8U8 */ 1464 1465 /* See whether the components are of the same size. */ 1466 for (i = 1; i < desc->nr_channels; i++) { 1467 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1468 } 1469 1470 /* Non-uniform formats. */ 1471 if (!uniform) { 1472 switch(desc->nr_channels) { 1473 case 3: 1474 if (desc->channel[0].size == 5 && 1475 desc->channel[1].size == 6 && 1476 desc->channel[2].size == 5) { 1477 return V_008F14_IMG_DATA_FORMAT_5_6_5; 1478 } 1479 goto out_unknown; 1480 case 4: 1481 if (desc->channel[0].size == 5 && 1482 desc->channel[1].size == 5 && 1483 desc->channel[2].size == 5 && 1484 desc->channel[3].size == 1) { 1485 return V_008F14_IMG_DATA_FORMAT_1_5_5_5; 1486 } 1487 if (desc->channel[0].size == 10 && 1488 desc->channel[1].size == 10 && 1489 desc->channel[2].size == 10 && 1490 desc->channel[3].size == 2) { 1491 return V_008F14_IMG_DATA_FORMAT_2_10_10_10; 1492 } 1493 goto out_unknown; 1494 } 1495 goto out_unknown; 1496 } 1497 1498 if (first_non_void < 0 || first_non_void > 3) 1499 goto out_unknown; 1500 1501 /* uniform formats */ 1502 switch (desc->channel[first_non_void].size) { 1503 case 4: 1504 switch (desc->nr_channels) { 1505#if 0 /* Not supported for render targets */ 1506 case 2: 1507 return V_008F14_IMG_DATA_FORMAT_4_4; 1508#endif 1509 case 4: 1510 return V_008F14_IMG_DATA_FORMAT_4_4_4_4; 1511 } 1512 break; 1513 case 8: 1514 switch (desc->nr_channels) { 1515 case 1: 1516 return V_008F14_IMG_DATA_FORMAT_8; 1517 case 2: 1518 return V_008F14_IMG_DATA_FORMAT_8_8; 1519 case 4: 1520 return V_008F14_IMG_DATA_FORMAT_8_8_8_8; 1521 } 1522 break; 1523 case 16: 1524 switch (desc->nr_channels) { 1525 case 1: 1526 return V_008F14_IMG_DATA_FORMAT_16; 1527 case 2: 1528 return V_008F14_IMG_DATA_FORMAT_16_16; 1529 case 4: 1530 return V_008F14_IMG_DATA_FORMAT_16_16_16_16; 1531 } 1532 break; 1533 case 32: 1534 switch (desc->nr_channels) { 1535 case 1: 1536 return V_008F14_IMG_DATA_FORMAT_32; 1537 case 2: 1538 return V_008F14_IMG_DATA_FORMAT_32_32; 1539#if 0 /* Not supported for render targets */ 1540 case 3: 1541 return V_008F14_IMG_DATA_FORMAT_32_32_32; 1542#endif 1543 case 4: 1544 return V_008F14_IMG_DATA_FORMAT_32_32_32_32; 1545 } 1546 } 1547 1548out_unknown: 1549 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1550 return ~0; 1551} 1552 1553static unsigned si_tex_wrap(unsigned wrap) 1554{ 1555 switch (wrap) { 1556 default: 1557 case PIPE_TEX_WRAP_REPEAT: 1558 return V_008F30_SQ_TEX_WRAP; 1559 case PIPE_TEX_WRAP_CLAMP: 1560 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER; 1561 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 1562 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL; 1563 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 1564 return V_008F30_SQ_TEX_CLAMP_BORDER; 1565 case PIPE_TEX_WRAP_MIRROR_REPEAT: 1566 return V_008F30_SQ_TEX_MIRROR; 1567 case PIPE_TEX_WRAP_MIRROR_CLAMP: 1568 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 1569 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 1570 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 1571 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 1572 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER; 1573 } 1574} 1575 1576static unsigned si_tex_filter(unsigned filter) 1577{ 1578 switch (filter) { 1579 default: 1580 case PIPE_TEX_FILTER_NEAREST: 1581 return V_008F38_SQ_TEX_XY_FILTER_POINT; 1582 case PIPE_TEX_FILTER_LINEAR: 1583 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR; 1584 } 1585} 1586 1587static unsigned si_tex_mipfilter(unsigned filter) 1588{ 1589 switch (filter) { 1590 case PIPE_TEX_MIPFILTER_NEAREST: 1591 return V_008F38_SQ_TEX_Z_FILTER_POINT; 1592 case PIPE_TEX_MIPFILTER_LINEAR: 1593 return V_008F38_SQ_TEX_Z_FILTER_LINEAR; 1594 default: 1595 case PIPE_TEX_MIPFILTER_NONE: 1596 return V_008F38_SQ_TEX_Z_FILTER_NONE; 1597 } 1598} 1599 1600static unsigned si_tex_compare(unsigned compare) 1601{ 1602 switch (compare) { 1603 default: 1604 case PIPE_FUNC_NEVER: 1605 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER; 1606 case PIPE_FUNC_LESS: 1607 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS; 1608 case PIPE_FUNC_EQUAL: 1609 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL; 1610 case PIPE_FUNC_LEQUAL: 1611 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 1612 case PIPE_FUNC_GREATER: 1613 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER; 1614 case PIPE_FUNC_NOTEQUAL: 1615 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 1616 case PIPE_FUNC_GEQUAL: 1617 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 1618 case PIPE_FUNC_ALWAYS: 1619 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS; 1620 } 1621} 1622 1623static unsigned si_tex_dim(unsigned res_target, unsigned view_target, 1624 unsigned nr_samples) 1625{ 1626 if (view_target == PIPE_TEXTURE_CUBE || 1627 view_target == PIPE_TEXTURE_CUBE_ARRAY) 1628 res_target = view_target; 1629 1630 switch (res_target) { 1631 default: 1632 case PIPE_TEXTURE_1D: 1633 return V_008F1C_SQ_RSRC_IMG_1D; 1634 case PIPE_TEXTURE_1D_ARRAY: 1635 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY; 1636 case PIPE_TEXTURE_2D: 1637 case PIPE_TEXTURE_RECT: 1638 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA : 1639 V_008F1C_SQ_RSRC_IMG_2D; 1640 case PIPE_TEXTURE_2D_ARRAY: 1641 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : 1642 V_008F1C_SQ_RSRC_IMG_2D_ARRAY; 1643 case PIPE_TEXTURE_3D: 1644 return V_008F1C_SQ_RSRC_IMG_3D; 1645 case PIPE_TEXTURE_CUBE: 1646 case PIPE_TEXTURE_CUBE_ARRAY: 1647 return V_008F1C_SQ_RSRC_IMG_CUBE; 1648 } 1649} 1650 1651/* 1652 * Format support testing 1653 */ 1654 1655static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 1656{ 1657 return si_translate_texformat(screen, format, util_format_description(format), 1658 util_format_get_first_non_void_channel(format)) != ~0U; 1659} 1660 1661static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen, 1662 const struct util_format_description *desc, 1663 int first_non_void) 1664{ 1665 unsigned type = desc->channel[first_non_void].type; 1666 int i; 1667 1668 if (type == UTIL_FORMAT_TYPE_FIXED) 1669 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1670 1671 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT) 1672 return V_008F0C_BUF_DATA_FORMAT_10_11_11; 1673 1674 if (desc->nr_channels == 4 && 1675 desc->channel[0].size == 10 && 1676 desc->channel[1].size == 10 && 1677 desc->channel[2].size == 10 && 1678 desc->channel[3].size == 2) 1679 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10; 1680 1681 /* See whether the components are of the same size. */ 1682 for (i = 0; i < desc->nr_channels; i++) { 1683 if (desc->channel[first_non_void].size != desc->channel[i].size) 1684 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1685 } 1686 1687 switch (desc->channel[first_non_void].size) { 1688 case 8: 1689 switch (desc->nr_channels) { 1690 case 1: 1691 return V_008F0C_BUF_DATA_FORMAT_8; 1692 case 2: 1693 return V_008F0C_BUF_DATA_FORMAT_8_8; 1694 case 3: 1695 case 4: 1696 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8; 1697 } 1698 break; 1699 case 16: 1700 switch (desc->nr_channels) { 1701 case 1: 1702 return V_008F0C_BUF_DATA_FORMAT_16; 1703 case 2: 1704 return V_008F0C_BUF_DATA_FORMAT_16_16; 1705 case 3: 1706 case 4: 1707 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16; 1708 } 1709 break; 1710 case 32: 1711 /* From the Southern Islands ISA documentation about MTBUF: 1712 * 'Memory reads of data in memory that is 32 or 64 bits do not 1713 * undergo any format conversion.' 1714 */ 1715 if (type != UTIL_FORMAT_TYPE_FLOAT && 1716 !desc->channel[first_non_void].pure_integer) 1717 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1718 1719 switch (desc->nr_channels) { 1720 case 1: 1721 return V_008F0C_BUF_DATA_FORMAT_32; 1722 case 2: 1723 return V_008F0C_BUF_DATA_FORMAT_32_32; 1724 case 3: 1725 return V_008F0C_BUF_DATA_FORMAT_32_32_32; 1726 case 4: 1727 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32; 1728 } 1729 break; 1730 } 1731 1732 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1733} 1734 1735static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen, 1736 const struct util_format_description *desc, 1737 int first_non_void) 1738{ 1739 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT) 1740 return V_008F0C_BUF_NUM_FORMAT_FLOAT; 1741 1742 switch (desc->channel[first_non_void].type) { 1743 case UTIL_FORMAT_TYPE_SIGNED: 1744 if (desc->channel[first_non_void].normalized) 1745 return V_008F0C_BUF_NUM_FORMAT_SNORM; 1746 else if (desc->channel[first_non_void].pure_integer) 1747 return V_008F0C_BUF_NUM_FORMAT_SINT; 1748 else 1749 return V_008F0C_BUF_NUM_FORMAT_SSCALED; 1750 break; 1751 case UTIL_FORMAT_TYPE_UNSIGNED: 1752 if (desc->channel[first_non_void].normalized) 1753 return V_008F0C_BUF_NUM_FORMAT_UNORM; 1754 else if (desc->channel[first_non_void].pure_integer) 1755 return V_008F0C_BUF_NUM_FORMAT_UINT; 1756 else 1757 return V_008F0C_BUF_NUM_FORMAT_USCALED; 1758 break; 1759 case UTIL_FORMAT_TYPE_FLOAT: 1760 default: 1761 return V_008F0C_BUF_NUM_FORMAT_FLOAT; 1762 } 1763} 1764 1765static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format) 1766{ 1767 const struct util_format_description *desc; 1768 int first_non_void; 1769 unsigned data_format; 1770 1771 desc = util_format_description(format); 1772 first_non_void = util_format_get_first_non_void_channel(format); 1773 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void); 1774 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID; 1775} 1776 1777static bool si_is_colorbuffer_format_supported(enum pipe_format format) 1778{ 1779 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID && 1780 r600_translate_colorswap(format) != ~0U; 1781} 1782 1783static bool si_is_zs_format_supported(enum pipe_format format) 1784{ 1785 return si_translate_dbformat(format) != V_028040_Z_INVALID; 1786} 1787 1788boolean si_is_format_supported(struct pipe_screen *screen, 1789 enum pipe_format format, 1790 enum pipe_texture_target target, 1791 unsigned sample_count, 1792 unsigned usage) 1793{ 1794 unsigned retval = 0; 1795 1796 if (target >= PIPE_MAX_TEXTURE_TYPES) { 1797 R600_ERR("r600: unsupported texture type %d\n", target); 1798 return FALSE; 1799 } 1800 1801 if (!util_format_is_supported(format, usage)) 1802 return FALSE; 1803 1804 if (sample_count > 1) { 1805 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE)) 1806 return FALSE; 1807 1808 switch (sample_count) { 1809 case 2: 1810 case 4: 1811 case 8: 1812 break; 1813 default: 1814 return FALSE; 1815 } 1816 } 1817 1818 if (usage & PIPE_BIND_SAMPLER_VIEW) { 1819 if (target == PIPE_BUFFER) { 1820 if (si_is_vertex_format_supported(screen, format)) 1821 retval |= PIPE_BIND_SAMPLER_VIEW; 1822 } else { 1823 if (si_is_sampler_format_supported(screen, format)) 1824 retval |= PIPE_BIND_SAMPLER_VIEW; 1825 } 1826 } 1827 1828 if ((usage & (PIPE_BIND_RENDER_TARGET | 1829 PIPE_BIND_DISPLAY_TARGET | 1830 PIPE_BIND_SCANOUT | 1831 PIPE_BIND_SHARED | 1832 PIPE_BIND_BLENDABLE)) && 1833 si_is_colorbuffer_format_supported(format)) { 1834 retval |= usage & 1835 (PIPE_BIND_RENDER_TARGET | 1836 PIPE_BIND_DISPLAY_TARGET | 1837 PIPE_BIND_SCANOUT | 1838 PIPE_BIND_SHARED); 1839 if (!util_format_is_pure_integer(format) && 1840 !util_format_is_depth_or_stencil(format)) 1841 retval |= usage & PIPE_BIND_BLENDABLE; 1842 } 1843 1844 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 1845 si_is_zs_format_supported(format)) { 1846 retval |= PIPE_BIND_DEPTH_STENCIL; 1847 } 1848 1849 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 1850 si_is_vertex_format_supported(screen, format)) { 1851 retval |= PIPE_BIND_VERTEX_BUFFER; 1852 } 1853 1854 if (usage & PIPE_BIND_TRANSFER_READ) 1855 retval |= PIPE_BIND_TRANSFER_READ; 1856 if (usage & PIPE_BIND_TRANSFER_WRITE) 1857 retval |= PIPE_BIND_TRANSFER_WRITE; 1858 1859 return retval == usage; 1860} 1861 1862unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil) 1863{ 1864 unsigned tile_mode_index = 0; 1865 1866 if (stencil) { 1867 tile_mode_index = rtex->surface.stencil_tiling_index[level]; 1868 } else { 1869 tile_mode_index = rtex->surface.tiling_index[level]; 1870 } 1871 return tile_mode_index; 1872} 1873 1874/* 1875 * framebuffer handling 1876 */ 1877 1878static void si_choose_spi_color_formats(struct r600_surface *surf, 1879 unsigned format, unsigned swap, 1880 unsigned ntype, bool is_depth) 1881{ 1882 /* Alpha is needed for alpha-to-coverage. 1883 * Blending may be with or without alpha. 1884 */ 1885 unsigned normal = 0; /* most optimal, may not support blending or export alpha */ 1886 unsigned alpha = 0; /* exports alpha, but may not support blending */ 1887 unsigned blend = 0; /* supports blending, but may not export alpha */ 1888 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */ 1889 1890 /* Choose the SPI color formats. These are required values for Stoney/RB+. 1891 * Other chips have multiple choices, though they are not necessarily better. 1892 */ 1893 switch (format) { 1894 case V_028C70_COLOR_5_6_5: 1895 case V_028C70_COLOR_1_5_5_5: 1896 case V_028C70_COLOR_5_5_5_1: 1897 case V_028C70_COLOR_4_4_4_4: 1898 case V_028C70_COLOR_10_11_11: 1899 case V_028C70_COLOR_11_11_10: 1900 case V_028C70_COLOR_8: 1901 case V_028C70_COLOR_8_8: 1902 case V_028C70_COLOR_8_8_8_8: 1903 case V_028C70_COLOR_10_10_10_2: 1904 case V_028C70_COLOR_2_10_10_10: 1905 if (ntype == V_028C70_NUMBER_UINT) 1906 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR; 1907 else if (ntype == V_028C70_NUMBER_SINT) 1908 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR; 1909 else 1910 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR; 1911 break; 1912 1913 case V_028C70_COLOR_16: 1914 case V_028C70_COLOR_16_16: 1915 case V_028C70_COLOR_16_16_16_16: 1916 if (ntype == V_028C70_NUMBER_UNORM || 1917 ntype == V_028C70_NUMBER_SNORM) { 1918 /* UNORM16 and SNORM16 don't support blending */ 1919 if (ntype == V_028C70_NUMBER_UNORM) 1920 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR; 1921 else 1922 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR; 1923 1924 /* Use 32 bits per channel for blending. */ 1925 if (format == V_028C70_COLOR_16) { 1926 if (swap == V_028C70_SWAP_STD) { /* R */ 1927 blend = V_028714_SPI_SHADER_32_R; 1928 blend_alpha = V_028714_SPI_SHADER_32_AR; 1929 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */ 1930 blend = blend_alpha = V_028714_SPI_SHADER_32_AR; 1931 else 1932 assert(0); 1933 } else if (format == V_028C70_COLOR_16_16) { 1934 if (swap == V_028C70_SWAP_STD) { /* RG */ 1935 blend = V_028714_SPI_SHADER_32_GR; 1936 blend_alpha = V_028714_SPI_SHADER_32_ABGR; 1937 } else if (swap == V_028C70_SWAP_ALT) /* RA */ 1938 blend = blend_alpha = V_028714_SPI_SHADER_32_AR; 1939 else 1940 assert(0); 1941 } else /* 16_16_16_16 */ 1942 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR; 1943 } else if (ntype == V_028C70_NUMBER_UINT) 1944 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR; 1945 else if (ntype == V_028C70_NUMBER_SINT) 1946 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR; 1947 else if (ntype == V_028C70_NUMBER_FLOAT) 1948 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR; 1949 else 1950 assert(0); 1951 break; 1952 1953 case V_028C70_COLOR_32: 1954 if (swap == V_028C70_SWAP_STD) { /* R */ 1955 blend = normal = V_028714_SPI_SHADER_32_R; 1956 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR; 1957 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */ 1958 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR; 1959 else 1960 assert(0); 1961 break; 1962 1963 case V_028C70_COLOR_32_32: 1964 if (swap == V_028C70_SWAP_STD) { /* RG */ 1965 blend = normal = V_028714_SPI_SHADER_32_GR; 1966 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR; 1967 } else if (swap == V_028C70_SWAP_ALT) /* RA */ 1968 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR; 1969 else 1970 assert(0); 1971 break; 1972 1973 case V_028C70_COLOR_32_32_32_32: 1974 case V_028C70_COLOR_8_24: 1975 case V_028C70_COLOR_24_8: 1976 case V_028C70_COLOR_X24_8_32_FLOAT: 1977 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR; 1978 break; 1979 1980 default: 1981 assert(0); 1982 return; 1983 } 1984 1985 /* The DB->CB copy needs 32_ABGR. */ 1986 if (is_depth) 1987 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR; 1988 1989 surf->spi_shader_col_format = normal; 1990 surf->spi_shader_col_format_alpha = alpha; 1991 surf->spi_shader_col_format_blend = blend; 1992 surf->spi_shader_col_format_blend_alpha = blend_alpha; 1993} 1994 1995static void si_initialize_color_surface(struct si_context *sctx, 1996 struct r600_surface *surf) 1997{ 1998 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; 1999 unsigned level = surf->base.u.tex.level; 2000 uint64_t offset = rtex->surface.level[level].offset; 2001 unsigned pitch, slice; 2002 unsigned color_info, color_attrib, color_pitch, color_view; 2003 unsigned tile_mode_index; 2004 unsigned format, swap, ntype, endian; 2005 const struct util_format_description *desc; 2006 int i; 2007 unsigned blend_clamp = 0, blend_bypass = 0; 2008 2009 /* Layered rendering doesn't work with LINEAR_GENERAL. 2010 * (LINEAR_ALIGNED and others work) */ 2011 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) { 2012 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer); 2013 offset += rtex->surface.level[level].slice_size * 2014 surf->base.u.tex.first_layer; 2015 color_view = 0; 2016 } else { 2017 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | 2018 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); 2019 } 2020 2021 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; 2022 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 2023 if (slice) { 2024 slice = slice - 1; 2025 } 2026 2027 tile_mode_index = si_tile_mode_index(rtex, level, false); 2028 2029 desc = util_format_description(surf->base.format); 2030 for (i = 0; i < 4; i++) { 2031 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 2032 break; 2033 } 2034 } 2035 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { 2036 ntype = V_028C70_NUMBER_FLOAT; 2037 } else { 2038 ntype = V_028C70_NUMBER_UNORM; 2039 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 2040 ntype = V_028C70_NUMBER_SRGB; 2041 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 2042 if (desc->channel[i].pure_integer) { 2043 ntype = V_028C70_NUMBER_SINT; 2044 } else { 2045 assert(desc->channel[i].normalized); 2046 ntype = V_028C70_NUMBER_SNORM; 2047 } 2048 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 2049 if (desc->channel[i].pure_integer) { 2050 ntype = V_028C70_NUMBER_UINT; 2051 } else { 2052 assert(desc->channel[i].normalized); 2053 ntype = V_028C70_NUMBER_UNORM; 2054 } 2055 } 2056 } 2057 2058 format = si_translate_colorformat(surf->base.format); 2059 if (format == V_028C70_COLOR_INVALID) { 2060 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format); 2061 } 2062 assert(format != V_028C70_COLOR_INVALID); 2063 swap = r600_translate_colorswap(surf->base.format); 2064 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { 2065 endian = V_028C70_ENDIAN_NONE; 2066 } else { 2067 endian = si_colorformat_endian_swap(format); 2068 } 2069 2070 /* blend clamp should be set for all NORM/SRGB types */ 2071 if (ntype == V_028C70_NUMBER_UNORM || 2072 ntype == V_028C70_NUMBER_SNORM || 2073 ntype == V_028C70_NUMBER_SRGB) 2074 blend_clamp = 1; 2075 2076 /* set blend bypass according to docs if SINT/UINT or 2077 8/24 COLOR variants */ 2078 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT || 2079 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 || 2080 format == V_028C70_COLOR_X24_8_32_FLOAT) { 2081 blend_clamp = 0; 2082 blend_bypass = 1; 2083 } 2084 2085 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) && 2086 (format == V_028C70_COLOR_8 || 2087 format == V_028C70_COLOR_8_8 || 2088 format == V_028C70_COLOR_8_8_8_8)) 2089 surf->color_is_int8 = true; 2090 2091 color_info = S_028C70_FORMAT(format) | 2092 S_028C70_COMP_SWAP(swap) | 2093 S_028C70_BLEND_CLAMP(blend_clamp) | 2094 S_028C70_BLEND_BYPASS(blend_bypass) | 2095 S_028C70_NUMBER_TYPE(ntype) | 2096 S_028C70_ENDIAN(endian); 2097 2098 color_pitch = S_028C64_TILE_MAX(pitch); 2099 2100 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) | 2101 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1); 2102 2103 if (rtex->resource.b.b.nr_samples > 1) { 2104 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples); 2105 2106 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | 2107 S_028C74_NUM_FRAGMENTS(log_samples); 2108 2109 if (rtex->fmask.size) { 2110 color_info |= S_028C70_COMPRESSION(1); 2111 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height); 2112 2113 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index); 2114 2115 if (sctx->b.chip_class == SI) { 2116 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */ 2117 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh); 2118 } 2119 if (sctx->b.chip_class >= CIK) { 2120 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1); 2121 } 2122 } 2123 } 2124 2125 offset += rtex->resource.gpu_address; 2126 2127 surf->cb_color_base = offset >> 8; 2128 surf->cb_color_pitch = color_pitch; 2129 surf->cb_color_slice = S_028C68_TILE_MAX(slice); 2130 surf->cb_color_view = color_view; 2131 surf->cb_color_info = color_info; 2132 surf->cb_color_attrib = color_attrib; 2133 2134 if (sctx->b.chip_class >= VI && rtex->dcc_buffer) { 2135 unsigned max_uncompressed_block_size = 2; 2136 uint64_t dcc_offset = rtex->surface.level[level].dcc_offset; 2137 2138 if (rtex->surface.nsamples > 1) { 2139 if (rtex->surface.bpe == 1) 2140 max_uncompressed_block_size = 0; 2141 else if (rtex->surface.bpe == 2) 2142 max_uncompressed_block_size = 1; 2143 } 2144 2145 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) | 2146 S_028C78_INDEPENDENT_64B_BLOCKS(1); 2147 surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + dcc_offset) >> 8; 2148 } 2149 2150 if (rtex->fmask.size) { 2151 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8; 2152 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max); 2153 } else { 2154 /* This must be set for fast clear to work without FMASK. */ 2155 surf->cb_color_fmask = surf->cb_color_base; 2156 surf->cb_color_fmask_slice = surf->cb_color_slice; 2157 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index); 2158 2159 if (sctx->b.chip_class == SI) { 2160 unsigned bankh = util_logbase2(rtex->surface.bankh); 2161 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh); 2162 } 2163 2164 if (sctx->b.chip_class >= CIK) { 2165 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch); 2166 } 2167 } 2168 2169 /* Determine pixel shader export format */ 2170 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth); 2171 2172 if (sctx->b.family == CHIP_STONEY && 2173 !(sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)) { 2174 switch (desc->channel[0].size) { 2175 case 32: 2176 if (desc->nr_channels == 1) { 2177 if (swap == V_0280A0_SWAP_STD) 2178 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R; 2179 else if (swap == V_0280A0_SWAP_ALT_REV) 2180 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_A; 2181 } 2182 break; 2183 case 16: 2184 /* For 1-channel formats, use the superset thereof. */ 2185 if (desc->nr_channels <= 2) { 2186 if (swap == V_0280A0_SWAP_STD || 2187 swap == V_0280A0_SWAP_STD_REV) 2188 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_16_16_GR; 2189 else 2190 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_16_16_AR; 2191 } 2192 break; 2193 case 11: 2194 if (desc->nr_channels == 3) { 2195 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_10_11_11; 2196 surf->sx_blend_opt_epsilon = V_028758_11BIT_FORMAT; 2197 } 2198 break; 2199 case 10: 2200 if (desc->nr_channels == 4) { 2201 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_2_10_10_10; 2202 surf->sx_blend_opt_epsilon = V_028758_10BIT_FORMAT; 2203 } 2204 break; 2205 case 8: 2206 /* For 1 and 2-channel formats, use the superset thereof. */ 2207 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_8_8_8_8; 2208 surf->sx_blend_opt_epsilon = V_028758_8BIT_FORMAT; 2209 break; 2210 case 5: 2211 if (desc->nr_channels == 3) { 2212 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_5_6_5; 2213 surf->sx_blend_opt_epsilon = V_028758_6BIT_FORMAT; 2214 } else if (desc->nr_channels == 4) { 2215 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_1_5_5_5; 2216 surf->sx_blend_opt_epsilon = V_028758_5BIT_FORMAT; 2217 } 2218 break; 2219 case 4: 2220 /* For 1 nad 2-channel formats, use the superset thereof. */ 2221 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_4_4_4_4; 2222 surf->sx_blend_opt_epsilon = V_028758_4BIT_FORMAT; 2223 break; 2224 } 2225 } 2226 2227 surf->color_initialized = true; 2228} 2229 2230static void si_init_depth_surface(struct si_context *sctx, 2231 struct r600_surface *surf) 2232{ 2233 struct si_screen *sscreen = sctx->screen; 2234 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; 2235 unsigned level = surf->base.u.tex.level; 2236 struct radeon_surf_level *levelinfo = &rtex->surface.level[level]; 2237 unsigned format, tile_mode_index, array_mode; 2238 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config; 2239 uint32_t z_info, s_info, db_depth_info; 2240 uint64_t z_offs, s_offs; 2241 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0; 2242 2243 switch (sctx->framebuffer.state.zsbuf->texture->format) { 2244 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2245 case PIPE_FORMAT_X8Z24_UNORM: 2246 case PIPE_FORMAT_Z24X8_UNORM: 2247 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 2248 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24); 2249 break; 2250 case PIPE_FORMAT_Z32_FLOAT: 2251 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 2252 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | 2253 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 2254 break; 2255 case PIPE_FORMAT_Z16_UNORM: 2256 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16); 2257 break; 2258 default: 2259 assert(0); 2260 } 2261 2262 format = si_translate_dbformat(rtex->resource.b.b.format); 2263 2264 if (format == V_028040_Z_INVALID) { 2265 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format); 2266 } 2267 assert(format != V_028040_Z_INVALID); 2268 2269 s_offs = z_offs = rtex->resource.gpu_address; 2270 z_offs += rtex->surface.level[level].offset; 2271 s_offs += rtex->surface.stencil_level[level].offset; 2272 2273 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1); 2274 2275 z_info = S_028040_FORMAT(format); 2276 if (rtex->resource.b.b.nr_samples > 1) { 2277 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)); 2278 } 2279 2280 if (rtex->surface.flags & RADEON_SURF_SBUFFER) 2281 s_info = S_028044_FORMAT(V_028044_STENCIL_8); 2282 else 2283 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID); 2284 2285 if (sctx->b.chip_class >= CIK) { 2286 switch (rtex->surface.level[level].mode) { 2287 case RADEON_SURF_MODE_2D: 2288 array_mode = V_02803C_ARRAY_2D_TILED_THIN1; 2289 break; 2290 case RADEON_SURF_MODE_1D: 2291 case RADEON_SURF_MODE_LINEAR_ALIGNED: 2292 case RADEON_SURF_MODE_LINEAR: 2293 default: 2294 array_mode = V_02803C_ARRAY_1D_TILED_THIN1; 2295 break; 2296 } 2297 tile_split = rtex->surface.tile_split; 2298 stile_split = rtex->surface.stencil_tile_split; 2299 macro_aspect = rtex->surface.mtilea; 2300 bankw = rtex->surface.bankw; 2301 bankh = rtex->surface.bankh; 2302 tile_split = cik_tile_split(tile_split); 2303 stile_split = cik_tile_split(stile_split); 2304 macro_aspect = cik_macro_tile_aspect(macro_aspect); 2305 bankw = cik_bank_wh(bankw); 2306 bankh = cik_bank_wh(bankh); 2307 nbanks = si_num_banks(sscreen, rtex); 2308 tile_mode_index = si_tile_mode_index(rtex, level, false); 2309 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index); 2310 2311 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) | 2312 S_02803C_PIPE_CONFIG(pipe_config) | 2313 S_02803C_BANK_WIDTH(bankw) | 2314 S_02803C_BANK_HEIGHT(bankh) | 2315 S_02803C_MACRO_TILE_ASPECT(macro_aspect) | 2316 S_02803C_NUM_BANKS(nbanks); 2317 z_info |= S_028040_TILE_SPLIT(tile_split); 2318 s_info |= S_028044_TILE_SPLIT(stile_split); 2319 } else { 2320 tile_mode_index = si_tile_mode_index(rtex, level, false); 2321 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); 2322 tile_mode_index = si_tile_mode_index(rtex, level, true); 2323 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index); 2324 } 2325 2326 /* HiZ aka depth buffer htile */ 2327 /* use htile only for first level */ 2328 if (rtex->htile_buffer && !level) { 2329 z_info |= S_028040_TILE_SURFACE_ENABLE(1) | 2330 S_028040_ALLOW_EXPCLEAR(1); 2331 2332 if (rtex->surface.flags & RADEON_SURF_SBUFFER) 2333 s_info |= S_028044_ALLOW_EXPCLEAR(1); 2334 else 2335 /* Use all of the htile_buffer for depth if there's no stencil. */ 2336 s_info |= S_028044_TILE_STENCIL_DISABLE(1); 2337 2338 uint64_t va = rtex->htile_buffer->gpu_address; 2339 db_htile_data_base = va >> 8; 2340 db_htile_surface = S_028ABC_FULL_CACHE(1); 2341 } else { 2342 db_htile_data_base = 0; 2343 db_htile_surface = 0; 2344 } 2345 2346 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); 2347 2348 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) | 2349 S_028008_SLICE_MAX(surf->base.u.tex.last_layer); 2350 surf->db_htile_data_base = db_htile_data_base; 2351 surf->db_depth_info = db_depth_info; 2352 surf->db_z_info = z_info; 2353 surf->db_stencil_info = s_info; 2354 surf->db_depth_base = z_offs >> 8; 2355 surf->db_stencil_base = s_offs >> 8; 2356 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) | 2357 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1); 2358 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x * 2359 levelinfo->nblk_y) / 64 - 1); 2360 surf->db_htile_surface = db_htile_surface; 2361 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl; 2362 2363 surf->depth_initialized = true; 2364} 2365 2366static void si_set_framebuffer_state(struct pipe_context *ctx, 2367 const struct pipe_framebuffer_state *state) 2368{ 2369 struct si_context *sctx = (struct si_context *)ctx; 2370 struct pipe_constant_buffer constbuf = {0}; 2371 struct r600_surface *surf = NULL; 2372 struct r600_texture *rtex; 2373 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer; 2374 unsigned old_nr_samples = sctx->framebuffer.nr_samples; 2375 int i; 2376 2377 /* Only flush TC when changing the framebuffer state, because 2378 * the only client not using TC that can change textures is 2379 * the framebuffer. 2380 * 2381 * Flush all CB and DB caches here because all buffers can be used 2382 * for write by both TC (with shader image stores) and CB/DB. 2383 */ 2384 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 | 2385 SI_CONTEXT_INV_GLOBAL_L2 | 2386 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER; 2387 2388 /* Take the maximum of the old and new count. If the new count is lower, 2389 * dirtying is needed to disable the unbound colorbuffers. 2390 */ 2391 sctx->framebuffer.dirty_cbufs |= 2392 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1; 2393 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf; 2394 2395 util_copy_framebuffer_state(&sctx->framebuffer.state, state); 2396 2397 sctx->framebuffer.spi_shader_col_format = 0; 2398 sctx->framebuffer.spi_shader_col_format_alpha = 0; 2399 sctx->framebuffer.spi_shader_col_format_blend = 0; 2400 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0; 2401 sctx->framebuffer.color_is_int8 = 0; 2402 2403 sctx->framebuffer.compressed_cb_mask = 0; 2404 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state); 2405 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples); 2406 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] && 2407 util_format_is_pure_integer(state->cbufs[0]->format); 2408 2409 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer) 2410 si_mark_atom_dirty(sctx, &sctx->db_render_state); 2411 2412 for (i = 0; i < state->nr_cbufs; i++) { 2413 if (!state->cbufs[i]) 2414 continue; 2415 2416 surf = (struct r600_surface*)state->cbufs[i]; 2417 rtex = (struct r600_texture*)surf->base.texture; 2418 2419 if (!surf->color_initialized) { 2420 si_initialize_color_surface(sctx, surf); 2421 } 2422 2423 sctx->framebuffer.spi_shader_col_format |= 2424 surf->spi_shader_col_format << (i * 4); 2425 sctx->framebuffer.spi_shader_col_format_alpha |= 2426 surf->spi_shader_col_format_alpha << (i * 4); 2427 sctx->framebuffer.spi_shader_col_format_blend |= 2428 surf->spi_shader_col_format_blend << (i * 4); 2429 sctx->framebuffer.spi_shader_col_format_blend_alpha |= 2430 surf->spi_shader_col_format_blend_alpha << (i * 4); 2431 2432 if (surf->color_is_int8) 2433 sctx->framebuffer.color_is_int8 |= 1 << i; 2434 2435 if (rtex->fmask.size && rtex->cmask.size) { 2436 sctx->framebuffer.compressed_cb_mask |= 1 << i; 2437 } 2438 r600_context_add_resource_size(ctx, surf->base.texture); 2439 } 2440 /* Set the second SPI format for possible dual-src blending. */ 2441 if (i == 1 && surf) { 2442 sctx->framebuffer.spi_shader_col_format |= 2443 surf->spi_shader_col_format << (i * 4); 2444 sctx->framebuffer.spi_shader_col_format_alpha |= 2445 surf->spi_shader_col_format_alpha << (i * 4); 2446 sctx->framebuffer.spi_shader_col_format_blend |= 2447 surf->spi_shader_col_format_blend << (i * 4); 2448 sctx->framebuffer.spi_shader_col_format_blend_alpha |= 2449 surf->spi_shader_col_format_blend_alpha << (i * 4); 2450 } 2451 2452 if (state->zsbuf) { 2453 surf = (struct r600_surface*)state->zsbuf; 2454 2455 if (!surf->depth_initialized) { 2456 si_init_depth_surface(sctx, surf); 2457 } 2458 r600_context_add_resource_size(ctx, surf->base.texture); 2459 } 2460 2461 si_update_poly_offset_state(sctx); 2462 si_mark_atom_dirty(sctx, &sctx->cb_target_mask); 2463 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); 2464 2465 if (sctx->framebuffer.nr_samples != old_nr_samples) { 2466 si_mark_atom_dirty(sctx, &sctx->msaa_config); 2467 si_mark_atom_dirty(sctx, &sctx->db_render_state); 2468 2469 /* Set sample locations as fragment shader constants. */ 2470 switch (sctx->framebuffer.nr_samples) { 2471 case 1: 2472 constbuf.user_buffer = sctx->b.sample_locations_1x; 2473 break; 2474 case 2: 2475 constbuf.user_buffer = sctx->b.sample_locations_2x; 2476 break; 2477 case 4: 2478 constbuf.user_buffer = sctx->b.sample_locations_4x; 2479 break; 2480 case 8: 2481 constbuf.user_buffer = sctx->b.sample_locations_8x; 2482 break; 2483 case 16: 2484 constbuf.user_buffer = sctx->b.sample_locations_16x; 2485 break; 2486 default: 2487 assert(0); 2488 } 2489 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4; 2490 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT, 2491 SI_DRIVER_STATE_CONST_BUF, &constbuf); 2492 2493 /* Smoothing (only possible with nr_samples == 1) uses the same 2494 * sample locations as the MSAA it simulates. 2495 * 2496 * Therefore, don't update the sample locations when 2497 * transitioning from no AA to smoothing-equivalent AA, and 2498 * vice versa. 2499 */ 2500 if ((sctx->framebuffer.nr_samples != 1 || 2501 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) && 2502 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES || 2503 old_nr_samples != 1)) 2504 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs); 2505 } 2506} 2507 2508static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom) 2509{ 2510 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 2511 struct pipe_framebuffer_state *state = &sctx->framebuffer.state; 2512 unsigned i, nr_cbufs = state->nr_cbufs; 2513 struct r600_texture *tex = NULL; 2514 struct r600_surface *cb = NULL; 2515 uint32_t sx_ps_downconvert = 0; 2516 uint32_t sx_blend_opt_epsilon = 0; 2517 2518 /* Colorbuffers. */ 2519 for (i = 0; i < nr_cbufs; i++) { 2520 if (!(sctx->framebuffer.dirty_cbufs & (1 << i))) 2521 continue; 2522 2523 cb = (struct r600_surface*)state->cbufs[i]; 2524 if (!cb) { 2525 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 2526 S_028C70_FORMAT(V_028C70_COLOR_INVALID)); 2527 continue; 2528 } 2529 2530 tex = (struct r600_texture *)cb->base.texture; 2531 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, 2532 &tex->resource, RADEON_USAGE_READWRITE, 2533 tex->surface.nsamples > 1 ? 2534 RADEON_PRIO_COLOR_BUFFER_MSAA : 2535 RADEON_PRIO_COLOR_BUFFER); 2536 2537 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) { 2538 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, 2539 tex->cmask_buffer, RADEON_USAGE_READWRITE, 2540 RADEON_PRIO_CMASK); 2541 } 2542 2543 if (tex->dcc_buffer && tex->dcc_buffer != &tex->resource) { 2544 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, 2545 tex->dcc_buffer, RADEON_USAGE_READWRITE, 2546 RADEON_PRIO_DCC); 2547 } 2548 2549 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 2550 sctx->b.chip_class >= VI ? 14 : 13); 2551 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */ 2552 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */ 2553 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */ 2554 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */ 2555 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */ 2556 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */ 2557 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */ 2558 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */ 2559 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */ 2560 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */ 2561 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */ 2562 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */ 2563 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */ 2564 2565 if (sctx->b.chip_class >= VI) 2566 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */ 2567 2568 sx_ps_downconvert |= cb->sx_ps_downconvert << (4 * i); 2569 sx_blend_opt_epsilon |= cb->sx_blend_opt_epsilon << (4 * i); 2570 } 2571 /* set CB_COLOR1_INFO for possible dual-src blending */ 2572 if (i == 1 && state->cbufs[0] && 2573 sctx->framebuffer.dirty_cbufs & (1 << 0)) { 2574 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, 2575 cb->cb_color_info | tex->cb_color_info); 2576 sx_ps_downconvert |= cb->sx_ps_downconvert << (4 * i); 2577 sx_blend_opt_epsilon |= cb->sx_blend_opt_epsilon << (4 * i); 2578 i++; 2579 } 2580 for (; i < 8 ; i++) 2581 if (sctx->framebuffer.dirty_cbufs & (1 << i)) 2582 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); 2583 2584 if (sctx->b.family == CHIP_STONEY) { 2585 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 2); 2586 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */ 2587 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */ 2588 } 2589 2590 /* ZS buffer. */ 2591 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) { 2592 struct r600_surface *zb = (struct r600_surface*)state->zsbuf; 2593 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture; 2594 2595 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, 2596 &rtex->resource, RADEON_USAGE_READWRITE, 2597 zb->base.texture->nr_samples > 1 ? 2598 RADEON_PRIO_DEPTH_BUFFER_MSAA : 2599 RADEON_PRIO_DEPTH_BUFFER); 2600 2601 if (zb->db_htile_data_base) { 2602 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, 2603 rtex->htile_buffer, RADEON_USAGE_READWRITE, 2604 RADEON_PRIO_HTILE); 2605 } 2606 2607 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); 2608 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base); 2609 2610 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9); 2611 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */ 2612 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */ 2613 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0)); 2614 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */ 2615 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */ 2616 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */ 2617 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */ 2618 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */ 2619 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */ 2620 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */ 2621 2622 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2); 2623 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */ 2624 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */ 2625 2626 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface); 2627 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 2628 zb->pa_su_poly_offset_db_fmt_cntl); 2629 } else if (sctx->framebuffer.dirty_zsbuf) { 2630 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2); 2631 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */ 2632 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */ 2633 } 2634 2635 /* Framebuffer dimensions. */ 2636 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */ 2637 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR, 2638 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height)); 2639 2640 sctx->framebuffer.dirty_cbufs = 0; 2641 sctx->framebuffer.dirty_zsbuf = false; 2642} 2643 2644static void si_emit_msaa_sample_locs(struct si_context *sctx, 2645 struct r600_atom *atom) 2646{ 2647 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 2648 unsigned nr_samples = sctx->framebuffer.nr_samples; 2649 2650 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples : 2651 SI_NUM_SMOOTH_AA_SAMPLES); 2652} 2653 2654static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom) 2655{ 2656 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 2657 2658 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples, 2659 sctx->ps_iter_samples, 2660 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0); 2661} 2662 2663 2664static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples) 2665{ 2666 struct si_context *sctx = (struct si_context *)ctx; 2667 2668 if (sctx->ps_iter_samples == min_samples) 2669 return; 2670 2671 sctx->ps_iter_samples = min_samples; 2672 2673 if (sctx->framebuffer.nr_samples > 1) 2674 si_mark_atom_dirty(sctx, &sctx->msaa_config); 2675} 2676 2677/* 2678 * Samplers 2679 */ 2680 2681/** 2682 * Create a sampler view. 2683 * 2684 * @param ctx context 2685 * @param texture texture 2686 * @param state sampler view template 2687 * @param width0 width0 override (for compressed textures as int) 2688 * @param height0 height0 override (for compressed textures as int) 2689 * @param force_level set the base address to the level (for compressed textures) 2690 */ 2691struct pipe_sampler_view * 2692si_create_sampler_view_custom(struct pipe_context *ctx, 2693 struct pipe_resource *texture, 2694 const struct pipe_sampler_view *state, 2695 unsigned width0, unsigned height0, 2696 unsigned force_level) 2697{ 2698 struct si_context *sctx = (struct si_context*)ctx; 2699 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view); 2700 struct r600_texture *tmp = (struct r600_texture*)texture; 2701 const struct util_format_description *desc; 2702 unsigned format, num_format, base_level, first_level, last_level; 2703 uint32_t pitch = 0; 2704 unsigned char state_swizzle[4], swizzle[4]; 2705 unsigned height, depth, width; 2706 enum pipe_format pipe_format = state->format; 2707 struct radeon_surf_level *surflevel; 2708 int first_non_void; 2709 uint64_t va; 2710 unsigned last_layer = state->u.tex.last_layer; 2711 2712 if (!view) 2713 return NULL; 2714 2715 /* initialize base object */ 2716 view->base = *state; 2717 view->base.texture = NULL; 2718 view->base.reference.count = 1; 2719 view->base.context = ctx; 2720 2721 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */ 2722 if (!texture) { 2723 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) | 2724 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) | 2725 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) | 2726 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) | 2727 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D); 2728 return &view->base; 2729 } 2730 2731 pipe_resource_reference(&view->base.texture, texture); 2732 view->resource = &tmp->resource; 2733 2734 if (state->format == PIPE_FORMAT_X24S8_UINT || 2735 state->format == PIPE_FORMAT_S8X24_UINT || 2736 state->format == PIPE_FORMAT_X32_S8X24_UINT || 2737 state->format == PIPE_FORMAT_S8_UINT) 2738 view->is_stencil_sampler = true; 2739 2740 /* Buffer resource. */ 2741 if (texture->target == PIPE_BUFFER) { 2742 unsigned stride, num_records; 2743 2744 desc = util_format_description(state->format); 2745 first_non_void = util_format_get_first_non_void_channel(state->format); 2746 stride = desc->block.bits / 8; 2747 va = tmp->resource.gpu_address + state->u.buf.first_element*stride; 2748 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void); 2749 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void); 2750 2751 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element; 2752 num_records = MIN2(num_records, texture->width0 / stride); 2753 2754 if (sctx->b.chip_class >= VI) 2755 num_records *= stride; 2756 2757 view->state[4] = va; 2758 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) | 2759 S_008F04_STRIDE(stride); 2760 view->state[6] = num_records; 2761 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | 2762 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | 2763 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | 2764 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | 2765 S_008F0C_NUM_FORMAT(num_format) | 2766 S_008F0C_DATA_FORMAT(format); 2767 2768 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers); 2769 return &view->base; 2770 } 2771 2772 state_swizzle[0] = state->swizzle_r; 2773 state_swizzle[1] = state->swizzle_g; 2774 state_swizzle[2] = state->swizzle_b; 2775 state_swizzle[3] = state->swizzle_a; 2776 2777 surflevel = tmp->surface.level; 2778 2779 /* Texturing with separate depth and stencil. */ 2780 if (tmp->is_depth && !tmp->is_flushing_texture) { 2781 switch (pipe_format) { 2782 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 2783 pipe_format = PIPE_FORMAT_Z32_FLOAT; 2784 break; 2785 case PIPE_FORMAT_X8Z24_UNORM: 2786 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2787 /* Z24 is always stored like this. */ 2788 pipe_format = PIPE_FORMAT_Z24X8_UNORM; 2789 break; 2790 case PIPE_FORMAT_X24S8_UINT: 2791 case PIPE_FORMAT_S8X24_UINT: 2792 case PIPE_FORMAT_X32_S8X24_UINT: 2793 pipe_format = PIPE_FORMAT_S8_UINT; 2794 surflevel = tmp->surface.stencil_level; 2795 break; 2796 default:; 2797 } 2798 } 2799 2800 desc = util_format_description(pipe_format); 2801 2802 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) { 2803 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0}; 2804 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1}; 2805 2806 switch (pipe_format) { 2807 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2808 case PIPE_FORMAT_X24S8_UINT: 2809 case PIPE_FORMAT_X32_S8X24_UINT: 2810 case PIPE_FORMAT_X8Z24_UNORM: 2811 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle); 2812 break; 2813 default: 2814 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle); 2815 } 2816 } else { 2817 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle); 2818 } 2819 2820 first_non_void = util_format_get_first_non_void_channel(pipe_format); 2821 2822 switch (pipe_format) { 2823 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2824 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2825 break; 2826 default: 2827 if (first_non_void < 0) { 2828 if (util_format_is_compressed(pipe_format)) { 2829 switch (pipe_format) { 2830 case PIPE_FORMAT_DXT1_SRGB: 2831 case PIPE_FORMAT_DXT1_SRGBA: 2832 case PIPE_FORMAT_DXT3_SRGBA: 2833 case PIPE_FORMAT_DXT5_SRGBA: 2834 case PIPE_FORMAT_BPTC_SRGBA: 2835 case PIPE_FORMAT_ETC2_SRGB8: 2836 case PIPE_FORMAT_ETC2_SRGB8A1: 2837 case PIPE_FORMAT_ETC2_SRGBA8: 2838 num_format = V_008F14_IMG_NUM_FORMAT_SRGB; 2839 break; 2840 case PIPE_FORMAT_RGTC1_SNORM: 2841 case PIPE_FORMAT_LATC1_SNORM: 2842 case PIPE_FORMAT_RGTC2_SNORM: 2843 case PIPE_FORMAT_LATC2_SNORM: 2844 case PIPE_FORMAT_ETC2_R11_SNORM: 2845 case PIPE_FORMAT_ETC2_RG11_SNORM: 2846 /* implies float, so use SNORM/UNORM to determine 2847 whether data is signed or not */ 2848 case PIPE_FORMAT_BPTC_RGB_FLOAT: 2849 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 2850 break; 2851 default: 2852 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2853 break; 2854 } 2855 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) { 2856 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2857 } else { 2858 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2859 } 2860 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) { 2861 num_format = V_008F14_IMG_NUM_FORMAT_SRGB; 2862 } else { 2863 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2864 2865 switch (desc->channel[first_non_void].type) { 2866 case UTIL_FORMAT_TYPE_FLOAT: 2867 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2868 break; 2869 case UTIL_FORMAT_TYPE_SIGNED: 2870 if (desc->channel[first_non_void].normalized) 2871 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 2872 else if (desc->channel[first_non_void].pure_integer) 2873 num_format = V_008F14_IMG_NUM_FORMAT_SINT; 2874 else 2875 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED; 2876 break; 2877 case UTIL_FORMAT_TYPE_UNSIGNED: 2878 if (desc->channel[first_non_void].normalized) 2879 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2880 else if (desc->channel[first_non_void].pure_integer) 2881 num_format = V_008F14_IMG_NUM_FORMAT_UINT; 2882 else 2883 num_format = V_008F14_IMG_NUM_FORMAT_USCALED; 2884 } 2885 } 2886 } 2887 2888 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void); 2889 if (format == ~0) { 2890 format = 0; 2891 } 2892 2893 base_level = 0; 2894 first_level = state->u.tex.first_level; 2895 last_level = state->u.tex.last_level; 2896 width = width0; 2897 height = height0; 2898 depth = texture->depth0; 2899 2900 if (force_level) { 2901 assert(force_level == first_level && 2902 force_level == last_level); 2903 base_level = force_level; 2904 first_level = 0; 2905 last_level = 0; 2906 width = u_minify(width, force_level); 2907 height = u_minify(height, force_level); 2908 depth = u_minify(depth, force_level); 2909 } 2910 2911 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format); 2912 2913 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 2914 height = 1; 2915 depth = texture->array_size; 2916 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 2917 depth = texture->array_size; 2918 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY) 2919 depth = texture->array_size / 6; 2920 2921 /* This is not needed if state trackers set last_layer correctly. */ 2922 if (state->target == PIPE_TEXTURE_1D || 2923 state->target == PIPE_TEXTURE_2D || 2924 state->target == PIPE_TEXTURE_RECT || 2925 state->target == PIPE_TEXTURE_CUBE) 2926 last_layer = state->u.tex.first_layer; 2927 2928 va = tmp->resource.gpu_address + surflevel[base_level].offset; 2929 2930 view->state[0] = va >> 8; 2931 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) | 2932 S_008F14_DATA_FORMAT(format) | 2933 S_008F14_NUM_FORMAT(num_format)); 2934 view->state[2] = (S_008F18_WIDTH(width - 1) | 2935 S_008F18_HEIGHT(height - 1)); 2936 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) | 2937 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | 2938 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | 2939 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | 2940 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ? 2941 0 : first_level) | 2942 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ? 2943 util_logbase2(texture->nr_samples) : 2944 last_level) | 2945 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) | 2946 S_008F1C_POW2_PAD(texture->last_level > 0) | 2947 S_008F1C_TYPE(si_tex_dim(texture->target, state->target, 2948 texture->nr_samples))); 2949 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1)); 2950 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) | 2951 S_008F24_LAST_ARRAY(last_layer)); 2952 2953 if (tmp->dcc_buffer) { 2954 uint64_t dcc_offset = surflevel[base_level].dcc_offset; 2955 unsigned swap = r600_translate_colorswap(pipe_format); 2956 2957 view->state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1); 2958 view->state[7] = (tmp->dcc_buffer->gpu_address + dcc_offset) >> 8; 2959 view->dcc_buffer = tmp->dcc_buffer; 2960 } else { 2961 view->state[6] = 0; 2962 view->state[7] = 0; 2963 } 2964 2965 /* Initialize the sampler view for FMASK. */ 2966 if (tmp->fmask.size) { 2967 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset; 2968 uint32_t fmask_format; 2969 2970 switch (texture->nr_samples) { 2971 case 2: 2972 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2; 2973 break; 2974 case 4: 2975 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4; 2976 break; 2977 case 8: 2978 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8; 2979 break; 2980 default: 2981 assert(0); 2982 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID; 2983 } 2984 2985 view->fmask_state[0] = va >> 8; 2986 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) | 2987 S_008F14_DATA_FORMAT(fmask_format) | 2988 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT); 2989 view->fmask_state[2] = S_008F18_WIDTH(width - 1) | 2990 S_008F18_HEIGHT(height - 1); 2991 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) | 2992 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) | 2993 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | 2994 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) | 2995 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) | 2996 S_008F1C_TYPE(si_tex_dim(texture->target, 2997 state->target, 0)); 2998 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) | 2999 S_008F20_PITCH(tmp->fmask.pitch_in_pixels - 1); 3000 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) | 3001 S_008F24_LAST_ARRAY(last_layer); 3002 view->fmask_state[6] = 0; 3003 view->fmask_state[7] = 0; 3004 } 3005 3006 return &view->base; 3007} 3008 3009static struct pipe_sampler_view * 3010si_create_sampler_view(struct pipe_context *ctx, 3011 struct pipe_resource *texture, 3012 const struct pipe_sampler_view *state) 3013{ 3014 return si_create_sampler_view_custom(ctx, texture, state, 3015 texture ? texture->width0 : 0, 3016 texture ? texture->height0 : 0, 0); 3017} 3018 3019static void si_sampler_view_destroy(struct pipe_context *ctx, 3020 struct pipe_sampler_view *state) 3021{ 3022 struct si_sampler_view *view = (struct si_sampler_view *)state; 3023 3024 if (view->resource && view->resource->b.b.target == PIPE_BUFFER) 3025 LIST_DELINIT(&view->list); 3026 3027 pipe_resource_reference(&state->texture, NULL); 3028 FREE(view); 3029} 3030 3031static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter) 3032{ 3033 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER || 3034 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER || 3035 (linear_filter && 3036 (wrap == PIPE_TEX_WRAP_CLAMP || 3037 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP)); 3038} 3039 3040static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state) 3041{ 3042 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST || 3043 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST; 3044 3045 return (state->border_color.ui[0] || state->border_color.ui[1] || 3046 state->border_color.ui[2] || state->border_color.ui[3]) && 3047 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) || 3048 wrap_mode_uses_border_color(state->wrap_t, linear_filter) || 3049 wrap_mode_uses_border_color(state->wrap_r, linear_filter)); 3050} 3051 3052static void *si_create_sampler_state(struct pipe_context *ctx, 3053 const struct pipe_sampler_state *state) 3054{ 3055 struct si_context *sctx = (struct si_context *)ctx; 3056 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state); 3057 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; 3058 unsigned border_color_type, border_color_index = 0; 3059 3060 if (!rstate) { 3061 return NULL; 3062 } 3063 3064 if (!sampler_state_needs_border_color(state)) 3065 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; 3066 else if (state->border_color.f[0] == 0 && 3067 state->border_color.f[1] == 0 && 3068 state->border_color.f[2] == 0 && 3069 state->border_color.f[3] == 0) 3070 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; 3071 else if (state->border_color.f[0] == 0 && 3072 state->border_color.f[1] == 0 && 3073 state->border_color.f[2] == 0 && 3074 state->border_color.f[3] == 1) 3075 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK; 3076 else if (state->border_color.f[0] == 1 && 3077 state->border_color.f[1] == 1 && 3078 state->border_color.f[2] == 1 && 3079 state->border_color.f[3] == 1) 3080 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE; 3081 else { 3082 int i; 3083 3084 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER; 3085 3086 /* Check if the border has been uploaded already. */ 3087 for (i = 0; i < sctx->border_color_count; i++) 3088 if (memcmp(&sctx->border_color_table[i], &state->border_color, 3089 sizeof(state->border_color)) == 0) 3090 break; 3091 3092 if (i >= SI_MAX_BORDER_COLORS) { 3093 /* Getting 4096 unique border colors is very unlikely. */ 3094 fprintf(stderr, "radeonsi: The border color table is full. " 3095 "Any new border colors will be just black. " 3096 "Please file a bug.\n"); 3097 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; 3098 } else { 3099 if (i == sctx->border_color_count) { 3100 /* Upload a new border color. */ 3101 memcpy(&sctx->border_color_table[i], &state->border_color, 3102 sizeof(state->border_color)); 3103 util_memcpy_cpu_to_le32(&sctx->border_color_map[i], 3104 &state->border_color, 3105 sizeof(state->border_color)); 3106 sctx->border_color_count++; 3107 } 3108 3109 border_color_index = i; 3110 } 3111 } 3112 3113 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | 3114 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) | 3115 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) | 3116 r600_tex_aniso_filter(state->max_anisotropy) << 9 | 3117 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) | 3118 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) | 3119 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map)); 3120 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | 3121 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8))); 3122 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) | 3123 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) | 3124 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) | 3125 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter))); 3126 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) | 3127 S_008F3C_BORDER_COLOR_TYPE(border_color_type); 3128 return rstate; 3129} 3130 3131static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask) 3132{ 3133 struct si_context *sctx = (struct si_context *)ctx; 3134 3135 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask) 3136 return; 3137 3138 sctx->sample_mask.sample_mask = sample_mask; 3139 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom); 3140} 3141 3142static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom) 3143{ 3144 struct radeon_winsys_cs *cs = sctx->b.gfx.cs; 3145 unsigned mask = sctx->sample_mask.sample_mask; 3146 3147 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2); 3148 radeon_emit(cs, mask | (mask << 16)); 3149 radeon_emit(cs, mask | (mask << 16)); 3150} 3151 3152static void si_delete_sampler_state(struct pipe_context *ctx, void *state) 3153{ 3154 free(state); 3155} 3156 3157/* 3158 * Vertex elements & buffers 3159 */ 3160 3161static void *si_create_vertex_elements(struct pipe_context *ctx, 3162 unsigned count, 3163 const struct pipe_vertex_element *elements) 3164{ 3165 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element); 3166 int i; 3167 3168 assert(count < SI_MAX_ATTRIBS); 3169 if (!v) 3170 return NULL; 3171 3172 v->count = count; 3173 for (i = 0; i < count; ++i) { 3174 const struct util_format_description *desc; 3175 unsigned data_format, num_format; 3176 int first_non_void; 3177 3178 desc = util_format_description(elements[i].src_format); 3179 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format); 3180 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void); 3181 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void); 3182 3183 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | 3184 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | 3185 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | 3186 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | 3187 S_008F0C_NUM_FORMAT(num_format) | 3188 S_008F0C_DATA_FORMAT(data_format); 3189 v->format_size[i] = desc->block.bits / 8; 3190 } 3191 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); 3192 3193 return v; 3194} 3195 3196static void si_bind_vertex_elements(struct pipe_context *ctx, void *state) 3197{ 3198 struct si_context *sctx = (struct si_context *)ctx; 3199 struct si_vertex_element *v = (struct si_vertex_element*)state; 3200 3201 sctx->vertex_elements = v; 3202 sctx->vertex_buffers_dirty = true; 3203} 3204 3205static void si_delete_vertex_element(struct pipe_context *ctx, void *state) 3206{ 3207 struct si_context *sctx = (struct si_context *)ctx; 3208 3209 if (sctx->vertex_elements == state) 3210 sctx->vertex_elements = NULL; 3211 FREE(state); 3212} 3213 3214static void si_set_vertex_buffers(struct pipe_context *ctx, 3215 unsigned start_slot, unsigned count, 3216 const struct pipe_vertex_buffer *buffers) 3217{ 3218 struct si_context *sctx = (struct si_context *)ctx; 3219 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot; 3220 int i; 3221 3222 assert(start_slot + count <= Elements(sctx->vertex_buffer)); 3223 3224 if (buffers) { 3225 for (i = 0; i < count; i++) { 3226 const struct pipe_vertex_buffer *src = buffers + i; 3227 struct pipe_vertex_buffer *dsti = dst + i; 3228 3229 pipe_resource_reference(&dsti->buffer, src->buffer); 3230 dsti->buffer_offset = src->buffer_offset; 3231 dsti->stride = src->stride; 3232 r600_context_add_resource_size(ctx, src->buffer); 3233 } 3234 } else { 3235 for (i = 0; i < count; i++) { 3236 pipe_resource_reference(&dst[i].buffer, NULL); 3237 } 3238 } 3239 sctx->vertex_buffers_dirty = true; 3240} 3241 3242static void si_set_index_buffer(struct pipe_context *ctx, 3243 const struct pipe_index_buffer *ib) 3244{ 3245 struct si_context *sctx = (struct si_context *)ctx; 3246 3247 if (ib) { 3248 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer); 3249 memcpy(&sctx->index_buffer, ib, sizeof(*ib)); 3250 r600_context_add_resource_size(ctx, ib->buffer); 3251 } else { 3252 pipe_resource_reference(&sctx->index_buffer.buffer, NULL); 3253 } 3254} 3255 3256/* 3257 * Misc 3258 */ 3259static void si_set_polygon_stipple(struct pipe_context *ctx, 3260 const struct pipe_poly_stipple *state) 3261{ 3262 struct si_context *sctx = (struct si_context *)ctx; 3263 struct pipe_resource *tex; 3264 struct pipe_sampler_view *view; 3265 bool is_zero = true; 3266 bool is_one = true; 3267 int i; 3268 3269 /* The hardware obeys 0 and 1 swizzles in the descriptor even if 3270 * the resource is NULL/invalid. Take advantage of this fact and skip 3271 * texture allocation if the stipple pattern is constant. 3272 * 3273 * This is an optimization for the common case when stippling isn't 3274 * used but set_polygon_stipple is still called by st/mesa. 3275 */ 3276 for (i = 0; i < Elements(state->stipple); i++) { 3277 is_zero = is_zero && state->stipple[i] == 0; 3278 is_one = is_one && state->stipple[i] == 0xffffffff; 3279 } 3280 3281 if (is_zero || is_one) { 3282 struct pipe_sampler_view templ = {{0}}; 3283 3284 templ.swizzle_r = PIPE_SWIZZLE_ZERO; 3285 templ.swizzle_g = PIPE_SWIZZLE_ZERO; 3286 templ.swizzle_b = PIPE_SWIZZLE_ZERO; 3287 /* The pattern should be inverted in the texture. */ 3288 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO; 3289 3290 view = ctx->create_sampler_view(ctx, NULL, &templ); 3291 } else { 3292 /* Create a new texture. */ 3293 tex = util_pstipple_create_stipple_texture(ctx, state->stipple); 3294 if (!tex) 3295 return; 3296 3297 view = util_pstipple_create_sampler_view(ctx, tex); 3298 pipe_resource_reference(&tex, NULL); 3299 } 3300 3301 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 3302 SI_POLY_STIPPLE_SAMPLER, 1, &view); 3303 pipe_sampler_view_reference(&view, NULL); 3304 3305 /* Bind the sampler state if needed. */ 3306 if (!sctx->pstipple_sampler_state) { 3307 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx); 3308 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT, 3309 SI_POLY_STIPPLE_SAMPLER, 1, 3310 &sctx->pstipple_sampler_state); 3311 } 3312} 3313 3314static void si_set_tess_state(struct pipe_context *ctx, 3315 const float default_outer_level[4], 3316 const float default_inner_level[2]) 3317{ 3318 struct si_context *sctx = (struct si_context *)ctx; 3319 struct pipe_constant_buffer cb; 3320 float array[8]; 3321 3322 memcpy(array, default_outer_level, sizeof(float) * 4); 3323 memcpy(array+4, default_inner_level, sizeof(float) * 2); 3324 3325 cb.buffer = NULL; 3326 cb.user_buffer = NULL; 3327 cb.buffer_size = sizeof(array); 3328 3329 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer, 3330 (void*)array, sizeof(array), 3331 &cb.buffer_offset); 3332 3333 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL, 3334 SI_DRIVER_STATE_CONST_BUF, &cb); 3335 pipe_resource_reference(&cb.buffer, NULL); 3336} 3337 3338static void si_texture_barrier(struct pipe_context *ctx) 3339{ 3340 struct si_context *sctx = (struct si_context *)ctx; 3341 3342 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 | 3343 SI_CONTEXT_INV_GLOBAL_L2 | 3344 SI_CONTEXT_FLUSH_AND_INV_CB; 3345} 3346 3347static void *si_create_blend_custom(struct si_context *sctx, unsigned mode) 3348{ 3349 struct pipe_blend_state blend; 3350 3351 memset(&blend, 0, sizeof(blend)); 3352 blend.independent_blend_enable = true; 3353 blend.rt[0].colormask = 0xf; 3354 return si_create_blend_state_mode(&sctx->b.b, &blend, mode); 3355} 3356 3357static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw, 3358 bool include_draw_vbo) 3359{ 3360 si_need_cs_space((struct si_context*)ctx); 3361} 3362 3363static void si_init_config(struct si_context *sctx); 3364 3365void si_init_state_functions(struct si_context *sctx) 3366{ 3367 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond); 3368 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin); 3369 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable); 3370 3371 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush); 3372 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state); 3373 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs); 3374 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state); 3375 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config); 3376 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask); 3377 si_init_atom(sctx, &sctx->cb_target_mask, &sctx->atoms.s.cb_target_mask, si_emit_cb_target_mask); 3378 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color); 3379 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs); 3380 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state); 3381 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors); 3382 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports); 3383 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref); 3384 3385 sctx->b.b.create_blend_state = si_create_blend_state; 3386 sctx->b.b.bind_blend_state = si_bind_blend_state; 3387 sctx->b.b.delete_blend_state = si_delete_blend_state; 3388 sctx->b.b.set_blend_color = si_set_blend_color; 3389 3390 sctx->b.b.create_rasterizer_state = si_create_rs_state; 3391 sctx->b.b.bind_rasterizer_state = si_bind_rs_state; 3392 sctx->b.b.delete_rasterizer_state = si_delete_rs_state; 3393 3394 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state; 3395 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state; 3396 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state; 3397 3398 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx); 3399 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE); 3400 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS); 3401 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR); 3402 3403 sctx->b.b.set_clip_state = si_set_clip_state; 3404 sctx->b.b.set_scissor_states = si_set_scissor_states; 3405 sctx->b.b.set_viewport_states = si_set_viewport_states; 3406 sctx->b.b.set_stencil_ref = si_set_stencil_ref; 3407 3408 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state; 3409 sctx->b.b.get_sample_position = cayman_get_sample_position; 3410 3411 sctx->b.b.create_sampler_state = si_create_sampler_state; 3412 sctx->b.b.delete_sampler_state = si_delete_sampler_state; 3413 3414 sctx->b.b.create_sampler_view = si_create_sampler_view; 3415 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy; 3416 3417 sctx->b.b.set_sample_mask = si_set_sample_mask; 3418 3419 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements; 3420 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements; 3421 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element; 3422 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers; 3423 sctx->b.b.set_index_buffer = si_set_index_buffer; 3424 3425 sctx->b.b.texture_barrier = si_texture_barrier; 3426 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple; 3427 sctx->b.b.set_min_samples = si_set_min_samples; 3428 sctx->b.b.set_tess_state = si_set_tess_state; 3429 3430 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state; 3431 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space; 3432 3433 sctx->b.b.draw_vbo = si_draw_vbo; 3434 3435 if (sctx->b.chip_class >= CIK) { 3436 sctx->b.dma_copy = cik_sdma_copy; 3437 } else { 3438 sctx->b.dma_copy = si_dma_copy; 3439 } 3440 3441 si_init_config(sctx); 3442} 3443 3444static void 3445si_write_harvested_raster_configs(struct si_context *sctx, 3446 struct si_pm4_state *pm4, 3447 unsigned raster_config, 3448 unsigned raster_config_1) 3449{ 3450 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1); 3451 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1); 3452 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask; 3453 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16); 3454 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2); 3455 unsigned rb_per_se = num_rb / num_se; 3456 unsigned se_mask[4]; 3457 unsigned se; 3458 3459 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; 3460 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; 3461 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; 3462 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; 3463 3464 assert(num_se == 1 || num_se == 2 || num_se == 4); 3465 assert(sh_per_se == 1 || sh_per_se == 2); 3466 assert(rb_per_pkr == 1 || rb_per_pkr == 2); 3467 3468 /* XXX: I can't figure out what the *_XSEL and *_YSEL 3469 * fields are for, so I'm leaving them as their default 3470 * values. */ 3471 3472 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || 3473 (!se_mask[2] && !se_mask[3]))) { 3474 raster_config_1 &= C_028354_SE_PAIR_MAP; 3475 3476 if (!se_mask[0] && !se_mask[1]) { 3477 raster_config_1 |= 3478 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3); 3479 } else { 3480 raster_config_1 |= 3481 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0); 3482 } 3483 } 3484 3485 for (se = 0; se < num_se; se++) { 3486 unsigned raster_config_se = raster_config; 3487 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); 3488 unsigned pkr1_mask = pkr0_mask << rb_per_pkr; 3489 int idx = (se / 2) * 2; 3490 3491 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { 3492 raster_config_se &= C_028350_SE_MAP; 3493 3494 if (!se_mask[idx]) { 3495 raster_config_se |= 3496 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3); 3497 } else { 3498 raster_config_se |= 3499 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0); 3500 } 3501 } 3502 3503 pkr0_mask &= rb_mask; 3504 pkr1_mask &= rb_mask; 3505 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { 3506 raster_config_se &= C_028350_PKR_MAP; 3507 3508 if (!pkr0_mask) { 3509 raster_config_se |= 3510 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3); 3511 } else { 3512 raster_config_se |= 3513 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0); 3514 } 3515 } 3516 3517 if (rb_per_se >= 2) { 3518 unsigned rb0_mask = 1 << (se * rb_per_se); 3519 unsigned rb1_mask = rb0_mask << 1; 3520 3521 rb0_mask &= rb_mask; 3522 rb1_mask &= rb_mask; 3523 if (!rb0_mask || !rb1_mask) { 3524 raster_config_se &= C_028350_RB_MAP_PKR0; 3525 3526 if (!rb0_mask) { 3527 raster_config_se |= 3528 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3); 3529 } else { 3530 raster_config_se |= 3531 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0); 3532 } 3533 } 3534 3535 if (rb_per_se > 2) { 3536 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); 3537 rb1_mask = rb0_mask << 1; 3538 rb0_mask &= rb_mask; 3539 rb1_mask &= rb_mask; 3540 if (!rb0_mask || !rb1_mask) { 3541 raster_config_se &= C_028350_RB_MAP_PKR1; 3542 3543 if (!rb0_mask) { 3544 raster_config_se |= 3545 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3); 3546 } else { 3547 raster_config_se |= 3548 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0); 3549 } 3550 } 3551 } 3552 } 3553 3554 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ 3555 if (sctx->b.chip_class < CIK) 3556 si_pm4_set_reg(pm4, GRBM_GFX_INDEX, 3557 SE_INDEX(se) | SH_BROADCAST_WRITES | 3558 INSTANCE_BROADCAST_WRITES); 3559 else 3560 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX, 3561 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) | 3562 S_030800_INSTANCE_BROADCAST_WRITES(1)); 3563 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se); 3564 if (sctx->b.chip_class >= CIK) 3565 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); 3566 } 3567 3568 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ 3569 if (sctx->b.chip_class < CIK) 3570 si_pm4_set_reg(pm4, GRBM_GFX_INDEX, 3571 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES | 3572 INSTANCE_BROADCAST_WRITES); 3573 else 3574 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX, 3575 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) | 3576 S_030800_INSTANCE_BROADCAST_WRITES(1)); 3577} 3578 3579static void si_init_config(struct si_context *sctx) 3580{ 3581 struct si_screen *sscreen = sctx->screen; 3582 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16); 3583 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask; 3584 unsigned raster_config, raster_config_1; 3585 uint64_t border_color_va = sctx->border_color_buffer->gpu_address; 3586 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 3587 int i; 3588 3589 if (!pm4) 3590 return; 3591 3592 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL); 3593 si_pm4_cmd_add(pm4, 0x80000000); 3594 si_pm4_cmd_add(pm4, 0x80000000); 3595 si_pm4_cmd_end(pm4, false); 3596 3597 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64)); 3598 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0)); 3599 3600 /* FIXME calculate these values somehow ??? */ 3601 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES); 3602 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40); 3603 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2); 3604 3605 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); 3606 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); 3607 3608 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); 3609 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); 3610 if (sctx->b.chip_class < CIK) 3611 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | 3612 S_008A14_CLIP_VTX_REORDER_ENA(1)); 3613 3614 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210); 3615 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98); 3616 3617 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0); 3618 3619 for (i = 0; i < 16; i++) { 3620 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0); 3621 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0)); 3622 } 3623 3624 switch (sctx->screen->b.family) { 3625 case CHIP_TAHITI: 3626 case CHIP_PITCAIRN: 3627 raster_config = 0x2a00126a; 3628 raster_config_1 = 0x00000000; 3629 break; 3630 case CHIP_VERDE: 3631 raster_config = 0x0000124a; 3632 raster_config_1 = 0x00000000; 3633 break; 3634 case CHIP_OLAND: 3635 raster_config = 0x00000082; 3636 raster_config_1 = 0x00000000; 3637 break; 3638 case CHIP_HAINAN: 3639 raster_config = 0x00000000; 3640 raster_config_1 = 0x00000000; 3641 break; 3642 case CHIP_BONAIRE: 3643 raster_config = 0x16000012; 3644 raster_config_1 = 0x00000000; 3645 break; 3646 case CHIP_HAWAII: 3647 raster_config = 0x3a00161a; 3648 raster_config_1 = 0x0000002e; 3649 break; 3650 case CHIP_FIJI: 3651 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) { 3652 /* old kernels with old tiling config */ 3653 raster_config = 0x16000012; 3654 raster_config_1 = 0x0000002a; 3655 } else { 3656 raster_config = 0x3a00161a; 3657 raster_config_1 = 0x0000002e; 3658 } 3659 break; 3660 case CHIP_TONGA: 3661 raster_config = 0x16000012; 3662 raster_config_1 = 0x0000002a; 3663 break; 3664 case CHIP_ICELAND: 3665 raster_config = 0x00000002; 3666 raster_config_1 = 0x00000000; 3667 break; 3668 case CHIP_CARRIZO: 3669 raster_config = 0x00000002; 3670 raster_config_1 = 0x00000000; 3671 break; 3672 case CHIP_KAVERI: 3673 /* KV should be 0x00000002, but that causes problems with radeon */ 3674 raster_config = 0x00000000; /* 0x00000002 */ 3675 raster_config_1 = 0x00000000; 3676 break; 3677 case CHIP_KABINI: 3678 case CHIP_MULLINS: 3679 case CHIP_STONEY: 3680 raster_config = 0x00000000; 3681 raster_config_1 = 0x00000000; 3682 break; 3683 default: 3684 fprintf(stderr, 3685 "radeonsi: Unknown GPU, using 0 for raster_config\n"); 3686 raster_config = 0x00000000; 3687 raster_config_1 = 0x00000000; 3688 break; 3689 } 3690 3691 /* Always use the default config when all backends are enabled 3692 * (or when we failed to determine the enabled backends). 3693 */ 3694 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) { 3695 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 3696 raster_config); 3697 if (sctx->b.chip_class >= CIK) 3698 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 3699 raster_config_1); 3700 } else { 3701 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1); 3702 } 3703 3704 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1)); 3705 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1)); 3706 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, 3707 S_028244_BR_X(16384) | S_028244_BR_Y(16384)); 3708 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0); 3709 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, 3710 S_028034_BR_X(16384) | S_028034_BR_Y(16384)); 3711 3712 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); 3713 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 3714 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */ 3715 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0); 3716 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0); 3717 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0)); 3718 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0)); 3719 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0)); 3720 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0)); 3721 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); 3722 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); 3723 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); 3724 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 3725 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 3726 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE)); 3727 3728 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); 3729 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); 3730 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0); 3731 3732 if (sctx->b.chip_class >= CIK) { 3733 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0); 3734 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff)); 3735 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff)); 3736 3737 if (sscreen->b.info.num_good_compute_units / 3738 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) { 3739 /* Too few available compute units per SH. Disallowing 3740 * VS to run on CU0 could hurt us more than late VS 3741 * allocation would help. 3742 * 3743 * LATE_ALLOC_VS = 2 is the highest safe number. 3744 */ 3745 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff)); 3746 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff)); 3747 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2)); 3748 } else { 3749 /* Set LATE_ALLOC_VS == 31. It should be less than 3750 * the number of scratch waves. Limitations: 3751 * - VS can't execute on CU0. 3752 * - If HS writes outputs to LDS, LS can't execute on CU0. 3753 */ 3754 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe)); 3755 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe)); 3756 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31)); 3757 } 3758 3759 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff)); 3760 } 3761 3762 if (sctx->b.chip_class >= VI) { 3763 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL, 3764 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) | 3765 S_028424_OVERWRITE_COMBINER_WATERMARK(4)); 3766 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30); 3767 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32); 3768 } 3769 3770 if (sctx->b.family == CHIP_STONEY) 3771 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0); 3772 3773 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8); 3774 if (sctx->b.chip_class >= CIK) 3775 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40); 3776 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ, 3777 RADEON_PRIO_BORDER_COLORS); 3778 3779 si_pm4_upload_indirect_buffer(sctx, pm4); 3780 sctx->init_config = pm4; 3781} 3782