si_state.c revision eaabb4ead07ae043ecc789024028e225ebd0f318
1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Christian König <christian.koenig@amd.com> 25 */ 26 27#include <byteswap.h> 28 29#include "util/u_memory.h" 30#include "util/u_framebuffer.h" 31#include "util/u_blitter.h" 32#include "util/u_helpers.h" 33#include "util/u_math.h" 34#include "util/u_pack_color.h" 35#include "util/u_upload_mgr.h" 36#include "util/u_format_s3tc.h" 37#include "tgsi/tgsi_parse.h" 38#include "radeonsi_pipe.h" 39#include "radeonsi_shader.h" 40#include "si_state.h" 41#include "sid.h" 42 43/* 44 * inferred framebuffer and blender state 45 */ 46static void si_update_fb_blend_state(struct r600_context *rctx) 47{ 48 struct si_pm4_state *pm4; 49 struct si_state_blend *blend = rctx->queued.named.blend; 50 uint32_t mask; 51 52 if (blend == NULL) 53 return; 54 55 pm4 = CALLOC_STRUCT(si_pm4_state); 56 if (pm4 == NULL) 57 return; 58 59 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1; 60 mask &= blend->cb_target_mask; 61 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask); 62 63 si_pm4_set_state(rctx, fb_blend, pm4); 64} 65 66/* 67 * Blender functions 68 */ 69 70static uint32_t si_translate_blend_function(int blend_func) 71{ 72 switch (blend_func) { 73 case PIPE_BLEND_ADD: 74 return V_028780_COMB_DST_PLUS_SRC; 75 case PIPE_BLEND_SUBTRACT: 76 return V_028780_COMB_SRC_MINUS_DST; 77 case PIPE_BLEND_REVERSE_SUBTRACT: 78 return V_028780_COMB_DST_MINUS_SRC; 79 case PIPE_BLEND_MIN: 80 return V_028780_COMB_MIN_DST_SRC; 81 case PIPE_BLEND_MAX: 82 return V_028780_COMB_MAX_DST_SRC; 83 default: 84 R600_ERR("Unknown blend function %d\n", blend_func); 85 assert(0); 86 break; 87 } 88 return 0; 89} 90 91static uint32_t si_translate_blend_factor(int blend_fact) 92{ 93 switch (blend_fact) { 94 case PIPE_BLENDFACTOR_ONE: 95 return V_028780_BLEND_ONE; 96 case PIPE_BLENDFACTOR_SRC_COLOR: 97 return V_028780_BLEND_SRC_COLOR; 98 case PIPE_BLENDFACTOR_SRC_ALPHA: 99 return V_028780_BLEND_SRC_ALPHA; 100 case PIPE_BLENDFACTOR_DST_ALPHA: 101 return V_028780_BLEND_DST_ALPHA; 102 case PIPE_BLENDFACTOR_DST_COLOR: 103 return V_028780_BLEND_DST_COLOR; 104 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 105 return V_028780_BLEND_SRC_ALPHA_SATURATE; 106 case PIPE_BLENDFACTOR_CONST_COLOR: 107 return V_028780_BLEND_CONSTANT_COLOR; 108 case PIPE_BLENDFACTOR_CONST_ALPHA: 109 return V_028780_BLEND_CONSTANT_ALPHA; 110 case PIPE_BLENDFACTOR_ZERO: 111 return V_028780_BLEND_ZERO; 112 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 113 return V_028780_BLEND_ONE_MINUS_SRC_COLOR; 114 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 115 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; 116 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 117 return V_028780_BLEND_ONE_MINUS_DST_ALPHA; 118 case PIPE_BLENDFACTOR_INV_DST_COLOR: 119 return V_028780_BLEND_ONE_MINUS_DST_COLOR; 120 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 121 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; 122 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 123 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; 124 case PIPE_BLENDFACTOR_SRC1_COLOR: 125 return V_028780_BLEND_SRC1_COLOR; 126 case PIPE_BLENDFACTOR_SRC1_ALPHA: 127 return V_028780_BLEND_SRC1_ALPHA; 128 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 129 return V_028780_BLEND_INV_SRC1_COLOR; 130 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 131 return V_028780_BLEND_INV_SRC1_ALPHA; 132 default: 133 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 134 assert(0); 135 break; 136 } 137 return 0; 138} 139 140static void *si_create_blend_state(struct pipe_context *ctx, 141 const struct pipe_blend_state *state) 142{ 143 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend); 144 struct si_pm4_state *pm4 = &blend->pm4; 145 146 uint32_t color_control; 147 148 if (blend == NULL) 149 return NULL; 150 151 color_control = S_028808_MODE(V_028808_CB_NORMAL); 152 if (state->logicop_enable) { 153 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4)); 154 } else { 155 color_control |= S_028808_ROP3(0xcc); 156 } 157 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); 158 159 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0); 160 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0); 161 162 blend->cb_target_mask = 0; 163 for (int i = 0; i < 8; i++) { 164 /* state->rt entries > 0 only written if independent blending */ 165 const int j = state->independent_blend_enable ? i : 0; 166 167 unsigned eqRGB = state->rt[j].rgb_func; 168 unsigned srcRGB = state->rt[j].rgb_src_factor; 169 unsigned dstRGB = state->rt[j].rgb_dst_factor; 170 unsigned eqA = state->rt[j].alpha_func; 171 unsigned srcA = state->rt[j].alpha_src_factor; 172 unsigned dstA = state->rt[j].alpha_dst_factor; 173 174 unsigned blend_cntl = 0; 175 176 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 177 blend->cb_target_mask |= state->rt[j].colormask << (4 * i); 178 179 if (!state->rt[j].blend_enable) { 180 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 181 continue; 182 } 183 184 blend_cntl |= S_028780_ENABLE(1); 185 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); 186 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); 187 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); 188 189 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 190 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); 191 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); 192 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); 193 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); 194 } 195 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 196 } 197 198 return blend; 199} 200 201static void si_bind_blend_state(struct pipe_context *ctx, void *state) 202{ 203 struct r600_context *rctx = (struct r600_context *)ctx; 204 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state); 205 si_update_fb_blend_state(rctx); 206} 207 208static void si_delete_blend_state(struct pipe_context *ctx, void *state) 209{ 210 struct r600_context *rctx = (struct r600_context *)ctx; 211 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state); 212} 213 214static void si_set_blend_color(struct pipe_context *ctx, 215 const struct pipe_blend_color *state) 216{ 217 struct r600_context *rctx = (struct r600_context *)ctx; 218 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 219 220 if (pm4 == NULL) 221 return; 222 223 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0])); 224 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1])); 225 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2])); 226 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3])); 227 228 si_pm4_set_state(rctx, blend_color, pm4); 229} 230 231/* 232 * Clipping, scissors and viewport 233 */ 234 235static void si_set_clip_state(struct pipe_context *ctx, 236 const struct pipe_clip_state *state) 237{ 238 struct r600_context *rctx = (struct r600_context *)ctx; 239 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 240 struct pipe_constant_buffer cb; 241 242 if (pm4 == NULL) 243 return; 244 245 for (int i = 0; i < 6; i++) { 246 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16, 247 fui(state->ucp[i][0])); 248 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16, 249 fui(state->ucp[i][1])); 250 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16, 251 fui(state->ucp[i][2])); 252 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16, 253 fui(state->ucp[i][3])); 254 } 255 256 cb.buffer = NULL; 257 cb.user_buffer = state->ucp; 258 cb.buffer_offset = 0; 259 cb.buffer_size = 4*4*8; 260 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb); 261 pipe_resource_reference(&cb.buffer, NULL); 262 263 si_pm4_set_state(rctx, clip, pm4); 264} 265 266static void si_set_scissor_states(struct pipe_context *ctx, 267 unsigned start_slot, 268 unsigned num_scissors, 269 const struct pipe_scissor_state *state) 270{ 271 struct r600_context *rctx = (struct r600_context *)ctx; 272 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 273 uint32_t tl, br; 274 275 if (pm4 == NULL) 276 return; 277 278 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny); 279 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 280 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl); 281 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br); 282 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl); 283 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br); 284 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl); 285 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br); 286 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl); 287 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br); 288 289 si_pm4_set_state(rctx, scissor, pm4); 290} 291 292static void si_set_viewport_states(struct pipe_context *ctx, 293 unsigned start_slot, 294 unsigned num_viewports, 295 const struct pipe_viewport_state *state) 296{ 297 struct r600_context *rctx = (struct r600_context *)ctx; 298 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport); 299 struct si_pm4_state *pm4 = &viewport->pm4; 300 301 if (viewport == NULL) 302 return; 303 304 viewport->viewport = *state; 305 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000); 306 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000); 307 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0])); 308 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0])); 309 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1])); 310 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1])); 311 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2])); 312 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2])); 313 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F); 314 315 si_pm4_set_state(rctx, viewport, viewport); 316} 317 318/* 319 * inferred state between framebuffer and rasterizer 320 */ 321static void si_update_fb_rs_state(struct r600_context *rctx) 322{ 323 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer; 324 struct si_pm4_state *pm4; 325 unsigned offset_db_fmt_cntl = 0, depth; 326 float offset_units; 327 328 if (!rs || !rctx->framebuffer.zsbuf) 329 return; 330 331 offset_units = rctx->queued.named.rasterizer->offset_units; 332 switch (rctx->framebuffer.zsbuf->texture->format) { 333 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 334 case PIPE_FORMAT_X8Z24_UNORM: 335 case PIPE_FORMAT_Z24X8_UNORM: 336 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 337 depth = -24; 338 offset_units *= 2.0f; 339 break; 340 case PIPE_FORMAT_Z32_FLOAT: 341 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 342 depth = -23; 343 offset_units *= 1.0f; 344 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 345 break; 346 case PIPE_FORMAT_Z16_UNORM: 347 depth = -16; 348 offset_units *= 4.0f; 349 break; 350 default: 351 return; 352 } 353 354 pm4 = CALLOC_STRUCT(si_pm4_state); 355 /* FIXME some of those reg can be computed with cso */ 356 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 357 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 358 fui(rctx->queued.named.rasterizer->offset_scale)); 359 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units)); 360 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 361 fui(rctx->queued.named.rasterizer->offset_scale)); 362 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units)); 363 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl); 364 365 si_pm4_set_state(rctx, fb_rs, pm4); 366} 367 368/* 369 * Rasterizer 370 */ 371 372static uint32_t si_translate_fill(uint32_t func) 373{ 374 switch(func) { 375 case PIPE_POLYGON_MODE_FILL: 376 return V_028814_X_DRAW_TRIANGLES; 377 case PIPE_POLYGON_MODE_LINE: 378 return V_028814_X_DRAW_LINES; 379 case PIPE_POLYGON_MODE_POINT: 380 return V_028814_X_DRAW_POINTS; 381 default: 382 assert(0); 383 return V_028814_X_DRAW_POINTS; 384 } 385} 386 387static void *si_create_rs_state(struct pipe_context *ctx, 388 const struct pipe_rasterizer_state *state) 389{ 390 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer); 391 struct si_pm4_state *pm4 = &rs->pm4; 392 unsigned tmp; 393 unsigned prov_vtx = 1, polygon_dual_mode; 394 unsigned clip_rule; 395 float psize_min, psize_max; 396 397 if (rs == NULL) { 398 return NULL; 399 } 400 401 rs->two_side = state->light_twoside; 402 rs->clip_plane_enable = state->clip_plane_enable; 403 404 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 405 state->fill_back != PIPE_POLYGON_MODE_FILL); 406 407 if (state->flatshade_first) 408 prov_vtx = 0; 409 410 rs->flatshade = state->flatshade; 411 rs->sprite_coord_enable = state->sprite_coord_enable; 412 rs->pa_sc_line_stipple = state->line_stipple_enable ? 413 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 414 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 415 rs->pa_su_sc_mode_cntl = 416 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 417 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 418 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 419 S_028814_FACE(!state->front_ccw) | 420 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 421 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 422 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 423 S_028814_POLY_MODE(polygon_dual_mode) | 424 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | 425 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)); 426 rs->pa_cl_clip_cntl = 427 S_028810_PS_UCP_MODE(3) | 428 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 429 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 430 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 431 432 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 433 434 /* offset */ 435 rs->offset_units = state->offset_units; 436 rs->offset_scale = state->offset_scale * 12.0f; 437 438 tmp = S_0286D4_FLAT_SHADE_ENA(1); 439 if (state->sprite_coord_enable) { 440 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 441 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | 442 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | 443 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | 444 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1); 445 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 446 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 447 } 448 } 449 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp); 450 451 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000); 452 /* point size 12.4 fixed point */ 453 tmp = (unsigned)(state->point_size * 8.0); 454 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 455 456 if (state->point_size_per_vertex) { 457 psize_min = util_get_min_point_size(state); 458 psize_max = 8192; 459 } else { 460 /* Force the point size to be as if the vertex output was disabled. */ 461 psize_min = state->point_size; 462 psize_max = state->point_size; 463 } 464 /* Divide by two, because 0.5 = 1 pixel. */ 465 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX, 466 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | 467 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); 468 469 tmp = (unsigned)state->line_width * 8; 470 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); 471 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0, 472 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable)); 473 474 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400); 475 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL, 476 S_028BE4_PIX_CENTER(state->half_pixel_center)); 477 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000); 478 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000); 479 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000); 480 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000); 481 482 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 483 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule); 484 485 return rs; 486} 487 488static void si_bind_rs_state(struct pipe_context *ctx, void *state) 489{ 490 struct r600_context *rctx = (struct r600_context *)ctx; 491 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state; 492 493 if (state == NULL) 494 return; 495 496 // TODO 497 rctx->sprite_coord_enable = rs->sprite_coord_enable; 498 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; 499 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl; 500 501 si_pm4_bind_state(rctx, rasterizer, rs); 502 si_update_fb_rs_state(rctx); 503} 504 505static void si_delete_rs_state(struct pipe_context *ctx, void *state) 506{ 507 struct r600_context *rctx = (struct r600_context *)ctx; 508 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state); 509} 510 511/* 512 * infeered state between dsa and stencil ref 513 */ 514static void si_update_dsa_stencil_ref(struct r600_context *rctx) 515{ 516 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 517 struct pipe_stencil_ref *ref = &rctx->stencil_ref; 518 struct si_state_dsa *dsa = rctx->queued.named.dsa; 519 520 if (pm4 == NULL) 521 return; 522 523 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK, 524 S_028430_STENCILTESTVAL(ref->ref_value[0]) | 525 S_028430_STENCILMASK(dsa->valuemask[0]) | 526 S_028430_STENCILWRITEMASK(dsa->writemask[0]) | 527 S_028430_STENCILOPVAL(1)); 528 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF, 529 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) | 530 S_028434_STENCILMASK_BF(dsa->valuemask[1]) | 531 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) | 532 S_028434_STENCILOPVAL_BF(1)); 533 534 si_pm4_set_state(rctx, dsa_stencil_ref, pm4); 535} 536 537static void si_set_pipe_stencil_ref(struct pipe_context *ctx, 538 const struct pipe_stencil_ref *state) 539{ 540 struct r600_context *rctx = (struct r600_context *)ctx; 541 rctx->stencil_ref = *state; 542 si_update_dsa_stencil_ref(rctx); 543} 544 545 546/* 547 * DSA 548 */ 549 550static uint32_t si_translate_stencil_op(int s_op) 551{ 552 switch (s_op) { 553 case PIPE_STENCIL_OP_KEEP: 554 return V_02842C_STENCIL_KEEP; 555 case PIPE_STENCIL_OP_ZERO: 556 return V_02842C_STENCIL_ZERO; 557 case PIPE_STENCIL_OP_REPLACE: 558 return V_02842C_STENCIL_REPLACE_TEST; 559 case PIPE_STENCIL_OP_INCR: 560 return V_02842C_STENCIL_ADD_CLAMP; 561 case PIPE_STENCIL_OP_DECR: 562 return V_02842C_STENCIL_SUB_CLAMP; 563 case PIPE_STENCIL_OP_INCR_WRAP: 564 return V_02842C_STENCIL_ADD_WRAP; 565 case PIPE_STENCIL_OP_DECR_WRAP: 566 return V_02842C_STENCIL_SUB_WRAP; 567 case PIPE_STENCIL_OP_INVERT: 568 return V_02842C_STENCIL_INVERT; 569 default: 570 R600_ERR("Unknown stencil op %d", s_op); 571 assert(0); 572 break; 573 } 574 return 0; 575} 576 577static void *si_create_dsa_state(struct pipe_context *ctx, 578 const struct pipe_depth_stencil_alpha_state *state) 579{ 580 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa); 581 struct si_pm4_state *pm4 = &dsa->pm4; 582 unsigned db_depth_control; 583 unsigned db_render_override, db_render_control; 584 uint32_t db_stencil_control = 0; 585 586 if (dsa == NULL) { 587 return NULL; 588 } 589 590 dsa->valuemask[0] = state->stencil[0].valuemask; 591 dsa->valuemask[1] = state->stencil[1].valuemask; 592 dsa->writemask[0] = state->stencil[0].writemask; 593 dsa->writemask[1] = state->stencil[1].writemask; 594 595 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 596 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 597 S_028800_ZFUNC(state->depth.func); 598 599 /* stencil */ 600 if (state->stencil[0].enabled) { 601 db_depth_control |= S_028800_STENCIL_ENABLE(1); 602 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); 603 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op)); 604 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op)); 605 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op)); 606 607 if (state->stencil[1].enabled) { 608 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 609 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); 610 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op)); 611 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op)); 612 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op)); 613 } 614 } 615 616 /* alpha */ 617 if (state->alpha.enabled) { 618 dsa->alpha_func = state->alpha.func; 619 dsa->alpha_ref = state->alpha.ref_value; 620 } else { 621 dsa->alpha_func = PIPE_FUNC_ALWAYS; 622 } 623 624 /* misc */ 625 db_render_control = 0; 626 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) | 627 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 628 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); 629 /* TODO db_render_override depends on query */ 630 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000); 631 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000); 632 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000); 633 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000); 634 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control); 635 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); 636 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control); 637 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override); 638 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); 639 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); 640 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); 641 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); 642 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00); 643 dsa->db_render_override = db_render_override; 644 645 return dsa; 646} 647 648static void si_bind_dsa_state(struct pipe_context *ctx, void *state) 649{ 650 struct r600_context *rctx = (struct r600_context *)ctx; 651 struct si_state_dsa *dsa = state; 652 653 if (state == NULL) 654 return; 655 656 si_pm4_bind_state(rctx, dsa, dsa); 657 si_update_dsa_stencil_ref(rctx); 658} 659 660static void si_delete_dsa_state(struct pipe_context *ctx, void *state) 661{ 662 struct r600_context *rctx = (struct r600_context *)ctx; 663 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state); 664} 665 666static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth, 667 bool copy_stencil) 668{ 669 struct pipe_depth_stencil_alpha_state dsa; 670 struct si_state_dsa *state; 671 672 memset(&dsa, 0, sizeof(dsa)); 673 674 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 675 if (copy_depth || copy_stencil) { 676 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, 677 S_028000_DEPTH_COPY(copy_depth) | 678 S_028000_STENCIL_COPY(copy_stencil) | 679 S_028000_COPY_CENTROID(1)); 680 } else { 681 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, 682 S_028000_DEPTH_COMPRESS_DISABLE(1) | 683 S_028000_STENCIL_COMPRESS_DISABLE(1)); 684 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE, 685 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) | 686 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 687 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) | 688 S_02800C_DISABLE_TILE_RATE_TILES(1)); 689 } 690 691 return state; 692} 693 694/* 695 * format translation 696 */ 697static uint32_t si_translate_colorformat(enum pipe_format format) 698{ 699 switch (format) { 700 /* 8-bit buffers. */ 701 case PIPE_FORMAT_A8_UNORM: 702 case PIPE_FORMAT_A8_SNORM: 703 case PIPE_FORMAT_A8_UINT: 704 case PIPE_FORMAT_A8_SINT: 705 case PIPE_FORMAT_I8_UNORM: 706 case PIPE_FORMAT_I8_SNORM: 707 case PIPE_FORMAT_I8_UINT: 708 case PIPE_FORMAT_I8_SINT: 709 case PIPE_FORMAT_L8_UNORM: 710 case PIPE_FORMAT_L8_SNORM: 711 case PIPE_FORMAT_L8_UINT: 712 case PIPE_FORMAT_L8_SINT: 713 case PIPE_FORMAT_L8_SRGB: 714 case PIPE_FORMAT_R8_UNORM: 715 case PIPE_FORMAT_R8_SNORM: 716 case PIPE_FORMAT_R8_UINT: 717 case PIPE_FORMAT_R8_SINT: 718 return V_028C70_COLOR_8; 719 720 /* 16-bit buffers. */ 721 case PIPE_FORMAT_B5G6R5_UNORM: 722 return V_028C70_COLOR_5_6_5; 723 724 case PIPE_FORMAT_B5G5R5A1_UNORM: 725 case PIPE_FORMAT_B5G5R5X1_UNORM: 726 return V_028C70_COLOR_1_5_5_5; 727 728 case PIPE_FORMAT_B4G4R4A4_UNORM: 729 case PIPE_FORMAT_B4G4R4X4_UNORM: 730 return V_028C70_COLOR_4_4_4_4; 731 732 case PIPE_FORMAT_L8A8_UNORM: 733 case PIPE_FORMAT_L8A8_SNORM: 734 case PIPE_FORMAT_L8A8_UINT: 735 case PIPE_FORMAT_L8A8_SINT: 736 case PIPE_FORMAT_R8G8_SNORM: 737 case PIPE_FORMAT_R8G8_UNORM: 738 case PIPE_FORMAT_R8G8_UINT: 739 case PIPE_FORMAT_R8G8_SINT: 740 return V_028C70_COLOR_8_8; 741 742 case PIPE_FORMAT_Z16_UNORM: 743 case PIPE_FORMAT_R16_UNORM: 744 case PIPE_FORMAT_R16_SNORM: 745 case PIPE_FORMAT_R16_UINT: 746 case PIPE_FORMAT_R16_SINT: 747 case PIPE_FORMAT_R16_FLOAT: 748 case PIPE_FORMAT_L16_UNORM: 749 case PIPE_FORMAT_L16_SNORM: 750 case PIPE_FORMAT_L16_FLOAT: 751 case PIPE_FORMAT_I16_UNORM: 752 case PIPE_FORMAT_I16_SNORM: 753 case PIPE_FORMAT_I16_FLOAT: 754 case PIPE_FORMAT_A16_UNORM: 755 case PIPE_FORMAT_A16_SNORM: 756 case PIPE_FORMAT_A16_FLOAT: 757 return V_028C70_COLOR_16; 758 759 /* 32-bit buffers. */ 760 case PIPE_FORMAT_A8B8G8R8_SRGB: 761 case PIPE_FORMAT_A8B8G8R8_UNORM: 762 case PIPE_FORMAT_A8R8G8B8_UNORM: 763 case PIPE_FORMAT_B8G8R8A8_SRGB: 764 case PIPE_FORMAT_B8G8R8A8_UNORM: 765 case PIPE_FORMAT_B8G8R8X8_UNORM: 766 case PIPE_FORMAT_R8G8B8A8_SNORM: 767 case PIPE_FORMAT_R8G8B8A8_UNORM: 768 case PIPE_FORMAT_R8G8B8X8_UNORM: 769 case PIPE_FORMAT_R8G8B8X8_SNORM: 770 case PIPE_FORMAT_R8G8B8X8_SRGB: 771 case PIPE_FORMAT_R8G8B8X8_UINT: 772 case PIPE_FORMAT_R8G8B8X8_SINT: 773 case PIPE_FORMAT_R8SG8SB8UX8U_NORM: 774 case PIPE_FORMAT_X8B8G8R8_UNORM: 775 case PIPE_FORMAT_X8R8G8B8_UNORM: 776 case PIPE_FORMAT_R8G8B8A8_SSCALED: 777 case PIPE_FORMAT_R8G8B8A8_USCALED: 778 case PIPE_FORMAT_R8G8B8A8_SINT: 779 case PIPE_FORMAT_R8G8B8A8_UINT: 780 return V_028C70_COLOR_8_8_8_8; 781 782 case PIPE_FORMAT_R10G10B10A2_UNORM: 783 case PIPE_FORMAT_R10G10B10X2_SNORM: 784 case PIPE_FORMAT_B10G10R10A2_UNORM: 785 case PIPE_FORMAT_B10G10R10A2_UINT: 786 case PIPE_FORMAT_B10G10R10X2_UNORM: 787 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 788 return V_028C70_COLOR_2_10_10_10; 789 790 case PIPE_FORMAT_Z24X8_UNORM: 791 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 792 return V_028C70_COLOR_8_24; 793 794 case PIPE_FORMAT_S8X24_UINT: 795 case PIPE_FORMAT_X8Z24_UNORM: 796 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 797 return V_028C70_COLOR_24_8; 798 799 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 800 return V_028C70_COLOR_X24_8_32_FLOAT; 801 802 case PIPE_FORMAT_I32_FLOAT: 803 case PIPE_FORMAT_L32_FLOAT: 804 case PIPE_FORMAT_R32_FLOAT: 805 case PIPE_FORMAT_A32_FLOAT: 806 case PIPE_FORMAT_Z32_FLOAT: 807 return V_028C70_COLOR_32; 808 809 case PIPE_FORMAT_L16A16_UNORM: 810 case PIPE_FORMAT_L16A16_SNORM: 811 case PIPE_FORMAT_L16A16_FLOAT: 812 case PIPE_FORMAT_R16G16_SSCALED: 813 case PIPE_FORMAT_R16G16_UNORM: 814 case PIPE_FORMAT_R16G16_SNORM: 815 case PIPE_FORMAT_R16G16_UINT: 816 case PIPE_FORMAT_R16G16_SINT: 817 case PIPE_FORMAT_R16G16_FLOAT: 818 return V_028C70_COLOR_16_16; 819 820 case PIPE_FORMAT_R11G11B10_FLOAT: 821 return V_028C70_COLOR_10_11_11; 822 823 /* 64-bit buffers. */ 824 case PIPE_FORMAT_R16G16B16A16_UINT: 825 case PIPE_FORMAT_R16G16B16A16_SINT: 826 case PIPE_FORMAT_R16G16B16A16_USCALED: 827 case PIPE_FORMAT_R16G16B16A16_SSCALED: 828 case PIPE_FORMAT_R16G16B16A16_UNORM: 829 case PIPE_FORMAT_R16G16B16A16_SNORM: 830 case PIPE_FORMAT_R16G16B16A16_FLOAT: 831 case PIPE_FORMAT_R16G16B16X16_UNORM: 832 case PIPE_FORMAT_R16G16B16X16_SNORM: 833 case PIPE_FORMAT_R16G16B16X16_FLOAT: 834 case PIPE_FORMAT_R16G16B16X16_UINT: 835 case PIPE_FORMAT_R16G16B16X16_SINT: 836 return V_028C70_COLOR_16_16_16_16; 837 838 case PIPE_FORMAT_L32A32_FLOAT: 839 case PIPE_FORMAT_L32A32_UINT: 840 case PIPE_FORMAT_L32A32_SINT: 841 case PIPE_FORMAT_R32G32_FLOAT: 842 case PIPE_FORMAT_R32G32_USCALED: 843 case PIPE_FORMAT_R32G32_SSCALED: 844 case PIPE_FORMAT_R32G32_SINT: 845 case PIPE_FORMAT_R32G32_UINT: 846 return V_028C70_COLOR_32_32; 847 848 /* 128-bit buffers. */ 849 case PIPE_FORMAT_R32G32B32A32_SNORM: 850 case PIPE_FORMAT_R32G32B32A32_UNORM: 851 case PIPE_FORMAT_R32G32B32A32_SSCALED: 852 case PIPE_FORMAT_R32G32B32A32_USCALED: 853 case PIPE_FORMAT_R32G32B32A32_SINT: 854 case PIPE_FORMAT_R32G32B32A32_UINT: 855 case PIPE_FORMAT_R32G32B32A32_FLOAT: 856 case PIPE_FORMAT_R32G32B32X32_FLOAT: 857 case PIPE_FORMAT_R32G32B32X32_UINT: 858 case PIPE_FORMAT_R32G32B32X32_SINT: 859 return V_028C70_COLOR_32_32_32_32; 860 861 /* YUV buffers. */ 862 case PIPE_FORMAT_UYVY: 863 case PIPE_FORMAT_YUYV: 864 /* 96-bit buffers. */ 865 case PIPE_FORMAT_R32G32B32_FLOAT: 866 /* 8-bit buffers. */ 867 case PIPE_FORMAT_L4A4_UNORM: 868 case PIPE_FORMAT_R4A4_UNORM: 869 case PIPE_FORMAT_A4R4_UNORM: 870 default: 871 return V_028C70_COLOR_INVALID; /* Unsupported. */ 872 } 873} 874 875static uint32_t si_translate_colorswap(enum pipe_format format) 876{ 877 switch (format) { 878 /* 8-bit buffers. */ 879 case PIPE_FORMAT_L4A4_UNORM: 880 case PIPE_FORMAT_A4R4_UNORM: 881 return V_028C70_SWAP_ALT; 882 883 case PIPE_FORMAT_A8_UNORM: 884 case PIPE_FORMAT_A8_SNORM: 885 case PIPE_FORMAT_A8_UINT: 886 case PIPE_FORMAT_A8_SINT: 887 case PIPE_FORMAT_R4A4_UNORM: 888 return V_028C70_SWAP_ALT_REV; 889 case PIPE_FORMAT_I8_UNORM: 890 case PIPE_FORMAT_I8_SNORM: 891 case PIPE_FORMAT_L8_UNORM: 892 case PIPE_FORMAT_L8_SNORM: 893 case PIPE_FORMAT_I8_UINT: 894 case PIPE_FORMAT_I8_SINT: 895 case PIPE_FORMAT_L8_UINT: 896 case PIPE_FORMAT_L8_SINT: 897 case PIPE_FORMAT_L8_SRGB: 898 case PIPE_FORMAT_R8_UNORM: 899 case PIPE_FORMAT_R8_SNORM: 900 case PIPE_FORMAT_R8_UINT: 901 case PIPE_FORMAT_R8_SINT: 902 return V_028C70_SWAP_STD; 903 904 /* 16-bit buffers. */ 905 case PIPE_FORMAT_B5G6R5_UNORM: 906 return V_028C70_SWAP_STD_REV; 907 908 case PIPE_FORMAT_B5G5R5A1_UNORM: 909 case PIPE_FORMAT_B5G5R5X1_UNORM: 910 return V_028C70_SWAP_ALT; 911 912 case PIPE_FORMAT_B4G4R4A4_UNORM: 913 case PIPE_FORMAT_B4G4R4X4_UNORM: 914 return V_028C70_SWAP_ALT; 915 916 case PIPE_FORMAT_Z16_UNORM: 917 return V_028C70_SWAP_STD; 918 919 case PIPE_FORMAT_L8A8_UNORM: 920 case PIPE_FORMAT_L8A8_SNORM: 921 case PIPE_FORMAT_L8A8_UINT: 922 case PIPE_FORMAT_L8A8_SINT: 923 return V_028C70_SWAP_ALT; 924 case PIPE_FORMAT_R8G8_SNORM: 925 case PIPE_FORMAT_R8G8_UNORM: 926 case PIPE_FORMAT_R8G8_UINT: 927 case PIPE_FORMAT_R8G8_SINT: 928 return V_028C70_SWAP_STD; 929 930 case PIPE_FORMAT_I16_UNORM: 931 case PIPE_FORMAT_I16_SNORM: 932 case PIPE_FORMAT_I16_FLOAT: 933 case PIPE_FORMAT_L16_UNORM: 934 case PIPE_FORMAT_L16_SNORM: 935 case PIPE_FORMAT_L16_FLOAT: 936 case PIPE_FORMAT_R16_UNORM: 937 case PIPE_FORMAT_R16_SNORM: 938 case PIPE_FORMAT_R16_UINT: 939 case PIPE_FORMAT_R16_SINT: 940 case PIPE_FORMAT_R16_FLOAT: 941 return V_028C70_SWAP_STD; 942 943 case PIPE_FORMAT_A16_UNORM: 944 case PIPE_FORMAT_A16_SNORM: 945 case PIPE_FORMAT_A16_FLOAT: 946 return V_028C70_SWAP_ALT_REV; 947 948 /* 32-bit buffers. */ 949 case PIPE_FORMAT_A8B8G8R8_SRGB: 950 return V_028C70_SWAP_STD_REV; 951 case PIPE_FORMAT_B8G8R8A8_SRGB: 952 return V_028C70_SWAP_ALT; 953 954 case PIPE_FORMAT_B8G8R8A8_UNORM: 955 case PIPE_FORMAT_B8G8R8X8_UNORM: 956 return V_028C70_SWAP_ALT; 957 958 case PIPE_FORMAT_A8R8G8B8_UNORM: 959 case PIPE_FORMAT_X8R8G8B8_UNORM: 960 return V_028C70_SWAP_ALT_REV; 961 case PIPE_FORMAT_R8G8B8A8_SNORM: 962 case PIPE_FORMAT_R8G8B8A8_UNORM: 963 case PIPE_FORMAT_R8G8B8A8_SSCALED: 964 case PIPE_FORMAT_R8G8B8A8_USCALED: 965 case PIPE_FORMAT_R8G8B8A8_SINT: 966 case PIPE_FORMAT_R8G8B8A8_UINT: 967 case PIPE_FORMAT_R8G8B8X8_UNORM: 968 case PIPE_FORMAT_R8G8B8X8_SNORM: 969 case PIPE_FORMAT_R8G8B8X8_SRGB: 970 case PIPE_FORMAT_R8G8B8X8_UINT: 971 case PIPE_FORMAT_R8G8B8X8_SINT: 972 return V_028C70_SWAP_STD; 973 974 case PIPE_FORMAT_A8B8G8R8_UNORM: 975 case PIPE_FORMAT_X8B8G8R8_UNORM: 976 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */ 977 return V_028C70_SWAP_STD_REV; 978 979 case PIPE_FORMAT_Z24X8_UNORM: 980 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 981 return V_028C70_SWAP_STD; 982 983 case PIPE_FORMAT_S8X24_UINT: 984 case PIPE_FORMAT_X8Z24_UNORM: 985 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 986 return V_028C70_SWAP_STD_REV; 987 988 case PIPE_FORMAT_R10G10B10A2_UNORM: 989 case PIPE_FORMAT_R10G10B10X2_SNORM: 990 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 991 return V_028C70_SWAP_STD; 992 993 case PIPE_FORMAT_B10G10R10A2_UNORM: 994 case PIPE_FORMAT_B10G10R10A2_UINT: 995 case PIPE_FORMAT_B10G10R10X2_UNORM: 996 return V_028C70_SWAP_ALT; 997 998 case PIPE_FORMAT_R11G11B10_FLOAT: 999 case PIPE_FORMAT_I32_FLOAT: 1000 case PIPE_FORMAT_L32_FLOAT: 1001 case PIPE_FORMAT_R32_FLOAT: 1002 case PIPE_FORMAT_R32_UINT: 1003 case PIPE_FORMAT_R32_SINT: 1004 case PIPE_FORMAT_Z32_FLOAT: 1005 case PIPE_FORMAT_R16G16_FLOAT: 1006 case PIPE_FORMAT_R16G16_UNORM: 1007 case PIPE_FORMAT_R16G16_SNORM: 1008 case PIPE_FORMAT_R16G16_UINT: 1009 case PIPE_FORMAT_R16G16_SINT: 1010 return V_028C70_SWAP_STD; 1011 1012 case PIPE_FORMAT_L16A16_UNORM: 1013 case PIPE_FORMAT_L16A16_SNORM: 1014 case PIPE_FORMAT_L16A16_FLOAT: 1015 return V_028C70_SWAP_ALT; 1016 1017 case PIPE_FORMAT_A32_FLOAT: 1018 return V_028C70_SWAP_ALT_REV; 1019 1020 /* 64-bit buffers. */ 1021 case PIPE_FORMAT_R32G32_FLOAT: 1022 case PIPE_FORMAT_R32G32_UINT: 1023 case PIPE_FORMAT_R32G32_SINT: 1024 case PIPE_FORMAT_R16G16B16A16_UNORM: 1025 case PIPE_FORMAT_R16G16B16A16_SNORM: 1026 case PIPE_FORMAT_R16G16B16A16_USCALED: 1027 case PIPE_FORMAT_R16G16B16A16_SSCALED: 1028 case PIPE_FORMAT_R16G16B16A16_UINT: 1029 case PIPE_FORMAT_R16G16B16A16_SINT: 1030 case PIPE_FORMAT_R16G16B16A16_FLOAT: 1031 case PIPE_FORMAT_R16G16B16X16_UNORM: 1032 case PIPE_FORMAT_R16G16B16X16_SNORM: 1033 case PIPE_FORMAT_R16G16B16X16_FLOAT: 1034 case PIPE_FORMAT_R16G16B16X16_UINT: 1035 case PIPE_FORMAT_R16G16B16X16_SINT: 1036 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1037 return V_028C70_SWAP_STD; 1038 1039 case PIPE_FORMAT_L32A32_FLOAT: 1040 case PIPE_FORMAT_L32A32_UINT: 1041 case PIPE_FORMAT_L32A32_SINT: 1042 return V_028C70_SWAP_ALT; 1043 1044 /* 128-bit buffers. */ 1045 case PIPE_FORMAT_R32G32B32A32_FLOAT: 1046 case PIPE_FORMAT_R32G32B32A32_SNORM: 1047 case PIPE_FORMAT_R32G32B32A32_UNORM: 1048 case PIPE_FORMAT_R32G32B32A32_SSCALED: 1049 case PIPE_FORMAT_R32G32B32A32_USCALED: 1050 case PIPE_FORMAT_R32G32B32A32_SINT: 1051 case PIPE_FORMAT_R32G32B32A32_UINT: 1052 case PIPE_FORMAT_R32G32B32X32_FLOAT: 1053 case PIPE_FORMAT_R32G32B32X32_UINT: 1054 case PIPE_FORMAT_R32G32B32X32_SINT: 1055 return V_028C70_SWAP_STD; 1056 default: 1057 R600_ERR("unsupported colorswap format %d\n", format); 1058 return ~0U; 1059 } 1060 return ~0U; 1061} 1062 1063static uint32_t si_colorformat_endian_swap(uint32_t colorformat) 1064{ 1065 if (R600_BIG_ENDIAN) { 1066 switch(colorformat) { 1067 /* 8-bit buffers. */ 1068 case V_028C70_COLOR_8: 1069 return V_028C70_ENDIAN_NONE; 1070 1071 /* 16-bit buffers. */ 1072 case V_028C70_COLOR_5_6_5: 1073 case V_028C70_COLOR_1_5_5_5: 1074 case V_028C70_COLOR_4_4_4_4: 1075 case V_028C70_COLOR_16: 1076 case V_028C70_COLOR_8_8: 1077 return V_028C70_ENDIAN_8IN16; 1078 1079 /* 32-bit buffers. */ 1080 case V_028C70_COLOR_8_8_8_8: 1081 case V_028C70_COLOR_2_10_10_10: 1082 case V_028C70_COLOR_8_24: 1083 case V_028C70_COLOR_24_8: 1084 case V_028C70_COLOR_16_16: 1085 return V_028C70_ENDIAN_8IN32; 1086 1087 /* 64-bit buffers. */ 1088 case V_028C70_COLOR_16_16_16_16: 1089 return V_028C70_ENDIAN_8IN16; 1090 1091 case V_028C70_COLOR_32_32: 1092 return V_028C70_ENDIAN_8IN32; 1093 1094 /* 128-bit buffers. */ 1095 case V_028C70_COLOR_32_32_32_32: 1096 return V_028C70_ENDIAN_8IN32; 1097 default: 1098 return V_028C70_ENDIAN_NONE; /* Unsupported. */ 1099 } 1100 } else { 1101 return V_028C70_ENDIAN_NONE; 1102 } 1103} 1104 1105/* Returns the size in bits of the widest component of a CB format */ 1106static unsigned si_colorformat_max_comp_size(uint32_t colorformat) 1107{ 1108 switch(colorformat) { 1109 case V_028C70_COLOR_4_4_4_4: 1110 return 4; 1111 1112 case V_028C70_COLOR_1_5_5_5: 1113 case V_028C70_COLOR_5_5_5_1: 1114 return 5; 1115 1116 case V_028C70_COLOR_5_6_5: 1117 return 6; 1118 1119 case V_028C70_COLOR_8: 1120 case V_028C70_COLOR_8_8: 1121 case V_028C70_COLOR_8_8_8_8: 1122 return 8; 1123 1124 case V_028C70_COLOR_10_10_10_2: 1125 case V_028C70_COLOR_2_10_10_10: 1126 return 10; 1127 1128 case V_028C70_COLOR_10_11_11: 1129 case V_028C70_COLOR_11_11_10: 1130 return 11; 1131 1132 case V_028C70_COLOR_16: 1133 case V_028C70_COLOR_16_16: 1134 case V_028C70_COLOR_16_16_16_16: 1135 return 16; 1136 1137 case V_028C70_COLOR_8_24: 1138 case V_028C70_COLOR_24_8: 1139 return 24; 1140 1141 case V_028C70_COLOR_32: 1142 case V_028C70_COLOR_32_32: 1143 case V_028C70_COLOR_32_32_32_32: 1144 case V_028C70_COLOR_X24_8_32_FLOAT: 1145 return 32; 1146 } 1147 1148 assert(!"Unknown maximum component size"); 1149 return 0; 1150} 1151 1152static uint32_t si_translate_dbformat(enum pipe_format format) 1153{ 1154 switch (format) { 1155 case PIPE_FORMAT_Z16_UNORM: 1156 return V_028040_Z_16; 1157 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1158 case PIPE_FORMAT_X8Z24_UNORM: 1159 case PIPE_FORMAT_Z24X8_UNORM: 1160 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1161 return V_028040_Z_24; /* deprecated on SI */ 1162 case PIPE_FORMAT_Z32_FLOAT: 1163 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1164 return V_028040_Z_32_FLOAT; 1165 default: 1166 return V_028040_Z_INVALID; 1167 } 1168} 1169 1170/* 1171 * Texture translation 1172 */ 1173 1174static uint32_t si_translate_texformat(struct pipe_screen *screen, 1175 enum pipe_format format, 1176 const struct util_format_description *desc, 1177 int first_non_void) 1178{ 1179 struct r600_screen *rscreen = (struct r600_screen*)screen; 1180 bool enable_s3tc = rscreen->info.drm_minor >= 31; 1181 boolean uniform = TRUE; 1182 int i; 1183 1184 /* Colorspace (return non-RGB formats directly). */ 1185 switch (desc->colorspace) { 1186 /* Depth stencil formats */ 1187 case UTIL_FORMAT_COLORSPACE_ZS: 1188 switch (format) { 1189 case PIPE_FORMAT_Z16_UNORM: 1190 return V_008F14_IMG_DATA_FORMAT_16; 1191 case PIPE_FORMAT_X24S8_UINT: 1192 case PIPE_FORMAT_Z24X8_UNORM: 1193 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1194 return V_008F14_IMG_DATA_FORMAT_8_24; 1195 case PIPE_FORMAT_X8Z24_UNORM: 1196 case PIPE_FORMAT_S8X24_UINT: 1197 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1198 return V_008F14_IMG_DATA_FORMAT_24_8; 1199 case PIPE_FORMAT_S8_UINT: 1200 return V_008F14_IMG_DATA_FORMAT_8; 1201 case PIPE_FORMAT_Z32_FLOAT: 1202 return V_008F14_IMG_DATA_FORMAT_32; 1203 case PIPE_FORMAT_X32_S8X24_UINT: 1204 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1205 return V_008F14_IMG_DATA_FORMAT_X24_8_32; 1206 default: 1207 goto out_unknown; 1208 } 1209 1210 case UTIL_FORMAT_COLORSPACE_YUV: 1211 goto out_unknown; /* TODO */ 1212 1213 case UTIL_FORMAT_COLORSPACE_SRGB: 1214 if (desc->nr_channels != 4 && desc->nr_channels != 1) 1215 goto out_unknown; 1216 break; 1217 1218 default: 1219 break; 1220 } 1221 1222 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 1223 if (!enable_s3tc) 1224 goto out_unknown; 1225 1226 switch (format) { 1227 case PIPE_FORMAT_RGTC1_SNORM: 1228 case PIPE_FORMAT_LATC1_SNORM: 1229 case PIPE_FORMAT_RGTC1_UNORM: 1230 case PIPE_FORMAT_LATC1_UNORM: 1231 return V_008F14_IMG_DATA_FORMAT_BC4; 1232 case PIPE_FORMAT_RGTC2_SNORM: 1233 case PIPE_FORMAT_LATC2_SNORM: 1234 case PIPE_FORMAT_RGTC2_UNORM: 1235 case PIPE_FORMAT_LATC2_UNORM: 1236 return V_008F14_IMG_DATA_FORMAT_BC5; 1237 default: 1238 goto out_unknown; 1239 } 1240 } 1241 1242 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 1243 1244 if (!enable_s3tc) 1245 goto out_unknown; 1246 1247 if (!util_format_s3tc_enabled) { 1248 goto out_unknown; 1249 } 1250 1251 switch (format) { 1252 case PIPE_FORMAT_DXT1_RGB: 1253 case PIPE_FORMAT_DXT1_RGBA: 1254 case PIPE_FORMAT_DXT1_SRGB: 1255 case PIPE_FORMAT_DXT1_SRGBA: 1256 return V_008F14_IMG_DATA_FORMAT_BC1; 1257 case PIPE_FORMAT_DXT3_RGBA: 1258 case PIPE_FORMAT_DXT3_SRGBA: 1259 return V_008F14_IMG_DATA_FORMAT_BC2; 1260 case PIPE_FORMAT_DXT5_RGBA: 1261 case PIPE_FORMAT_DXT5_SRGBA: 1262 return V_008F14_IMG_DATA_FORMAT_BC3; 1263 default: 1264 goto out_unknown; 1265 } 1266 } 1267 1268 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 1269 return V_008F14_IMG_DATA_FORMAT_5_9_9_9; 1270 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 1271 return V_008F14_IMG_DATA_FORMAT_10_11_11; 1272 } 1273 1274 /* R8G8Bx_SNORM - TODO CxV8U8 */ 1275 1276 /* See whether the components are of the same size. */ 1277 for (i = 1; i < desc->nr_channels; i++) { 1278 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1279 } 1280 1281 /* Non-uniform formats. */ 1282 if (!uniform) { 1283 switch(desc->nr_channels) { 1284 case 3: 1285 if (desc->channel[0].size == 5 && 1286 desc->channel[1].size == 6 && 1287 desc->channel[2].size == 5) { 1288 return V_008F14_IMG_DATA_FORMAT_5_6_5; 1289 } 1290 goto out_unknown; 1291 case 4: 1292 if (desc->channel[0].size == 5 && 1293 desc->channel[1].size == 5 && 1294 desc->channel[2].size == 5 && 1295 desc->channel[3].size == 1) { 1296 return V_008F14_IMG_DATA_FORMAT_1_5_5_5; 1297 } 1298 if (desc->channel[0].size == 10 && 1299 desc->channel[1].size == 10 && 1300 desc->channel[2].size == 10 && 1301 desc->channel[3].size == 2) { 1302 return V_008F14_IMG_DATA_FORMAT_2_10_10_10; 1303 } 1304 goto out_unknown; 1305 } 1306 goto out_unknown; 1307 } 1308 1309 if (first_non_void < 0 || first_non_void > 3) 1310 goto out_unknown; 1311 1312 /* uniform formats */ 1313 switch (desc->channel[first_non_void].size) { 1314 case 4: 1315 switch (desc->nr_channels) { 1316#if 0 /* Not supported for render targets */ 1317 case 2: 1318 return V_008F14_IMG_DATA_FORMAT_4_4; 1319#endif 1320 case 4: 1321 return V_008F14_IMG_DATA_FORMAT_4_4_4_4; 1322 } 1323 break; 1324 case 8: 1325 switch (desc->nr_channels) { 1326 case 1: 1327 return V_008F14_IMG_DATA_FORMAT_8; 1328 case 2: 1329 return V_008F14_IMG_DATA_FORMAT_8_8; 1330 case 4: 1331 return V_008F14_IMG_DATA_FORMAT_8_8_8_8; 1332 } 1333 break; 1334 case 16: 1335 switch (desc->nr_channels) { 1336 case 1: 1337 return V_008F14_IMG_DATA_FORMAT_16; 1338 case 2: 1339 return V_008F14_IMG_DATA_FORMAT_16_16; 1340 case 4: 1341 return V_008F14_IMG_DATA_FORMAT_16_16_16_16; 1342 } 1343 break; 1344 case 32: 1345 switch (desc->nr_channels) { 1346 case 1: 1347 return V_008F14_IMG_DATA_FORMAT_32; 1348 case 2: 1349 return V_008F14_IMG_DATA_FORMAT_32_32; 1350#if 0 /* Not supported for render targets */ 1351 case 3: 1352 return V_008F14_IMG_DATA_FORMAT_32_32_32; 1353#endif 1354 case 4: 1355 return V_008F14_IMG_DATA_FORMAT_32_32_32_32; 1356 } 1357 } 1358 1359out_unknown: 1360 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1361 return ~0; 1362} 1363 1364static unsigned si_tex_wrap(unsigned wrap) 1365{ 1366 switch (wrap) { 1367 default: 1368 case PIPE_TEX_WRAP_REPEAT: 1369 return V_008F30_SQ_TEX_WRAP; 1370 case PIPE_TEX_WRAP_CLAMP: 1371 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER; 1372 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 1373 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL; 1374 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 1375 return V_008F30_SQ_TEX_CLAMP_BORDER; 1376 case PIPE_TEX_WRAP_MIRROR_REPEAT: 1377 return V_008F30_SQ_TEX_MIRROR; 1378 case PIPE_TEX_WRAP_MIRROR_CLAMP: 1379 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 1380 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 1381 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 1382 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 1383 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER; 1384 } 1385} 1386 1387static unsigned si_tex_filter(unsigned filter) 1388{ 1389 switch (filter) { 1390 default: 1391 case PIPE_TEX_FILTER_NEAREST: 1392 return V_008F38_SQ_TEX_XY_FILTER_POINT; 1393 case PIPE_TEX_FILTER_LINEAR: 1394 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR; 1395 } 1396} 1397 1398static unsigned si_tex_mipfilter(unsigned filter) 1399{ 1400 switch (filter) { 1401 case PIPE_TEX_MIPFILTER_NEAREST: 1402 return V_008F38_SQ_TEX_Z_FILTER_POINT; 1403 case PIPE_TEX_MIPFILTER_LINEAR: 1404 return V_008F38_SQ_TEX_Z_FILTER_LINEAR; 1405 default: 1406 case PIPE_TEX_MIPFILTER_NONE: 1407 return V_008F38_SQ_TEX_Z_FILTER_NONE; 1408 } 1409} 1410 1411static unsigned si_tex_compare(unsigned compare) 1412{ 1413 switch (compare) { 1414 default: 1415 case PIPE_FUNC_NEVER: 1416 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER; 1417 case PIPE_FUNC_LESS: 1418 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS; 1419 case PIPE_FUNC_EQUAL: 1420 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL; 1421 case PIPE_FUNC_LEQUAL: 1422 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 1423 case PIPE_FUNC_GREATER: 1424 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER; 1425 case PIPE_FUNC_NOTEQUAL: 1426 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 1427 case PIPE_FUNC_GEQUAL: 1428 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 1429 case PIPE_FUNC_ALWAYS: 1430 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS; 1431 } 1432} 1433 1434static unsigned si_tex_dim(unsigned dim) 1435{ 1436 switch (dim) { 1437 default: 1438 case PIPE_TEXTURE_1D: 1439 return V_008F1C_SQ_RSRC_IMG_1D; 1440 case PIPE_TEXTURE_1D_ARRAY: 1441 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY; 1442 case PIPE_TEXTURE_2D: 1443 case PIPE_TEXTURE_RECT: 1444 return V_008F1C_SQ_RSRC_IMG_2D; 1445 case PIPE_TEXTURE_2D_ARRAY: 1446 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY; 1447 case PIPE_TEXTURE_3D: 1448 return V_008F1C_SQ_RSRC_IMG_3D; 1449 case PIPE_TEXTURE_CUBE: 1450 return V_008F1C_SQ_RSRC_IMG_CUBE; 1451 } 1452} 1453 1454/* 1455 * Format support testing 1456 */ 1457 1458static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 1459{ 1460 return si_translate_texformat(screen, format, util_format_description(format), 1461 util_format_get_first_non_void_channel(format)) != ~0U; 1462} 1463 1464static uint32_t si_translate_vertexformat(struct pipe_screen *screen, 1465 enum pipe_format format, 1466 const struct util_format_description *desc, 1467 int first_non_void) 1468{ 1469 unsigned type = desc->channel[first_non_void].type; 1470 int i; 1471 1472 if (type == UTIL_FORMAT_TYPE_FIXED) 1473 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1474 1475 /* See whether the components are of the same size. */ 1476 for (i = 0; i < desc->nr_channels; i++) { 1477 if (desc->channel[first_non_void].size != desc->channel[i].size) 1478 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1479 } 1480 1481 switch (desc->channel[first_non_void].size) { 1482 case 8: 1483 switch (desc->nr_channels) { 1484 case 1: 1485 return V_008F0C_BUF_DATA_FORMAT_8; 1486 case 2: 1487 return V_008F0C_BUF_DATA_FORMAT_8_8; 1488 case 3: 1489 case 4: 1490 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8; 1491 } 1492 break; 1493 case 16: 1494 switch (desc->nr_channels) { 1495 case 1: 1496 return V_008F0C_BUF_DATA_FORMAT_16; 1497 case 2: 1498 return V_008F0C_BUF_DATA_FORMAT_16_16; 1499 case 3: 1500 case 4: 1501 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16; 1502 } 1503 break; 1504 case 32: 1505 if (type != UTIL_FORMAT_TYPE_FLOAT) 1506 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1507 1508 switch (desc->nr_channels) { 1509 case 1: 1510 return V_008F0C_BUF_DATA_FORMAT_32; 1511 case 2: 1512 return V_008F0C_BUF_DATA_FORMAT_32_32; 1513 case 3: 1514 return V_008F0C_BUF_DATA_FORMAT_32_32_32; 1515 case 4: 1516 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32; 1517 } 1518 break; 1519 } 1520 1521 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1522} 1523 1524static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format) 1525{ 1526 const struct util_format_description *desc; 1527 int first_non_void; 1528 unsigned data_format; 1529 1530 desc = util_format_description(format); 1531 first_non_void = util_format_get_first_non_void_channel(format); 1532 data_format = si_translate_vertexformat(screen, format, desc, first_non_void); 1533 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID; 1534} 1535 1536static bool si_is_colorbuffer_format_supported(enum pipe_format format) 1537{ 1538 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID && 1539 si_translate_colorswap(format) != ~0U; 1540} 1541 1542static bool si_is_zs_format_supported(enum pipe_format format) 1543{ 1544 return si_translate_dbformat(format) != V_028040_Z_INVALID; 1545} 1546 1547boolean si_is_format_supported(struct pipe_screen *screen, 1548 enum pipe_format format, 1549 enum pipe_texture_target target, 1550 unsigned sample_count, 1551 unsigned usage) 1552{ 1553 unsigned retval = 0; 1554 1555 if (target >= PIPE_MAX_TEXTURE_TYPES) { 1556 R600_ERR("r600: unsupported texture type %d\n", target); 1557 return FALSE; 1558 } 1559 1560 if (!util_format_is_supported(format, usage)) 1561 return FALSE; 1562 1563 /* Multisample */ 1564 if (sample_count > 1) 1565 return FALSE; 1566 1567 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 1568 si_is_sampler_format_supported(screen, format)) { 1569 retval |= PIPE_BIND_SAMPLER_VIEW; 1570 } 1571 1572 if ((usage & (PIPE_BIND_RENDER_TARGET | 1573 PIPE_BIND_DISPLAY_TARGET | 1574 PIPE_BIND_SCANOUT | 1575 PIPE_BIND_SHARED)) && 1576 si_is_colorbuffer_format_supported(format)) { 1577 retval |= usage & 1578 (PIPE_BIND_RENDER_TARGET | 1579 PIPE_BIND_DISPLAY_TARGET | 1580 PIPE_BIND_SCANOUT | 1581 PIPE_BIND_SHARED); 1582 } 1583 1584 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 1585 si_is_zs_format_supported(format)) { 1586 retval |= PIPE_BIND_DEPTH_STENCIL; 1587 } 1588 1589 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 1590 si_is_vertex_format_supported(screen, format)) { 1591 retval |= PIPE_BIND_VERTEX_BUFFER; 1592 } 1593 1594 if (usage & PIPE_BIND_TRANSFER_READ) 1595 retval |= PIPE_BIND_TRANSFER_READ; 1596 if (usage & PIPE_BIND_TRANSFER_WRITE) 1597 retval |= PIPE_BIND_TRANSFER_WRITE; 1598 1599 return retval == usage; 1600} 1601 1602static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level, bool stencil) 1603{ 1604 unsigned tile_mode_index = 0; 1605 1606 if (stencil) { 1607 tile_mode_index = rtex->surface.stencil_tiling_index[level]; 1608 } else { 1609 tile_mode_index = rtex->surface.tiling_index[level]; 1610 } 1611 return tile_mode_index; 1612} 1613 1614/* 1615 * framebuffer handling 1616 */ 1617 1618static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, 1619 const struct pipe_framebuffer_state *state, int cb) 1620{ 1621 struct r600_resource_texture *rtex; 1622 struct r600_surface *surf; 1623 unsigned level = state->cbufs[cb]->u.tex.level; 1624 unsigned pitch, slice; 1625 unsigned color_info, color_attrib; 1626 unsigned tile_mode_index; 1627 unsigned format, swap, ntype, endian; 1628 uint64_t offset; 1629 const struct util_format_description *desc; 1630 int i; 1631 unsigned blend_clamp = 0, blend_bypass = 0; 1632 unsigned max_comp_size; 1633 1634 surf = (struct r600_surface *)state->cbufs[cb]; 1635 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; 1636 1637 offset = rtex->surface.level[level].offset; 1638 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1639 offset += rtex->surface.level[level].slice_size * 1640 state->cbufs[cb]->u.tex.first_layer; 1641 } 1642 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; 1643 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1644 if (slice) { 1645 slice = slice - 1; 1646 } 1647 1648 tile_mode_index = si_tile_mode_index(rtex, level, false); 1649 1650 desc = util_format_description(surf->base.format); 1651 for (i = 0; i < 4; i++) { 1652 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1653 break; 1654 } 1655 } 1656 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { 1657 ntype = V_028C70_NUMBER_FLOAT; 1658 } else { 1659 ntype = V_028C70_NUMBER_UNORM; 1660 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1661 ntype = V_028C70_NUMBER_SRGB; 1662 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1663 if (desc->channel[i].pure_integer) { 1664 ntype = V_028C70_NUMBER_SINT; 1665 } else { 1666 assert(desc->channel[i].normalized); 1667 ntype = V_028C70_NUMBER_SNORM; 1668 } 1669 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1670 if (desc->channel[i].pure_integer) { 1671 ntype = V_028C70_NUMBER_UINT; 1672 } else { 1673 assert(desc->channel[i].normalized); 1674 ntype = V_028C70_NUMBER_UNORM; 1675 } 1676 } 1677 } 1678 1679 format = si_translate_colorformat(surf->base.format); 1680 if (format == V_028C70_COLOR_INVALID) { 1681 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format); 1682 } 1683 assert(format != V_028C70_COLOR_INVALID); 1684 swap = si_translate_colorswap(surf->base.format); 1685 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { 1686 endian = V_028C70_ENDIAN_NONE; 1687 } else { 1688 endian = si_colorformat_endian_swap(format); 1689 } 1690 1691 /* blend clamp should be set for all NORM/SRGB types */ 1692 if (ntype == V_028C70_NUMBER_UNORM || 1693 ntype == V_028C70_NUMBER_SNORM || 1694 ntype == V_028C70_NUMBER_SRGB) 1695 blend_clamp = 1; 1696 1697 /* set blend bypass according to docs if SINT/UINT or 1698 8/24 COLOR variants */ 1699 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT || 1700 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 || 1701 format == V_028C70_COLOR_X24_8_32_FLOAT) { 1702 blend_clamp = 0; 1703 blend_bypass = 1; 1704 } 1705 1706 color_info = S_028C70_FORMAT(format) | 1707 S_028C70_COMP_SWAP(swap) | 1708 S_028C70_BLEND_CLAMP(blend_clamp) | 1709 S_028C70_BLEND_BYPASS(blend_bypass) | 1710 S_028C70_NUMBER_TYPE(ntype) | 1711 S_028C70_ENDIAN(endian); 1712 1713 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) | 1714 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1); 1715 1716 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture); 1717 offset >>= 8; 1718 1719 /* FIXME handle enabling of CB beyond BASE8 which has different offset */ 1720 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); 1721 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset); 1722 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch)); 1723 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice)); 1724 1725 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1726 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000); 1727 } else { 1728 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 1729 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) | 1730 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer)); 1731 } 1732 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info); 1733 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib); 1734 1735 /* set CB_COLOR1_INFO for possible dual-src blending */ 1736 if (state->nr_cbufs == 1) { 1737 assert(cb == 0); 1738 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info); 1739 } 1740 1741 /* Determine pixel shader export format */ 1742 max_comp_size = si_colorformat_max_comp_size(format); 1743 if (ntype == V_028C70_NUMBER_SRGB || 1744 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) && 1745 max_comp_size <= 10) || 1746 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) { 1747 rctx->export_16bpc |= 1 << cb; 1748 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */ 1749 if (state->nr_cbufs == 1) 1750 rctx->export_16bpc |= 1 << 1; 1751 } 1752} 1753 1754static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, 1755 const struct pipe_framebuffer_state *state) 1756{ 1757 struct r600_resource_texture *rtex; 1758 struct r600_surface *surf; 1759 unsigned level, pitch, slice, format, tile_mode_index; 1760 uint32_t z_info, s_info; 1761 uint64_t z_offs, s_offs; 1762 1763 if (state->zsbuf == NULL) { 1764 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID)); 1765 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID)); 1766 return; 1767 } 1768 1769 surf = (struct r600_surface *)state->zsbuf; 1770 level = surf->base.u.tex.level; 1771 rtex = (struct r600_resource_texture*)surf->base.texture; 1772 1773 format = si_translate_dbformat(rtex->real_format); 1774 1775 if (format == V_028040_Z_INVALID) { 1776 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format); 1777 } 1778 assert(format != V_028040_Z_INVALID); 1779 1780 s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture); 1781 z_offs += rtex->surface.level[level].offset; 1782 s_offs += rtex->surface.stencil_level[level].offset; 1783 1784 z_offs >>= 8; 1785 s_offs >>= 8; 1786 1787 pitch = (rtex->surface.level[level].nblk_x / 8) - 1; 1788 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1789 if (slice) { 1790 slice = slice - 1; 1791 } 1792 1793 z_info = S_028040_FORMAT(format); 1794 if (rtex->surface.flags & RADEON_SURF_SBUFFER) 1795 s_info = S_028044_FORMAT(V_028044_STENCIL_8); 1796 else 1797 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID); 1798 1799 tile_mode_index = si_tile_mode_index(rtex, level, false); 1800 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index); 1801 tile_mode_index = si_tile_mode_index(rtex, level, true); 1802 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index); 1803 1804 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, 1805 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) | 1806 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer)); 1807 1808 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, S_02803C_ADDR5_SWIZZLE_MASK(1)); 1809 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info); 1810 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info); 1811 1812 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); 1813 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs); 1814 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs); 1815 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs); 1816 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs); 1817 1818 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch)); 1819 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice)); 1820} 1821 1822static void si_set_framebuffer_state(struct pipe_context *ctx, 1823 const struct pipe_framebuffer_state *state) 1824{ 1825 struct r600_context *rctx = (struct r600_context *)ctx; 1826 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 1827 uint32_t tl, br; 1828 int tl_x, tl_y, br_x, br_y; 1829 1830 if (pm4 == NULL) 1831 return; 1832 1833 si_pm4_inval_fb_cache(pm4, state->nr_cbufs); 1834 1835 if (state->zsbuf) 1836 si_pm4_inval_zsbuf_cache(pm4); 1837 1838 util_copy_framebuffer_state(&rctx->framebuffer, state); 1839 1840 /* build states */ 1841 rctx->export_16bpc = 0; 1842 for (int i = 0; i < state->nr_cbufs; i++) { 1843 si_cb(rctx, pm4, state, i); 1844 } 1845 assert(!(rctx->export_16bpc & ~0xff)); 1846 si_db(rctx, pm4, state); 1847 1848 tl_x = 0; 1849 tl_y = 0; 1850 br_x = state->width; 1851 br_y = state->height; 1852 1853 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y); 1854 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y); 1855 1856 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl); 1857 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br); 1858 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl); 1859 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br); 1860 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl); 1861 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br); 1862 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl); 1863 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br); 1864 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000); 1865 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 1866 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000); 1867 1868 si_pm4_set_state(rctx, framebuffer, pm4); 1869 si_update_fb_rs_state(rctx); 1870 si_update_fb_blend_state(rctx); 1871} 1872 1873/* 1874 * shaders 1875 */ 1876 1877/* Compute the key for the hw shader variant */ 1878static INLINE void si_shader_selector_key(struct pipe_context *ctx, 1879 struct si_pipe_shader_selector *sel, 1880 union si_shader_key *key) 1881{ 1882 struct r600_context *rctx = (struct r600_context *)ctx; 1883 memset(key, 0, sizeof(*key)); 1884 1885 if (sel->type == PIPE_SHADER_VERTEX) { 1886 unsigned i; 1887 if (!rctx->vertex_elements) 1888 return; 1889 1890 for (i = 0; i < rctx->vertex_elements->count; ++i) 1891 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor; 1892 1893 } else if (sel->type == PIPE_SHADER_FRAGMENT) { 1894 if (sel->fs_write_all) 1895 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs; 1896 key->ps.export_16bpc = rctx->export_16bpc; 1897 if (rctx->queued.named.rasterizer) { 1898 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side; 1899 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade; 1900 } 1901 if (rctx->queued.named.dsa) { 1902 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func; 1903 key->ps.alpha_ref = rctx->queued.named.dsa->alpha_ref; 1904 } else { 1905 key->ps.alpha_func = PIPE_FUNC_ALWAYS; 1906 } 1907 } 1908} 1909 1910/* Select the hw shader variant depending on the current state. 1911 * (*dirty) is set to 1 if current variant was changed */ 1912int si_shader_select(struct pipe_context *ctx, 1913 struct si_pipe_shader_selector *sel, 1914 unsigned *dirty) 1915{ 1916 union si_shader_key key; 1917 struct si_pipe_shader * shader = NULL; 1918 int r; 1919 1920 si_shader_selector_key(ctx, sel, &key); 1921 1922 /* Check if we don't need to change anything. 1923 * This path is also used for most shaders that don't need multiple 1924 * variants, it will cost just a computation of the key and this 1925 * test. */ 1926 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) { 1927 return 0; 1928 } 1929 1930 /* lookup if we have other variants in the list */ 1931 if (sel->num_shaders > 1) { 1932 struct si_pipe_shader *p = sel->current, *c = p->next_variant; 1933 1934 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) { 1935 p = c; 1936 c = c->next_variant; 1937 } 1938 1939 if (c) { 1940 p->next_variant = c->next_variant; 1941 shader = c; 1942 } 1943 } 1944 1945 if (unlikely(!shader)) { 1946 shader = CALLOC(1, sizeof(struct si_pipe_shader)); 1947 shader->selector = sel; 1948 shader->key = key; 1949 1950 r = si_pipe_shader_create(ctx, shader); 1951 if (unlikely(r)) { 1952 R600_ERR("Failed to build shader variant (type=%u) %d\n", 1953 sel->type, r); 1954 sel->current = NULL; 1955 FREE(shader); 1956 return r; 1957 } 1958 1959 /* We don't know the value of fs_write_all property until we built 1960 * at least one variant, so we may need to recompute the key (include 1961 * rctx->framebuffer.nr_cbufs) after building first variant. */ 1962 if (sel->type == PIPE_SHADER_FRAGMENT && 1963 sel->num_shaders == 0 && 1964 shader->shader.fs_write_all) { 1965 sel->fs_write_all = 1; 1966 si_shader_selector_key(ctx, sel, &shader->key); 1967 } 1968 1969 sel->num_shaders++; 1970 } 1971 1972 if (dirty) 1973 *dirty = 1; 1974 1975 shader->next_variant = sel->current; 1976 sel->current = shader; 1977 1978 return 0; 1979} 1980 1981static void *si_create_shader_state(struct pipe_context *ctx, 1982 const struct pipe_shader_state *state, 1983 unsigned pipe_shader_type) 1984{ 1985 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector); 1986 int r; 1987 1988 sel->type = pipe_shader_type; 1989 sel->tokens = tgsi_dup_tokens(state->tokens); 1990 sel->so = state->stream_output; 1991 1992 r = si_shader_select(ctx, sel, NULL); 1993 if (r) { 1994 free(sel); 1995 return NULL; 1996 } 1997 1998 return sel; 1999} 2000 2001static void *si_create_fs_state(struct pipe_context *ctx, 2002 const struct pipe_shader_state *state) 2003{ 2004 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT); 2005} 2006 2007static void *si_create_vs_state(struct pipe_context *ctx, 2008 const struct pipe_shader_state *state) 2009{ 2010 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX); 2011} 2012 2013static void si_bind_vs_shader(struct pipe_context *ctx, void *state) 2014{ 2015 struct r600_context *rctx = (struct r600_context *)ctx; 2016 struct si_pipe_shader_selector *sel = state; 2017 2018 if (rctx->vs_shader == sel) 2019 return; 2020 2021 rctx->vs_shader = sel; 2022 2023 if (sel && sel->current) 2024 si_pm4_bind_state(rctx, vs, sel->current->pm4); 2025 else 2026 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4); 2027} 2028 2029static void si_bind_ps_shader(struct pipe_context *ctx, void *state) 2030{ 2031 struct r600_context *rctx = (struct r600_context *)ctx; 2032 struct si_pipe_shader_selector *sel = state; 2033 2034 if (rctx->ps_shader == sel) 2035 return; 2036 2037 rctx->ps_shader = sel; 2038 2039 if (sel && sel->current) 2040 si_pm4_bind_state(rctx, ps, sel->current->pm4); 2041 else 2042 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4); 2043} 2044 2045static void si_delete_shader_selector(struct pipe_context *ctx, 2046 struct si_pipe_shader_selector *sel) 2047{ 2048 struct r600_context *rctx = (struct r600_context *)ctx; 2049 struct si_pipe_shader *p = sel->current, *c; 2050 2051 while (p) { 2052 c = p->next_variant; 2053 si_pm4_delete_state(rctx, vs, p->pm4); 2054 si_pipe_shader_destroy(ctx, p); 2055 free(p); 2056 p = c; 2057 } 2058 2059 free(sel->tokens); 2060 free(sel); 2061 } 2062 2063static void si_delete_vs_shader(struct pipe_context *ctx, void *state) 2064{ 2065 struct r600_context *rctx = (struct r600_context *)ctx; 2066 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; 2067 2068 if (rctx->vs_shader == sel) { 2069 rctx->vs_shader = NULL; 2070 } 2071 2072 si_delete_shader_selector(ctx, sel); 2073} 2074 2075static void si_delete_ps_shader(struct pipe_context *ctx, void *state) 2076{ 2077 struct r600_context *rctx = (struct r600_context *)ctx; 2078 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; 2079 2080 if (rctx->ps_shader == sel) { 2081 rctx->ps_shader = NULL; 2082 } 2083 2084 si_delete_shader_selector(ctx, sel); 2085} 2086 2087/* 2088 * Samplers 2089 */ 2090 2091static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx, 2092 struct pipe_resource *texture, 2093 const struct pipe_sampler_view *state) 2094{ 2095 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view); 2096 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; 2097 const struct util_format_description *desc; 2098 unsigned format, num_format; 2099 uint32_t pitch = 0; 2100 unsigned char state_swizzle[4], swizzle[4]; 2101 unsigned height, depth, width; 2102 enum pipe_format pipe_format = state->format; 2103 struct radeon_surface_level *surflevel; 2104 int first_non_void; 2105 uint64_t va; 2106 2107 if (view == NULL) 2108 return NULL; 2109 2110 /* initialize base object */ 2111 view->base = *state; 2112 view->base.texture = NULL; 2113 pipe_reference(NULL, &texture->reference); 2114 view->base.texture = texture; 2115 view->base.reference.count = 1; 2116 view->base.context = ctx; 2117 2118 state_swizzle[0] = state->swizzle_r; 2119 state_swizzle[1] = state->swizzle_g; 2120 state_swizzle[2] = state->swizzle_b; 2121 state_swizzle[3] = state->swizzle_a; 2122 2123 surflevel = tmp->surface.level; 2124 2125 /* Texturing with separate depth and stencil. */ 2126 if (tmp->is_depth && !tmp->is_flushing_texture) { 2127 switch (pipe_format) { 2128 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 2129 pipe_format = PIPE_FORMAT_Z32_FLOAT; 2130 break; 2131 case PIPE_FORMAT_X8Z24_UNORM: 2132 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2133 /* Z24 is always stored like this. */ 2134 pipe_format = PIPE_FORMAT_Z24X8_UNORM; 2135 break; 2136 case PIPE_FORMAT_X24S8_UINT: 2137 case PIPE_FORMAT_S8X24_UINT: 2138 case PIPE_FORMAT_X32_S8X24_UINT: 2139 pipe_format = PIPE_FORMAT_S8_UINT; 2140 surflevel = tmp->surface.stencil_level; 2141 break; 2142 default:; 2143 } 2144 } 2145 2146 desc = util_format_description(pipe_format); 2147 2148 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) { 2149 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0}; 2150 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1}; 2151 2152 switch (pipe_format) { 2153 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2154 case PIPE_FORMAT_X24S8_UINT: 2155 case PIPE_FORMAT_X32_S8X24_UINT: 2156 case PIPE_FORMAT_X8Z24_UNORM: 2157 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle); 2158 break; 2159 default: 2160 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle); 2161 } 2162 } else { 2163 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle); 2164 } 2165 2166 first_non_void = util_format_get_first_non_void_channel(pipe_format); 2167 2168 switch (pipe_format) { 2169 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 2170 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2171 break; 2172 default: 2173 if (first_non_void < 0) { 2174 if (util_format_is_compressed(pipe_format)) { 2175 switch (pipe_format) { 2176 case PIPE_FORMAT_DXT1_SRGB: 2177 case PIPE_FORMAT_DXT1_SRGBA: 2178 case PIPE_FORMAT_DXT3_SRGBA: 2179 case PIPE_FORMAT_DXT5_SRGBA: 2180 num_format = V_008F14_IMG_NUM_FORMAT_SRGB; 2181 break; 2182 case PIPE_FORMAT_RGTC1_SNORM: 2183 case PIPE_FORMAT_LATC1_SNORM: 2184 case PIPE_FORMAT_RGTC2_SNORM: 2185 case PIPE_FORMAT_LATC2_SNORM: 2186 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 2187 break; 2188 default: 2189 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2190 break; 2191 } 2192 } else { 2193 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2194 } 2195 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) { 2196 num_format = V_008F14_IMG_NUM_FORMAT_SRGB; 2197 } else { 2198 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2199 2200 switch (desc->channel[first_non_void].type) { 2201 case UTIL_FORMAT_TYPE_FLOAT: 2202 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2203 break; 2204 case UTIL_FORMAT_TYPE_SIGNED: 2205 if (desc->channel[first_non_void].normalized) 2206 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 2207 else if (desc->channel[first_non_void].pure_integer) 2208 num_format = V_008F14_IMG_NUM_FORMAT_SINT; 2209 else 2210 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED; 2211 break; 2212 case UTIL_FORMAT_TYPE_UNSIGNED: 2213 if (desc->channel[first_non_void].normalized) 2214 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2215 else if (desc->channel[first_non_void].pure_integer) 2216 num_format = V_008F14_IMG_NUM_FORMAT_UINT; 2217 else 2218 num_format = V_008F14_IMG_NUM_FORMAT_USCALED; 2219 } 2220 } 2221 } 2222 2223 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void); 2224 if (format == ~0) { 2225 format = 0; 2226 } 2227 2228 view->resource = &tmp->resource; 2229 2230 /* not supported any more */ 2231 //endian = si_colorformat_endian_swap(format); 2232 2233 width = surflevel[0].npix_x; 2234 height = surflevel[0].npix_y; 2235 depth = surflevel[0].npix_z; 2236 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format); 2237 2238 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 2239 height = 1; 2240 depth = texture->array_size; 2241 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 2242 depth = texture->array_size; 2243 } 2244 2245 va = r600_resource_va(ctx->screen, texture); 2246 va += surflevel[0].offset; 2247 view->state[0] = va >> 8; 2248 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) | 2249 S_008F14_DATA_FORMAT(format) | 2250 S_008F14_NUM_FORMAT(num_format)); 2251 view->state[2] = (S_008F18_WIDTH(width - 1) | 2252 S_008F18_HEIGHT(height - 1)); 2253 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) | 2254 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | 2255 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | 2256 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | 2257 S_008F1C_BASE_LEVEL(state->u.tex.first_level) | 2258 S_008F1C_LAST_LEVEL(state->u.tex.last_level) | 2259 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) | 2260 S_008F1C_POW2_PAD(texture->last_level > 0) | 2261 S_008F1C_TYPE(si_tex_dim(texture->target))); 2262 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1)); 2263 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) | 2264 S_008F24_LAST_ARRAY(state->u.tex.last_layer)); 2265 view->state[6] = 0; 2266 view->state[7] = 0; 2267 2268 return &view->base; 2269} 2270 2271static void si_sampler_view_destroy(struct pipe_context *ctx, 2272 struct pipe_sampler_view *state) 2273{ 2274 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; 2275 2276 pipe_resource_reference(&state->texture, NULL); 2277 FREE(resource); 2278} 2279 2280static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter) 2281{ 2282 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER || 2283 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER || 2284 (linear_filter && 2285 (wrap == PIPE_TEX_WRAP_CLAMP || 2286 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP)); 2287} 2288 2289static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state) 2290{ 2291 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST || 2292 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST; 2293 2294 return (state->border_color.ui[0] || state->border_color.ui[1] || 2295 state->border_color.ui[2] || state->border_color.ui[3]) && 2296 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) || 2297 wrap_mode_uses_border_color(state->wrap_t, linear_filter) || 2298 wrap_mode_uses_border_color(state->wrap_r, linear_filter)); 2299} 2300 2301static void *si_create_sampler_state(struct pipe_context *ctx, 2302 const struct pipe_sampler_state *state) 2303{ 2304 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state); 2305 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; 2306 unsigned border_color_type; 2307 2308 if (rstate == NULL) { 2309 return NULL; 2310 } 2311 2312 if (sampler_state_needs_border_color(state)) 2313 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER; 2314 else 2315 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; 2316 2317 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | 2318 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) | 2319 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) | 2320 (state->max_anisotropy & 0x7) << 9 | /* XXX */ 2321 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) | 2322 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) | 2323 aniso_flag_offset << 16 | /* XXX */ 2324 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map)); 2325 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | 2326 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8))); 2327 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) | 2328 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) | 2329 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) | 2330 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter))); 2331 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type); 2332 2333 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) { 2334 memcpy(rstate->border_color, state->border_color.ui, 2335 sizeof(rstate->border_color)); 2336 } 2337 2338 return rstate; 2339} 2340 2341static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx, 2342 unsigned count, 2343 struct pipe_sampler_view **views, 2344 struct r600_textures_info *samplers, 2345 unsigned user_data_reg) 2346{ 2347 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views; 2348 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2349 int i, j; 2350 2351 if (!count) 2352 goto out; 2353 2354 si_pm4_inval_texture_cache(pm4); 2355 2356 si_pm4_sh_data_begin(pm4); 2357 for (i = 0; i < count; i++) { 2358 pipe_sampler_view_reference( 2359 (struct pipe_sampler_view **)&samplers->views[i], 2360 views[i]); 2361 2362 if (views[i]) { 2363 struct r600_resource_texture *rtex = 2364 (struct r600_resource_texture*)views[i]->texture; 2365 2366 if (rtex->is_depth && !rtex->is_flushing_texture) { 2367 samplers->depth_texture_mask |= 1 << i; 2368 } else { 2369 samplers->depth_texture_mask &= ~(1 << i); 2370 } 2371 2372 si_pm4_add_bo(pm4, resource[i]->resource, RADEON_USAGE_READ); 2373 } else { 2374 samplers->depth_texture_mask &= ~(1 << i); 2375 } 2376 2377 for (j = 0; j < Elements(resource[i]->state); ++j) { 2378 si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0); 2379 } 2380 } 2381 2382 for (i = count; i < NUM_TEX_UNITS; i++) { 2383 if (samplers->views[i]) 2384 pipe_sampler_view_reference((struct pipe_sampler_view **)&samplers->views[i], NULL); 2385 } 2386 2387 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_RESOURCE); 2388 2389out: 2390 rctx->ps_samplers.n_views = count; 2391 return pm4; 2392} 2393 2394static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count, 2395 struct pipe_sampler_view **views) 2396{ 2397 struct r600_context *rctx = (struct r600_context *)ctx; 2398 struct si_pm4_state *pm4; 2399 2400 pm4 = si_set_sampler_view(rctx, count, views, &rctx->vs_samplers, 2401 R_00B130_SPI_SHADER_USER_DATA_VS_0); 2402 si_pm4_set_state(rctx, vs_sampler_views, pm4); 2403} 2404 2405static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count, 2406 struct pipe_sampler_view **views) 2407{ 2408 struct r600_context *rctx = (struct r600_context *)ctx; 2409 struct si_pm4_state *pm4; 2410 2411 pm4 = si_set_sampler_view(rctx, count, views, &rctx->ps_samplers, 2412 R_00B030_SPI_SHADER_USER_DATA_PS_0); 2413 si_pm4_set_state(rctx, ps_sampler_views, pm4); 2414} 2415 2416static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned count, 2417 void **states, 2418 struct r600_textures_info *samplers, 2419 unsigned user_data_reg) 2420{ 2421 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states; 2422 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2423 uint32_t *border_color_table = NULL; 2424 int i, j; 2425 2426 if (!count) 2427 goto out; 2428 2429 si_pm4_inval_texture_cache(pm4); 2430 2431 si_pm4_sh_data_begin(pm4); 2432 for (i = 0; i < count; i++) { 2433 if (rstates[i] && 2434 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) == 2435 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) { 2436 if (!rctx->border_color_table || 2437 ((rctx->border_color_offset + count - i) & 2438 C_008F3C_BORDER_COLOR_PTR)) { 2439 si_resource_reference(&rctx->border_color_table, NULL); 2440 rctx->border_color_offset = 0; 2441 2442 rctx->border_color_table = 2443 si_resource_create_custom(&rctx->screen->screen, 2444 PIPE_USAGE_STAGING, 2445 4096 * 4 * 4); 2446 } 2447 2448 if (!border_color_table) { 2449 border_color_table = 2450 rctx->ws->buffer_map(rctx->border_color_table->cs_buf, 2451 rctx->cs, 2452 PIPE_TRANSFER_WRITE | 2453 PIPE_TRANSFER_UNSYNCHRONIZED); 2454 } 2455 2456 for (j = 0; j < 4; j++) { 2457 border_color_table[4 * rctx->border_color_offset + j] = 2458 util_le32_to_cpu(rstates[i]->border_color[j]); 2459 } 2460 2461 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR; 2462 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++); 2463 } 2464 2465 for (j = 0; j < Elements(rstates[i]->val); ++j) { 2466 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0); 2467 } 2468 } 2469 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER); 2470 2471 if (border_color_table) { 2472 uint64_t va_offset = 2473 r600_resource_va(&rctx->screen->screen, 2474 (void*)rctx->border_color_table); 2475 2476 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8); 2477 rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf); 2478 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ); 2479 } 2480 2481 memcpy(samplers->samplers, states, sizeof(void*) * count); 2482 2483out: 2484 samplers->n_samplers = count; 2485 return pm4; 2486} 2487 2488static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states) 2489{ 2490 struct r600_context *rctx = (struct r600_context *)ctx; 2491 struct si_pm4_state *pm4; 2492 2493 pm4 = si_bind_sampler(rctx, count, states, &rctx->vs_samplers, 2494 R_00B130_SPI_SHADER_USER_DATA_VS_0); 2495 si_pm4_set_state(rctx, vs_sampler, pm4); 2496} 2497 2498static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states) 2499{ 2500 struct r600_context *rctx = (struct r600_context *)ctx; 2501 struct si_pm4_state *pm4; 2502 2503 pm4 = si_bind_sampler(rctx, count, states, &rctx->ps_samplers, 2504 R_00B030_SPI_SHADER_USER_DATA_PS_0); 2505 si_pm4_set_state(rctx, ps_sampler, pm4); 2506} 2507 2508static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 2509{ 2510} 2511 2512static void si_delete_sampler_state(struct pipe_context *ctx, void *state) 2513{ 2514 free(state); 2515} 2516 2517/* 2518 * Constants 2519 */ 2520static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 2521 struct pipe_constant_buffer *input) 2522{ 2523 struct r600_context *rctx = (struct r600_context *)ctx; 2524 struct r600_constbuf_state *state = &rctx->constbuf_state[shader]; 2525 struct pipe_constant_buffer *cb; 2526 const uint8_t *ptr; 2527 2528 /* Note that the state tracker can unbind constant buffers by 2529 * passing NULL here. 2530 */ 2531 if (unlikely(!input || (!input->buffer && !input->user_buffer))) { 2532 state->enabled_mask &= ~(1 << index); 2533 state->dirty_mask &= ~(1 << index); 2534 pipe_resource_reference(&state->cb[index].buffer, NULL); 2535 return; 2536 } 2537 2538 cb = &state->cb[index]; 2539 cb->buffer_size = input->buffer_size; 2540 2541 ptr = input->user_buffer; 2542 2543 if (ptr) { 2544 /* Upload the user buffer. */ 2545 if (R600_BIG_ENDIAN) { 2546 uint32_t *tmpPtr; 2547 unsigned i, size = input->buffer_size; 2548 2549 if (!(tmpPtr = malloc(size))) { 2550 R600_ERR("Failed to allocate BE swap buffer.\n"); 2551 return; 2552 } 2553 2554 for (i = 0; i < size / 4; ++i) { 2555 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]); 2556 } 2557 2558 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer); 2559 free(tmpPtr); 2560 } else { 2561 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer); 2562 } 2563 } else { 2564 /* Setup the hw buffer. */ 2565 cb->buffer_offset = input->buffer_offset; 2566 pipe_resource_reference(&cb->buffer, input->buffer); 2567 } 2568 2569 state->enabled_mask |= 1 << index; 2570 state->dirty_mask |= 1 << index; 2571} 2572 2573/* 2574 * Vertex elements & buffers 2575 */ 2576 2577static void *si_create_vertex_elements(struct pipe_context *ctx, 2578 unsigned count, 2579 const struct pipe_vertex_element *elements) 2580{ 2581 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element); 2582 int i; 2583 2584 assert(count < PIPE_MAX_ATTRIBS); 2585 if (!v) 2586 return NULL; 2587 2588 v->count = count; 2589 for (i = 0; i < count; ++i) { 2590 const struct util_format_description *desc; 2591 unsigned data_format, num_format; 2592 int first_non_void; 2593 2594 desc = util_format_description(elements[i].src_format); 2595 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format); 2596 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format, 2597 desc, first_non_void); 2598 2599 switch (desc->channel[first_non_void].type) { 2600 case UTIL_FORMAT_TYPE_FIXED: 2601 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */ 2602 break; 2603 case UTIL_FORMAT_TYPE_SIGNED: 2604 if (desc->channel[first_non_void].normalized) 2605 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM; 2606 else if (desc->channel[first_non_void].pure_integer) 2607 num_format = V_008F0C_BUF_NUM_FORMAT_SINT; 2608 else 2609 num_format = V_008F0C_BUF_NUM_FORMAT_SSCALED; 2610 break; 2611 case UTIL_FORMAT_TYPE_UNSIGNED: 2612 if (desc->channel[first_non_void].normalized) 2613 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM; 2614 else if (desc->channel[first_non_void].pure_integer) 2615 num_format = V_008F0C_BUF_NUM_FORMAT_UINT; 2616 else 2617 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; 2618 break; 2619 case UTIL_FORMAT_TYPE_FLOAT: 2620 default: 2621 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2622 } 2623 2624 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | 2625 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | 2626 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | 2627 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | 2628 S_008F0C_NUM_FORMAT(num_format) | 2629 S_008F0C_DATA_FORMAT(data_format); 2630 } 2631 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); 2632 2633 return v; 2634} 2635 2636static void si_bind_vertex_elements(struct pipe_context *ctx, void *state) 2637{ 2638 struct r600_context *rctx = (struct r600_context *)ctx; 2639 struct si_vertex_element *v = (struct si_vertex_element*)state; 2640 2641 rctx->vertex_elements = v; 2642} 2643 2644static void si_delete_vertex_element(struct pipe_context *ctx, void *state) 2645{ 2646 struct r600_context *rctx = (struct r600_context *)ctx; 2647 2648 if (rctx->vertex_elements == state) 2649 rctx->vertex_elements = NULL; 2650 FREE(state); 2651} 2652 2653static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count, 2654 const struct pipe_vertex_buffer *buffers) 2655{ 2656 struct r600_context *rctx = (struct r600_context *)ctx; 2657 2658 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count); 2659} 2660 2661static void si_set_index_buffer(struct pipe_context *ctx, 2662 const struct pipe_index_buffer *ib) 2663{ 2664 struct r600_context *rctx = (struct r600_context *)ctx; 2665 2666 if (ib) { 2667 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer); 2668 memcpy(&rctx->index_buffer, ib, sizeof(*ib)); 2669 } else { 2670 pipe_resource_reference(&rctx->index_buffer.buffer, NULL); 2671 } 2672} 2673 2674/* 2675 * Misc 2676 */ 2677static void si_set_polygon_stipple(struct pipe_context *ctx, 2678 const struct pipe_poly_stipple *state) 2679{ 2680} 2681 2682static void si_texture_barrier(struct pipe_context *ctx) 2683{ 2684 struct r600_context *rctx = (struct r600_context *)ctx; 2685 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2686 2687 si_pm4_inval_texture_cache(pm4); 2688 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs); 2689 si_pm4_set_state(rctx, texture_barrier, pm4); 2690} 2691 2692void si_init_state_functions(struct r600_context *rctx) 2693{ 2694 rctx->context.create_blend_state = si_create_blend_state; 2695 rctx->context.bind_blend_state = si_bind_blend_state; 2696 rctx->context.delete_blend_state = si_delete_blend_state; 2697 rctx->context.set_blend_color = si_set_blend_color; 2698 2699 rctx->context.create_rasterizer_state = si_create_rs_state; 2700 rctx->context.bind_rasterizer_state = si_bind_rs_state; 2701 rctx->context.delete_rasterizer_state = si_delete_rs_state; 2702 2703 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state; 2704 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state; 2705 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state; 2706 rctx->custom_dsa_flush_depth_stencil = si_create_db_flush_dsa(rctx, true, true); 2707 rctx->custom_dsa_flush_depth = si_create_db_flush_dsa(rctx, true, false); 2708 rctx->custom_dsa_flush_stencil = si_create_db_flush_dsa(rctx, false, true); 2709 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false); 2710 2711 rctx->context.set_clip_state = si_set_clip_state; 2712 rctx->context.set_scissor_states = si_set_scissor_states; 2713 rctx->context.set_viewport_states = si_set_viewport_states; 2714 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref; 2715 2716 rctx->context.set_framebuffer_state = si_set_framebuffer_state; 2717 2718 rctx->context.create_vs_state = si_create_vs_state; 2719 rctx->context.create_fs_state = si_create_fs_state; 2720 rctx->context.bind_vs_state = si_bind_vs_shader; 2721 rctx->context.bind_fs_state = si_bind_ps_shader; 2722 rctx->context.delete_vs_state = si_delete_vs_shader; 2723 rctx->context.delete_fs_state = si_delete_ps_shader; 2724 2725 rctx->context.create_sampler_state = si_create_sampler_state; 2726 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler; 2727 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler; 2728 rctx->context.delete_sampler_state = si_delete_sampler_state; 2729 2730 rctx->context.create_sampler_view = si_create_sampler_view; 2731 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view; 2732 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view; 2733 rctx->context.sampler_view_destroy = si_sampler_view_destroy; 2734 2735 rctx->context.set_sample_mask = si_set_sample_mask; 2736 2737 rctx->context.set_constant_buffer = si_set_constant_buffer; 2738 2739 rctx->context.create_vertex_elements_state = si_create_vertex_elements; 2740 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements; 2741 rctx->context.delete_vertex_elements_state = si_delete_vertex_element; 2742 rctx->context.set_vertex_buffers = si_set_vertex_buffers; 2743 rctx->context.set_index_buffer = si_set_index_buffer; 2744 2745 rctx->context.create_stream_output_target = si_create_so_target; 2746 rctx->context.stream_output_target_destroy = si_so_target_destroy; 2747 rctx->context.set_stream_output_targets = si_set_so_targets; 2748 2749 rctx->context.texture_barrier = si_texture_barrier; 2750 rctx->context.set_polygon_stipple = si_set_polygon_stipple; 2751 2752 rctx->context.draw_vbo = si_draw_vbo; 2753} 2754 2755void si_init_config(struct r600_context *rctx) 2756{ 2757 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2758 2759 si_cmd_context_control(pm4); 2760 2761 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0); 2762 2763 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0); 2764 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0); 2765 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0); 2766 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0); 2767 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0); 2768 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0); 2769 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0); 2770 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0); 2771 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0); 2772 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0); 2773 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0); 2774 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0); 2775 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0); 2776 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0); 2777 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); 2778 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0); 2779 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); 2780 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, 2781 S_028AA8_SWITCH_ON_EOP(1) | 2782 S_028AA8_PARTIAL_VS_WAVE_ON(1) | 2783 S_028AA8_PRIMGROUP_SIZE(63)); 2784 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000); 2785 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); 2786 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | 2787 S_008A14_CLIP_VTX_REORDER_ENA(1)); 2788 2789 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0); 2790 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210); 2791 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98); 2792 2793 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000); 2794 2795 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0); 2796 2797 switch (rctx->screen->family) { 2798 case CHIP_TAHITI: 2799 case CHIP_PITCAIRN: 2800 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a); 2801 break; 2802 case CHIP_VERDE: 2803 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a); 2804 break; 2805 case CHIP_OLAND: 2806 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082); 2807 break; 2808 case CHIP_HAINAN: 2809 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); 2810 break; 2811 default: 2812 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000); 2813 break; 2814 } 2815 2816 si_pm4_set_state(rctx, init, pm4); 2817} 2818