intel_extensions.c revision 0f0f357b77123544ecc6c3cf50ac87b68e798d43
1/* 2 * Copyright 2003 VMware, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#include "main/version.h" 27 28#include "brw_context.h" 29#include "intel_batchbuffer.h" 30 31/** 32 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer. 33 * 34 * Some combinations of hardware and kernel versions allow this feature, 35 * while others don't. Instead of trying to enumerate every case, just 36 * try and write a register and see if works. 37 */ 38static bool 39can_do_pipelined_register_writes(struct brw_context *brw) 40{ 41 /** 42 * gen >= 8 specifically allows these writes. gen <= 6 also 43 * doesn't block them. 44 */ 45 if (brw->gen != 7) 46 return true; 47 48 static int result = -1; 49 if (result != -1) 50 return result; 51 52 /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the 53 * statistics registers), and we already reset it to zero before using it. 54 */ 55 const int reg = GEN7_SO_WRITE_OFFSET(0); 56 const int expected_value = 0x1337d0d0; 57 const int offset = 100; 58 59 /* The register we picked only exists on Gen7+. */ 60 assert(brw->gen == 7); 61 62 uint32_t *data; 63 /* Set a value in a BO to a known quantity. The workaround BO already 64 * exists and doesn't contain anything important, so we may as well use it. 65 */ 66 drm_intel_bo_map(brw->workaround_bo, true); 67 data = brw->workaround_bo->virtual; 68 data[offset] = 0xffffffff; 69 drm_intel_bo_unmap(brw->workaround_bo); 70 71 /* Write the register. */ 72 BEGIN_BATCH(3); 73 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); 74 OUT_BATCH(reg); 75 OUT_BATCH(expected_value); 76 ADVANCE_BATCH(); 77 78 brw_emit_mi_flush(brw); 79 80 /* Save the register's value back to the buffer. */ 81 BEGIN_BATCH(3); 82 OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); 83 OUT_BATCH(reg); 84 OUT_RELOC(brw->workaround_bo, 85 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 86 offset * sizeof(uint32_t)); 87 ADVANCE_BATCH(); 88 89 intel_batchbuffer_flush(brw); 90 91 /* Check whether the value got written. */ 92 drm_intel_bo_map(brw->workaround_bo, false); 93 data = brw->workaround_bo->virtual; 94 bool success = data[offset] == expected_value; 95 drm_intel_bo_unmap(brw->workaround_bo); 96 97 result = success; 98 99 return success; 100} 101 102static bool 103can_write_oacontrol(struct brw_context *brw) 104{ 105 if (brw->gen < 6 || brw->gen >= 8) 106 return false; 107 108 static int result = -1; 109 if (result != -1) 110 return result; 111 112 /* Set "Select Context ID" to a particular address (which is likely not a 113 * context), but leave all counting disabled. This should be harmless. 114 */ 115 const int expected_value = 0x31337000; 116 const int offset = 110; 117 118 uint32_t *data; 119 /* Set a value in a BO to a known quantity. The workaround BO already 120 * exists and doesn't contain anything important, so we may as well use it. 121 */ 122 drm_intel_bo_map(brw->workaround_bo, true); 123 data = brw->workaround_bo->virtual; 124 data[offset] = 0xffffffff; 125 drm_intel_bo_unmap(brw->workaround_bo); 126 127 /* Write OACONTROL. */ 128 BEGIN_BATCH(3); 129 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); 130 OUT_BATCH(OACONTROL); 131 OUT_BATCH(expected_value); 132 ADVANCE_BATCH(); 133 134 brw_emit_mi_flush(brw); 135 136 /* Save the register's value back to the buffer. */ 137 BEGIN_BATCH(3); 138 OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); 139 OUT_BATCH(OACONTROL); 140 OUT_RELOC(brw->workaround_bo, 141 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 142 offset * sizeof(uint32_t)); 143 ADVANCE_BATCH(); 144 145 brw_emit_mi_flush(brw); 146 147 /* Set OACONTROL back to zero (everything off). */ 148 BEGIN_BATCH(3); 149 OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); 150 OUT_BATCH(OACONTROL); 151 OUT_BATCH(0); 152 ADVANCE_BATCH(); 153 154 intel_batchbuffer_flush(brw); 155 156 /* Check whether the value got written. */ 157 drm_intel_bo_map(brw->workaround_bo, false); 158 data = brw->workaround_bo->virtual; 159 bool success = data[offset] == expected_value; 160 drm_intel_bo_unmap(brw->workaround_bo); 161 162 result = success; 163 164 return success; 165} 166 167/** 168 * Initializes potential list of extensions if ctx == NULL, or actually enables 169 * extensions for a context. 170 */ 171void 172intelInitExtensions(struct gl_context *ctx) 173{ 174 struct brw_context *brw = brw_context(ctx); 175 176 assert(brw->gen >= 4); 177 178 ctx->Extensions.ARB_arrays_of_arrays = true; 179 ctx->Extensions.ARB_buffer_storage = true; 180 ctx->Extensions.ARB_clear_texture = true; 181 ctx->Extensions.ARB_clip_control = true; 182 ctx->Extensions.ARB_copy_image = true; 183 ctx->Extensions.ARB_depth_buffer_float = true; 184 ctx->Extensions.ARB_depth_clamp = true; 185 ctx->Extensions.ARB_depth_texture = true; 186 ctx->Extensions.ARB_draw_elements_base_vertex = true; 187 ctx->Extensions.ARB_draw_instanced = true; 188 ctx->Extensions.ARB_ES2_compatibility = true; 189 ctx->Extensions.ARB_explicit_attrib_location = true; 190 ctx->Extensions.ARB_explicit_uniform_location = true; 191 ctx->Extensions.ARB_fragment_coord_conventions = true; 192 ctx->Extensions.ARB_fragment_program = true; 193 ctx->Extensions.ARB_fragment_program_shadow = true; 194 ctx->Extensions.ARB_fragment_shader = true; 195 ctx->Extensions.ARB_framebuffer_object = true; 196 ctx->Extensions.ARB_half_float_vertex = true; 197 ctx->Extensions.ARB_instanced_arrays = true; 198 ctx->Extensions.ARB_internalformat_query = true; 199 ctx->Extensions.ARB_internalformat_query2 = true; 200 ctx->Extensions.ARB_map_buffer_range = true; 201 ctx->Extensions.ARB_occlusion_query = true; 202 ctx->Extensions.ARB_occlusion_query2 = true; 203 ctx->Extensions.ARB_pipeline_statistics_query = true; 204 ctx->Extensions.ARB_point_sprite = true; 205 ctx->Extensions.ARB_seamless_cube_map = true; 206 ctx->Extensions.ARB_shader_bit_encoding = true; 207 ctx->Extensions.ARB_shader_draw_parameters = true; 208 ctx->Extensions.ARB_shader_texture_lod = true; 209 ctx->Extensions.ARB_shadow = true; 210 ctx->Extensions.ARB_sync = true; 211 ctx->Extensions.ARB_texture_border_clamp = true; 212 ctx->Extensions.ARB_texture_compression_rgtc = true; 213 ctx->Extensions.ARB_texture_cube_map = true; 214 ctx->Extensions.ARB_texture_env_combine = true; 215 ctx->Extensions.ARB_texture_env_crossbar = true; 216 ctx->Extensions.ARB_texture_env_dot3 = true; 217 ctx->Extensions.ARB_texture_float = true; 218 ctx->Extensions.ARB_texture_mirror_clamp_to_edge = true; 219 ctx->Extensions.ARB_texture_non_power_of_two = true; 220 ctx->Extensions.ARB_texture_rg = true; 221 ctx->Extensions.ARB_texture_rgb10_a2ui = true; 222 ctx->Extensions.ARB_vertex_program = true; 223 ctx->Extensions.ARB_vertex_shader = true; 224 ctx->Extensions.ARB_vertex_type_2_10_10_10_rev = true; 225 ctx->Extensions.ARB_vertex_type_10f_11f_11f_rev = true; 226 ctx->Extensions.EXT_blend_color = true; 227 ctx->Extensions.EXT_blend_equation_separate = true; 228 ctx->Extensions.EXT_blend_func_separate = true; 229 ctx->Extensions.EXT_blend_minmax = true; 230 ctx->Extensions.EXT_draw_buffers2 = true; 231 ctx->Extensions.EXT_framebuffer_sRGB = true; 232 ctx->Extensions.EXT_gpu_program_parameters = true; 233 ctx->Extensions.EXT_packed_float = true; 234 ctx->Extensions.EXT_pixel_buffer_object = true; 235 ctx->Extensions.EXT_point_parameters = true; 236 ctx->Extensions.EXT_polygon_offset_clamp = true; 237 ctx->Extensions.EXT_provoking_vertex = true; 238 ctx->Extensions.EXT_stencil_two_side = true; 239 ctx->Extensions.EXT_texture_array = true; 240 ctx->Extensions.EXT_texture_env_dot3 = true; 241 ctx->Extensions.EXT_texture_filter_anisotropic = true; 242 ctx->Extensions.EXT_texture_integer = true; 243 ctx->Extensions.EXT_texture_shared_exponent = true; 244 ctx->Extensions.EXT_texture_snorm = true; 245 ctx->Extensions.EXT_texture_sRGB = true; 246 ctx->Extensions.EXT_texture_sRGB_decode = true; 247 ctx->Extensions.EXT_texture_swizzle = true; 248 ctx->Extensions.EXT_vertex_array_bgra = true; 249 ctx->Extensions.KHR_robustness = true; 250 ctx->Extensions.AMD_seamless_cubemap_per_texture = true; 251 ctx->Extensions.APPLE_object_purgeable = true; 252 ctx->Extensions.ATI_separate_stencil = true; 253 ctx->Extensions.ATI_texture_env_combine3 = true; 254 ctx->Extensions.MESA_pack_invert = true; 255 ctx->Extensions.NV_conditional_render = true; 256 ctx->Extensions.NV_primitive_restart = true; 257 ctx->Extensions.NV_texture_barrier = true; 258 ctx->Extensions.NV_texture_env_combine4 = true; 259 ctx->Extensions.NV_texture_rectangle = true; 260 ctx->Extensions.TDFX_texture_compression_FXT1 = true; 261 ctx->Extensions.OES_compressed_ETC1_RGB8_texture = true; 262 ctx->Extensions.OES_draw_texture = true; 263 ctx->Extensions.OES_EGL_image = true; 264 ctx->Extensions.OES_EGL_image_external = true; 265 ctx->Extensions.OES_standard_derivatives = true; 266 ctx->Extensions.OES_texture_float = true; 267 ctx->Extensions.OES_texture_float_linear = true; 268 ctx->Extensions.OES_texture_half_float = true; 269 ctx->Extensions.OES_texture_half_float_linear = true; 270 271 if (brw->gen >= 8) 272 ctx->Const.GLSLVersion = 420; 273 else if (brw->gen >= 6) 274 ctx->Const.GLSLVersion = 330; 275 else 276 ctx->Const.GLSLVersion = 120; 277 _mesa_override_glsl_version(&ctx->Const); 278 279 if (brw->gen >= 5) { 280 ctx->Extensions.ARB_texture_query_levels = ctx->Const.GLSLVersion >= 130; 281 ctx->Extensions.ARB_texture_query_lod = true; 282 ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130; 283 ctx->Extensions.EXT_timer_query = true; 284 285 if (brw->gen == 5 || can_write_oacontrol(brw)) { 286 ctx->Extensions.AMD_performance_monitor = true; 287 ctx->Extensions.INTEL_performance_query = true; 288 } 289 } 290 291 if (brw->gen >= 6) { 292 ctx->Extensions.ARB_blend_func_extended = 293 !driQueryOptionb(&brw->optionCache, "disable_blend_func_extended"); 294 ctx->Extensions.ARB_conditional_render_inverted = true; 295 ctx->Extensions.ARB_cull_distance = true; 296 ctx->Extensions.ARB_draw_buffers_blend = true; 297 ctx->Extensions.ARB_ES3_compatibility = true; 298 ctx->Extensions.ARB_fragment_layer_viewport = true; 299 ctx->Extensions.ARB_sample_shading = true; 300 ctx->Extensions.ARB_shading_language_420pack = true; 301 ctx->Extensions.ARB_shading_language_packing = true; 302 ctx->Extensions.ARB_texture_buffer_object = true; 303 ctx->Extensions.ARB_texture_buffer_object_rgb32 = true; 304 ctx->Extensions.ARB_texture_buffer_range = true; 305 ctx->Extensions.ARB_texture_cube_map_array = true; 306 ctx->Extensions.ARB_texture_gather = true; 307 ctx->Extensions.ARB_texture_multisample = true; 308 ctx->Extensions.ARB_uniform_buffer_object = true; 309 310 ctx->Extensions.AMD_vertex_shader_layer = true; 311 ctx->Extensions.EXT_framebuffer_multisample = true; 312 ctx->Extensions.EXT_framebuffer_multisample_blit_scaled = true; 313 ctx->Extensions.EXT_transform_feedback = true; 314 ctx->Extensions.OES_depth_texture_cube_map = true; 315 ctx->Extensions.OES_sample_variables = true; 316 317 ctx->Extensions.ARB_timer_query = brw->intelScreen->hw_has_timestamp; 318 319 /* Only enable this in core profile because other parts of Mesa behave 320 * slightly differently when the extension is enabled. 321 */ 322 if (ctx->API == API_OPENGL_CORE) { 323 ctx->Extensions.ARB_shader_subroutine = true; 324 ctx->Extensions.ARB_viewport_array = true; 325 ctx->Extensions.AMD_vertex_shader_viewport_index = true; 326 } 327 } 328 329 brw->predicate.supported = false; 330 brw->can_do_pipelined_register_writes = 331 can_do_pipelined_register_writes(brw); 332 333 if (brw->gen >= 7) { 334 ctx->Extensions.ARB_conservative_depth = true; 335 ctx->Extensions.ARB_derivative_control = true; 336 ctx->Extensions.ARB_framebuffer_no_attachments = true; 337 ctx->Extensions.ARB_gpu_shader5 = true; 338 ctx->Extensions.ARB_shader_atomic_counters = true; 339 ctx->Extensions.ARB_shader_clock = true; 340 ctx->Extensions.ARB_shader_image_load_store = true; 341 ctx->Extensions.ARB_shader_image_size = true; 342 ctx->Extensions.ARB_shader_texture_image_samples = true; 343 ctx->Extensions.ARB_tessellation_shader = true; 344 ctx->Extensions.ARB_texture_compression_bptc = true; 345 ctx->Extensions.ARB_texture_view = true; 346 ctx->Extensions.ARB_shader_storage_buffer_object = true; 347 ctx->Extensions.EXT_shader_samples_identical = true; 348 ctx->Extensions.OES_texture_buffer = true; 349 350 if (brw->can_do_pipelined_register_writes) { 351 ctx->Extensions.ARB_draw_indirect = true; 352 ctx->Extensions.ARB_transform_feedback2 = true; 353 ctx->Extensions.ARB_transform_feedback3 = true; 354 ctx->Extensions.ARB_transform_feedback_instanced = true; 355 356 if ((brw->gen >= 8 || brw->intelScreen->cmd_parser_version >= 5) && 357 ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) 358 ctx->Extensions.ARB_compute_shader = true; 359 360 if (brw->intelScreen->cmd_parser_version >= 2) 361 brw->predicate.supported = true; 362 } 363 364 /* Only enable this in core profile because other parts of Mesa behave 365 * slightly differently when the extension is enabled. 366 */ 367 if (ctx->API == API_OPENGL_CORE) { 368 ctx->Extensions.ARB_viewport_array = true; 369 ctx->Extensions.AMD_vertex_shader_viewport_index = true; 370 ctx->Extensions.ARB_shader_subroutine = true; 371 } 372 } 373 374 if (brw->gen >= 8 || brw->is_haswell || brw->is_baytrail) { 375 ctx->Extensions.ARB_robust_buffer_access_behavior = true; 376 } 377 378 if (brw->intelScreen->has_mi_math_and_lrr) { 379 ctx->Extensions.ARB_query_buffer_object = true; 380 } 381 382 if (brw->gen >= 8 || brw->is_baytrail) { 383 /* For now, we only enable OES_copy_image on platforms that support 384 * ETC2 natively in hardware. We would need more hacks to support it 385 * elsewhere. 386 */ 387 ctx->Extensions.OES_copy_image = true; 388 } 389 390 if (brw->gen >= 8) { 391 ctx->Extensions.ARB_shader_precision = true; 392 ctx->Extensions.ARB_stencil_texturing = true; 393 ctx->Extensions.ARB_texture_stencil8 = true; 394 ctx->Extensions.ARB_gpu_shader_fp64 = true; 395 ctx->Extensions.ARB_vertex_attrib_64bit = true; 396 } 397 398 if (brw->gen >= 9) { 399 ctx->Extensions.KHR_texture_compression_astc_ldr = true; 400 ctx->Extensions.ARB_shader_stencil_export = true; 401 } 402 403 if (ctx->API == API_OPENGL_CORE) 404 ctx->Extensions.ARB_base_instance = true; 405 if (ctx->API != API_OPENGL_CORE) 406 ctx->Extensions.ARB_color_buffer_float = true; 407 408 if (ctx->Mesa_DXTn || driQueryOptionb(&brw->optionCache, "force_s3tc_enable")) 409 ctx->Extensions.EXT_texture_compression_s3tc = true; 410 411 ctx->Extensions.ANGLE_texture_compression_dxt = true; 412} 413