History log of /external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
d2590eb65ff28a9cbd592353d15d7e6cbd2c6fc6 14-Jan-2017 Kenneth Graunke <kenneth@whitecape.org> i965: Enable OpenGL 4.5 on Haswell.

Everything is in place and the test results look solid.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
75968a668e44b3fd7c9b9277937c005366fca116 11-Oct-2016 Juan A. Suarez Romero <jasuarez@igalia.com> i965/gen7: expose OpenGL 4.2 on Haswell when supported

GL_ARB_vertex_attrib_64bit was the last piece missing.

v2: update docs (Jordan)

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
77077986eb281f7537b77b91445778b7d75a81d7 17-Oct-2016 Samuel Iglesias Gonsálvez <siglesias@igalia.com> i965: enable ARB_shader_precision to HSW+

v2: update docs (Jordan)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
1d1ddbaa562fb3a60c4c612e1b6a8d0e2e402d0a 17-Oct-2016 Samuel Iglesias Gonsálvez <siglesias@igalia.com> i965: unify the code to enable of ARB_gpu_shader_fp64 and ARB_vertex_attrib_64bit for HSW+

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
485955be9c59ce56af9de41eaf9898526ee24be8 07-Jul-2016 Alejandro Piñeiro <apinheiro@igalia.com> i965: Enable ARB_vertex_attrib_64bit for Haswell

v2: update docs (Jordan)

Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
1472ff35914fb50c8b49a4f8678c76327e7da75c 08-Nov-2016 Ian Romanick <ian.d.romanick@intel.com> i965: Enable several GLES 3.1 extensions on HSW+

The only reason we didn't previously enable this was the dependency on
OpenGL ES 3.1. These should have been enabled as soon as HSW got
stencil texturing. We also needed to fixup setting MaxViewports.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
a98f2e53e1c669dee3114badcce261e564748af4 04-Jan-2017 Iago Toral Quiroga <itoral@igalia.com> i965: add a kernel_features bitfield to intel screen

We can use this to track various features that may or may not be supported
by the hw / kernel. Currently, we usually do this by checking the generation
and supported command parser versions in various places thoughtout the driver
code. With this patch, we centralize all these checks in just once place at
screen creation time, then we just query the bitfield wherever we need to
check if a particular feature is supported.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
e3123c8ca22e9a9337af6179dfd8383259f3ccc6 03-Jan-2017 Iago Toral Quiroga <itoral@igalia.com> i965/gen7: Enable OpenGL 4.0 in Haswell when supported

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
1f1b8def48f5e4015d15e6cde42b1b7705459f17 04-Jan-2017 Iago Toral Quiroga <itoral@igalia.com> i965: get rid of brw->can_do_pipelined_register_writes

Instead, check the screen field directly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
02a44484f01848775642661c4dd38dfd56f6c345 04-Jan-2017 Chris Wilson <chris@chris-wilson.co.uk> i965: Move the pipelined test for SO register access to the screen

Moving the test to the screen places it alongside the other global HW
feature tests that want to be shared between contexts.

Also, we need to know if we support pipelined register writes at
screen creation time so that we can tell if we can expose OpenGL 4.0
in gen7.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
96c9ec9c274d54c5acf0d705e59188fc70b83bec 22-Apr-2015 Robert Bragg <robert@sixbynine.org> i965: Remove perf monitor/query backend

In its current state the unified i965 backend for
AMD_performance_monitor and INTEL_performance_query isn't able to report
meaningful Observation Architecture metrics since we haven't so far had
the necessary kernel support to fully configure the OA unit, nor the
corresponding support for normalizing the counters into a form that can
be usefully interpreted by application developers (as opposed to raw
values that may, for example, scale by the number of EUs there are).

So that we can focus on implementing just one of these extensions fully
and since we anticipate some significant backend changes as we look to
use a new kernel interface to configure the OA unit, this patch removes
the current backend. This will simplify our ability to update the
frontend infrastructure and backend interface before updating our
support for performance counters.

Signed-off-by: Robert Bragg <robert@sixbynine.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
1a83e9892dd4b3a1895ede1b2d3d5fac01d56dc3 23-Jun-2016 Iago Toral Quiroga <itoral@igalia.com> i965/vec4: enable ARB_gpu_shader_fp64 for Haswell

Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
e9f17e9fb06a4389588f47be8c766b07e8d8b89f 25-Nov-2016 Lionel Landwerlin <lionel.g.landwerlin@intel.com> i965: enable INTEL_conservative_rasterization on Gen9+

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
0ff74a8990d9fe37365beb35ed8abacfbf3ed567 06-Dec-2016 Plamena Manolova <plamena.manolova@intel.com> i965: Add i965 plumbing for ARB_post_depth_coverage for i965 (gen9+).

This extension allows the fragment shader to control whether values in
gl_SampleMaskIn[] reflect the coverage after application of the early
depth and stencil tests.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
75128d6ffda9745161cb5c7ddd499422ad544d2c 15-Oct-2016 Kenneth Graunke <kenneth@whitecape.org> i965: Enable OpenGL 4.5.

Everything is in place. There are still conformance issues to sort out,
but we may as well turn it on in master.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4246986dec11f292520fbfec1ff842b90231337e 01-Sep-2016 Ian Romanick <ian.d.romanick@intel.com> i965: Sort some extension names

Trivial.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
40dd45d0c6aa4a9d727c09225967e9c3b1f45854 30-Jun-2016 Ian Romanick <ian.d.romanick@intel.com> i965: Enable ARB_shader_atomic_counter_ops

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
cd69d3f929692c60ebed8fafdf65863d68e03052 27-Sep-2016 Anuj Phogat <anuj.phogat@gmail.com> i965/gen8+: Enable GL_OES_viewport_array

This patch causes 2 regressions in khronos' gles cts tests
on various intel platforms.
Failing tests:
ES3-CTS.functional.state_query.integers.viewport_getinteger
ES3-CTS.functional.state_query.integers.viewport_getfloat

Here is an explanation of what's causing the failures:

CTS tests are not clamping the x, y location of the viewport's
bottom-left corner as recommended by ARB_viewport_array and
OES_viewport_array:
"The location of the viewport's bottom-left corner, given by (x,y), are
clamped to be within the implementation-dependent viewport bounds range.
The viewport bounds range [min, max] tuple may be determined by
calling GetFloatv with the symbolic constant VIEWPORT_BOUNDS_RANGE_OES"

Khronos CTS merge request to fix the test case:
https://gitlab.khronos.org/opengl/cts/merge_requests/399

V2: Initialize the relevant variables for GL_OES_viewport_array on gen8+

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
9694b23f66f4c41407289fb7d3ff25321042ef49 01-Dec-2015 Kenneth Graunke <kenneth@whitecape.org> i965: Rename intelScreen to screen.

"intelScreen" is wordy and also doesn't fit our style guidelines.
"screen" is shorter, which is nice, because we use it fairly often.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
d4bf9baa43e2cf7b4b877141ee472779ced219bf 20-Sep-2016 Dylan Baker <dylan@pnwbakers.com> mesa: Implement ARB_shader_viewport_layer_array for i965

This extension is a combination of AMD_vertex_shader_viewport_index and
AMD_vertex_shader_layer, making it rather trivial to implement.

For gallium I *think* this needs a new cap because of the addition of
support in tessellation evaluation shaders, and since I don't have any
hardware to test it on, I've left that for someone else to wire up.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
9fec15a7e047eda52beb0cc71d7605656d91f685 29-Aug-2016 Ilia Mirkin <imirkin@alum.mit.edu> i965: enable ARB_ES3_2_compatibility on gen8+

Note that ASTC support is not actually mandated for this extension to be
exposed.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
8c9dddadad31028d5389e227b386d6814e2c897a 14-Sep-2016 Kenneth Graunke <kenneth@whitecape.org> i965: Enable ANDROID_extension_pack_es31a on Gen9+.

AEP requires ASTC, which is currently only enabled on Skylake and later.
(It may be possible to extend this to Cherryview/Braswell in the future,
but earlier hardware doesn't have ASTC support.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
a0b1260fe0577e504c8ef31c07e13025324af8f8 28-Aug-2016 Ilia Mirkin <imirkin@alum.mit.edu> i965: enable OES_primitive_bounding_box with the no-op implementation

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
5e76baa2ad261c72f96a3df42ace4773a1c7daa9 27-Aug-2016 Jordan Justen <jordan.l.justen@intel.com> i965/hsw: Enable ARB_ES3_1_compatibility extension

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4ec1c2bb7f4ed4238ce80e25f93dd1120201aaec 27-Aug-2016 Ilia Mirkin <imirkin@alum.mit.edu> mesa: remove OES_shader_io_blocks enable

This extension should just be available whenever ES 3.1 is available.
With the new extension verification infrastructure, it will only be
enable-able on a #version 310 es shader, rendering the original reason
for having a separate enable moot.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
b387bc90c8f5f14cec4f909ce0d53455bc34ed1c 17-Aug-2016 Ian Romanick <ian.d.romanick@intel.com> i965: Enable OES_texture_cube_map_array on Gen8+

These are the only platforms that current expose OES_geometry_shader.
Once OpenGL ES 3.1 and OES_geometry_shader are enabled on Gen7, this
extension can be enabled there as well.

Gen6 will never get OpenGL ES 3.1, so it will never get this
extension... even though it has the desktop OpenGL extension. Alas.

NOTE: This causes a failure on Gen8+ platforms in
ES3-CTS.gtf.GL3Tests.texture_storage.texture_storage_texture_targets.
The test only fails because it doesn't know that 0x9009 is a valid
value when the extension exists.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
63af53dcd31cea89e5c8905e2a4898a5cb3d9ed4 23-May-2016 Ian Romanick <ian.d.romanick@intel.com> i965: Enable GL_OES_geometry_shader on Gen8+

Gen7 can get this extension (and GL_OES_shader_io_blocks) as soon as the
rest of OpenGL ES 3.1 is enabled.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
116b6e12d4d6f08d1c86475f5a2655d074804d6f 15-Jun-2016 Jordan Justen <jordan.l.justen@intel.com> i965: Enable ARB_texture_stencil8 for Haswell

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
f20f616324a79b8be91b84b6d965a0bc0096789c 08-Jun-2016 Jordan Justen <jordan.l.justen@intel.com> i965: Enable ARB_stencil_texturing for Haswell

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
219a451497d1138c12f927139c6e8aa94a116e53 30-Jun-2016 Kenneth Graunke <kenneth@whitecape.org> i965: Implement GL_KHR_blend_equation_advanced_coherent on Gen9+.

We always use a coherent read, and ignore the "opt out" enable flag.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
c2b10cabed6468b998a9c4d0ada7953d93311029 28-Jun-2016 Kenneth Graunke <kenneth@whitecape.org> i965: Enable GL_KHR_blend_equation_advanced on G45 and later.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
da85b5a9f1b22a8f6cae1a3b335dc5f31011bcb1 23-Jul-2016 Francisco Jerez <currojerez@riseup.net> i965: Expose shader framebuffer fetch extensions on Gen9+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
8a2f19a7772c80fcac85d6bdfa8e588d6cea1beb 20-Jul-2016 Francisco Jerez <currojerez@riseup.net> i965: Flip the non-coherent framebuffer fetch extension bit on G45-Gen8 hardware.

This is not enabled on the original Gen4 part because it lacks surface
state tile offsets so it may not be possible to sample from arbitrary
non-zero layers of the framebuffer depending on the miptree layout (it
should be possible to work around this by allocating a scratch surface
and doing the same hack currently used for render targets, but meh...).

On Gen9+ even though it should mostly work (feel free to force-enable
it in order to compare the coherent and non-coherent paths in terms of
performance), there are some corner cases like 1D array layered
framebuffers that cannot be handled easily by the non-coherent path
because of the incompatible layout in memory of 1D and 2D miptrees (it
should be possible to work around this too by doing state-dependent
recompiles, but it's hard to care enough since Gen9 has native support
for coherent render target reads...)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
949a89202621eb73e9f9d4c7b452d9bf9afbfd40 09-Aug-2016 Jason Ekstrand <jason.ekstrand@intel.com> i965: Roll intel_reg.h into brw_defines.h

More than half of the stuff in intel_reg.h had nothing whatsoever to do
with registers and really belongs in brw_defines.h anyway.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
b463b1d7cce2e9848b5937d1431c74f27e26edb3 21-Jul-2016 Timothy Arceri <timothy.arceri@collabora.com> i965: enable GL4.4 for Gen8+

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4ba9bd138a48bd61cbc24d546afef0986f2fd05a 20-May-2016 Timothy Arceri <timothy.arceri@collabora.com> i965: enable ARB_enhanced_layouts for gen6+

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
d99a040bbf2c385c0ad096ec140aa62f805a68b2 20-May-2016 Timothy Arceri <timothy.arceri@collabora.com> i965: enable ARB_enhanced_layouts for gen8+

Acked-by: Edward O'Callaghan <funfunctor@folklore1984.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
7cb49b1bd7f15d53e08d3716e9a835c42dc11c09 24-Jun-2016 Ian Romanick <ian.d.romanick@intel.com> i965: Enable MESA_shader_integer_functions on all GLSL 1.30 platforms

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
26c7f04d4a55b694623a389a564c9516d91c0026 21-Jun-2016 Ian Romanick <ian.d.romanick@intel.com> i965: Always enable GL_ARB_shading_language_packing

With the existing lowering passes, the functions from this extension
become a bunch of bit twiddling operations that have always been
supported.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4b2b6d4d4d62985679f164eef7d02a552e221941 21-Jun-2016 Ian Romanick <ian.d.romanick@intel.com> i965: Move enable of EXT_shader_integer_mix

This extension does not depend on the Gen. It only depends on the
availability of GLSL 1.30.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
ac0eb36d8e82abc5590773d045c6b63d9be6949a 08-Jul-2016 Anuj Phogat <anuj.phogat@gmail.com> i965/gen9: Enable KHR_texture_compression_astc_sliced_3d

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
895f7ddfb5c1c24d3f8269e73fc09458eddc4fdd 16-May-2016 Ian Romanick <ian.d.romanick@intel.com> i965: Delete redundant extension enables

A nearly identical block already exists in the gen >= 6 block above.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
32b1c0b694bf660d48054a6e859deaa8f9556efe 13-May-2016 Kenneth Graunke <kenneth@whitecape.org> i965: Enable GL_ARB_ES3_1_compatibility on Gen8+ if CS are available.

There are almost no tests in any test suite, but what little I've found
seems to work. Ilia believes everything is in place.

v2: Predicate the enable on ES 3.1 being available (Gen8+) and also
ARB_compute_shader being available (requested by Ilia).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
d8cf982f7d12190012b8917a4f4ad3a01a7f0102 20-May-2016 Francisco Jerez <currojerez@riseup.net> i965: Expose GL 4.3 on Gen8+.

ARB_compute_shader was the last feature missing.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
b7af108d3edd156836824dbad23f97d6acf75dc9 11-May-2016 Ian Romanick <ian.d.romanick@intel.com> i965: Enable GL_OES_shader_io_blocks

Only one dEQP io_blocks test fails. This test fails for the same reason
as the match_different_member_struct_names test in a previous commit.

dEQP-GLES31.functional.separate_shader.validation.io_blocks.match_different_member_struct_names

v2: Add to release notes.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
0f0f357b77123544ecc6c3cf50ac87b68e798d43 20-May-2016 Kenneth Graunke <kenneth@whitecape.org> i965: Enable OES_copy_image (and EXT) on Gen8+ and Baytrail.

For now, only enable it on platforms that actually support ETC2.

At this point, Broadwell is only failing 5 (out of 8358) dEQP tests:
dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.
srgb8_alpha8_r11f_g11f_b10f.renderbuffer_to_texture3d
srgb8_alpha8_rgb10_a2ui.renderbuffer_to_cubemap
srgb8_alpha8_rgb10_a2ui.renderbuffer_to_renderbuffer
srgb8_alpha8_rgb10_a2.renderbuffer_to_texture2d
srgb8_alpha8_rgb9_e5.renderbuffer_to_texture3d

These fail with all methods (meta, blorp, blitter, memcpy).

All are blacklisted from the Android mustpass list, which makes me
wonder whether there's an issue with the tests. The formats in
question work with other targets, and the targets in question work
with other formats...

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
85008db1d51f923113832394d7f8d6b1868be882 24-May-2016 Kristian Høgsberg Kristensen <krh@bitplanet.net> i965: Enable GL_KHR_robustness

GL_KHR_robustness adds the GL_CONTEXT_LOST error and five new entry
points that we already implement. This patch adds a new dispatch table
that returns GL_CONTEXT_LOST from all entry points and implements the
GL_LOSE_CONTEXT_ON_RESET strategy by setting that table when we learn
that we've lost the context.

With the GL_CONTEXT_LOST reporting in place and dispatch for the new
entry points we can turn on GL_KHR_robustness.

Signed-off-by: Kristian Høgsberg Kristensen <krh@bitplanet.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
5878254545f2b0207f47e581789e88fc0ab5c531 24-May-2016 Ilia Mirkin <imirkin@alum.mit.edu> mesa: remove separate enable for KHR_robust_buffer_access_behavior

This extension appears to be a strict subset of the ARB version. Also
remove it from GL3.txt since it doesn't seem relevant.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
75d10dff0bda6de2a31e26eb8e950adc5fd3994e 17-May-2016 Jason Ekstrand <jason.ekstrand@intel.com> i965: Enable ARB/KHR_robust_buffer_access_behavior on BYT and HSW+

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
a88c5d7e556f6f0c1dfcb253b38c66241cc67f72 16-May-2016 Dave Airlie <airlied@redhat.com> i965: reenable ARB_cull_distance.

Now the lowering pass is fixed we can reenable culling.

Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
9a1936d965e92c4b4aa682f96ef63362159f4fce 04-Apr-2016 Kenneth Graunke <kenneth@whitecape.org> i965: Enable ES 3.2 sample shading extensions.

This enables:
- GL_OES_sample_shading
- GL_OES_sample_variables
- GL_OES_shader_multisample_interpolation

On Gen8, we pass all the CTS tests, and all but 4 of the dEQP-GLES31
tests (dealing with 1x/2x MSAA at half rate sampling). We believe
those 4 dEQP-GLES31 tests are incorrect.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
e5e412cd272989fa801a027ab5dce7de48eb79c6 26-Apr-2016 Alejandro Piñeiro <apinheiro@igalia.com> i965: Expose OpenGL 4.2 for gen8+

ARB_vertex_attrib_64bit was the only feature missing.

v2: we can expose 4.2 instead of 4.1 (Ian Romanick)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
59b5441fd9dc9b99341381153cd1cc8510fa8e8a 12-Mar-2016 Alejandro Piñeiro <apinheiro@igalia.com> i965: Enable ARB_vertex_attrib_64bit for gen8+

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
aae0865dc0134bdfb4a4fe05b2bcdbee9fc0a0ff 17-May-2016 Kenneth Graunke <kenneth@whitecape.org> i965: Enable ARB_shader_precision on Gen8+.

I recently fixed a bug in the Piglit tests:
https://lists.freedesktop.org/archives/piglit/2016-May/019802.html

With that patch in place, we pass all the tests. So, turn it on.

We could probably expose this earlier than Gen8, but the extension
says that OpenGL 4.0 is required, and all of our tests are written
against GLSL 4.00 (which is only supported on Gen8+).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
71465179fc45820dabf933146fb16f044a7363d7 23-Feb-2016 Iago Toral Quiroga <itoral@igalia.com> i965: Expose OpenGL 4.0 for gen8+

ARB_gpu_shader_fp64 was the only feature missing.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
309d285c6b1fb7f9e19b687f182608f15d466476 23-Feb-2016 Iago Toral Quiroga <itoral@igalia.com> i965: Enable ARB_gpu_shader_fp64 for gen8+

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
9f8867d8779c7f402b9614ec334924aafc58cd64 14-May-2016 Dave Airlie <airlied@redhat.com> i965: disable cull distance temporarily.

I'll fix this up on Monday, so leave the docs changes in place.

Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
c564348a2ec601b28ae607ca0f77054ea53f6912 13-May-2016 Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com> i965: Add support for GL_ARB_cull_distance

Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4c71c8a74ad29bd84ca16803672ad1e9e30e2fff 05-May-2016 Kenneth Graunke <kenneth@whitecape.org> i965: Only enable ARB_query_buffer_object for newer kernels on Haswell.

On Haswell, we need version 6 of the kernel command parser in order to
write the math registers. Our implementation of ARB_query_buffer_object
heavily relies on MI_MATH, so we should only advertise it when MI_MATH
is available. We also need MI_LOAD_REGISTER_REG, which requires version
7 of the command parser.

To make these checks easier, introduce a screen->has_mi_math_and_lrr
flag that will be set when both commands are supported.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
f00c399bae7376bad2257d085fe754adfaa11cc8 19-Apr-2016 Jordan Justen <jordan.l.justen@intel.com> i965: Implement ARB_query_buffer_object for HSW+

v2:
* Declare loop index variable at loop site (idr)
* Make arrays of MI_MATH instructions 'static const' (idr)
* Remove commented debug code (idr)
* Updated comment in set_query_availability (Ken)
* Replace switch with if/else in hsw_result_to_gpr0 (Ken)
* Only divide GL_FRAGMENT_SHADER_INVOCATIONS_ARB by 4 on
hsw and gen8 (Ken)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
fd9a7d8f30e8a4f73c7973a9d4e59082ecb5c1bf 03-Mar-2016 Kenneth Graunke <kenneth@whitecape.org> i965: Enable ARB_texture_stencil8 and OES_texture_stencil8 on Gen8+.

Stencil texturing is required by ES 3.1. Apparently we never actually
turned it on. Do that now. Also turn on the desktop extension.

Fixes nine dEQP-GLES31.functional tests:

stencil_texturing.format.stencil_index8_2d
texture.border_clamp.formats.stencil_index8.nearest_size_pot
texture.border_clamp.formats.stencil_index8.nearest_size_npot
texture.border_clamp.formats.stencil_index8.gather_size_pot
texture.border_clamp.formats.stencil_index8.gather_size_npot
texture.border_clamp.unused_channels.stencil_index8
state_query.internal_format.renderbuffer.stencil_index8_samples
state_query.internal_format.texture_2d_multisample.stencil_index8_samples
state_query.internal_format.texture_2d_multisample_array.stencil_index8_samples

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
86cd9a134f8d6db5c65268f4ca89a919be17689b 13-Apr-2016 Nanley Chery <nanley.g.chery@intel.com> i965: Disable KHR_texture_compression_astc_hdr on Gen9

Although Gen9 samples from most HDR ASTC surfaces of correctly,
there currently are no software workarounds to fix the incorrect
sampling that occurs in others of certain color endpoint modes.

With this change, we are no longer failing the 14 tests from:
dEQP-GLES3.functional.texture.compressed.astc.endpoint_value_hdr_cem_15.*

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
875543e270de67e99ce049ca01b6cde8ac6911e1 30-Mar-2016 Ilia Mirkin <imirkin@alum.mit.edu> i965: enable OES_texture_buffer on gen7+

It will only end up getting exposed on gen8+ since it requires GL ES
3.1, but it should be ready to go on gen7 when support for GL ES 3.1 is
completed there.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Tested-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4f028bfcc048d7cbd7a7239e9f61b4d7b708aebb 21-Oct-2015 Antia Puentes <apuentes@igalia.com> i965: Enable the ARB_internalformat_query2 extension

Reviewed-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
9f36070c2fe248058f31559119a6bf6b68a7144e 10-Feb-2016 Jordan Justen <jordan.l.justen@intel.com> i965/gen7: Require kernel cmd_parser 5 for ARB_compute_shader

The indirect dispatch registers were whitelisted in command parser
version 5. (Version 5 is available as of Linux 4.4)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
bd21b54607615605b6335282029687bb0885f4ad 05-Jan-2016 Kenneth Graunke <kenneth@whitecape.org> i965: Only turn on ARB_compute_shader if we can write registers.

Compute shaders require reconfiguring the L3 for shared local memory
support. We have to be able to write the L3 registers to do that.

This effectively turns off compute shaders prior to Kernel 4.2.

(Previously, the extension enable was in an API_OPENGL_CORE conditional.
However, that isn't necessary - core Mesa extension handling already
restricts it properly. I've moved it out in this patch.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
cddfc2cefa93b884c40329dcb193fe4fb22143ab 10-Dec-2015 Kristian Høgsberg Kristensen <krh@bitplanet.net> i965: Add support for gl_DrawIDARB and enable extension

We have to break open a new vec4 for gl_DrawIDARB. We've used up all
space in the vec4 we use for SGVS and gl_DrawIDARB has to come from its
own separate vertex buffer anyway. This is because we point the vb for
base vertex and base instance into the draw parameter BO for indirect
draw calls, but the draw id is generated by mesa in a different buffer.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
381a89cf2a0c1e7babb0f134a3b5b662045092a2 26-Nov-2015 Kenneth Graunke <kenneth@whitecape.org> i965: Enable ARB_tessellation_shader on Gen7-7.5.

We've resolved all the GPU hangs, and everything seems to be working.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
7738f3a988bfa27a7c48c364cfa2d51c0b57e5d9 27-Jul-2015 Kenneth Graunke <kenneth@whitecape.org> i965: Enable ARB_tessellation_shader on Gen8+.

Everything is in place and I'm not aware of any further issues.

Tested with:
- Piglit
- Tessmark
- Unigine Heaven
- Shadow of Mordor
- GRID Autosport

I have patches to backport this to Haswell, Ivybridge, and Baytrail as
well (the first Intel hardware to support tessellation), but there are
still a lot of GPU hangs left to debug. So that will come later.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
d04612b60d98ff785646affaffc3d7243deecb74 03-Sep-2015 Jordan Justen <jordan.l.justen@intel.com> i965: Enable ARB_compute_shader extension on supported hardware

Enable ARB_compute_shader on gen7+, on hardware that supports the
OpenGL 4.3 requirements of a local group size of 1024.

With SIMD16 support, this is limited to Ivy Bridge and Haswell.

Broadwell will work with a local group size up to 896 on SIMD16
meaning programs that use this size or lower should run when setting
MESA_EXTENSION_OVERRIDE=GL_ARB_compute_shader.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4841cab01a2a6d308c00b4039f1fb1a29e44ed74 03-Sep-2015 Francisco Jerez <currojerez@riseup.net> i965: Keep track of whether LRI is allowed in the context struct.

This stores the result of can_do_pipelined_register_writes() in the
context struct so we can find out later whether LRI can be used to
program the L3 configuration.

v2:
* Split change of gen check in can_do_pipelined_register_writes (jljusten)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
50c2713726f007b988502ed5e7073fae11409853 03-Sep-2015 Francisco Jerez <currojerez@riseup.net> i965: Adjust gen check in can_do_pipelined_register_writes

Allow for pipelined register writes for gen < 7.

v2:
* Split from another patch and adjust comment (jljusten)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
f36993b46962eab4446bc1964eb47149751aee26 23-Nov-2015 Matt Turner <mattst88@gmail.com> i965: Clean up #includes in the compiler.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
99840eb983f74cd447546f7205c8c9f505ef82c8 18-Nov-2015 Ian Romanick <ian.d.romanick@intel.com> i965: Enable EXT_shader_samples_identical

On the vec4 backend, textureSamplesIdentical() will always return
false. There are currently no test cases for the vec4 backend, so we
don't have much confidence in any implementation. We also don't think
anyone is likely to miss it.

v2: Handle immediate value for MCS smarter. Rebase on changes to
nir_texop_sampels_identical (missing second parameter). Suggested by
Jason.

v3: Add Neil's code to handle 16x MSAA in the FS. Also rebase on top of
f9a9ba5e. Stub out the vec4 implementation.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v2]
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
5b75dbd7be09fdc80eff8141ef47c63a6a913c98 16-Oct-2015 Timothy Arceri <t_arceri@yahoo.com.au> i965: enable ARB_arrays_of_arrays

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
60418a28ea11b3e1d9365acfc168a8f8f5b41965 30-Oct-2015 Emil Velikov <emil.l.velikov@gmail.com> i965: enable ARB_shader_clock on gen7+

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
8c902a580a490181e7cde29073b11181db4614f8 17-Jun-2015 Kenneth Graunke <kenneth@whitecape.org> i965: Implement ARB_fragment_layer_viewport.

Normally, we could read gl_Layer from bits 26:16 of R0.0. However, the
specification requires that bogus out-of-range 32-bit values written by
previous stages need to appear in the fragment shader as-written.

Instead, we pass in the full 32-bit value from the VUE header as an
extra flat-shaded varying. We have the SF override the value to 0
when the previous stage didn't actually write a value (it's actually
defined to return 0).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
8eefdacb3892da662f85377f4fe1a33dbff2ce7a 20-Oct-2015 Ben Widawsky <benjamin.widawsky@intel.com> i965: Advertise ARB_shader_stencil_export (gen9+)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
dbae576f7f25fef72ca0b9f6f4822e0fddf7d607 19-Jun-2015 Ilia Mirkin <imirkin@alum.mit.edu> i965: add EXT_polygon_offset_clamp support to gen4/gen5

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
614b5307fd485a62205b0ceb05657dd862c1f036 18-Mar-2015 Samuel Iglesias Gonsalvez <siglesias@igalia.com> i965: Enable ARB_shader_storage_buffer_object extension for gen7+

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
71e187430cdd1d82972554d7f9e994a41847bea1 13-Aug-2015 Ilia Mirkin <imirkin@alum.mit.edu> i965: add ARB_texture_barrier support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
bfc5ace5bda6510d4dd3893a3b8c677a1c85e23e 12-Aug-2015 Ilia Mirkin <imirkin@alum.mit.edu> i965: enable ARB_shader_texture_image_samples

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
284dcad20a9a55278c1d3dd98f53e45650b22896 20-Aug-2015 Ian Romanick <ian.d.romanick@intel.com> i965: Fix typos in license

grep -lr 'sub license' | while read f; do \
sed --in-place -e 's/sub license/sublicense/' $f ;\
done

grep -lr 'NON-INFRINGEMENT' | while read f; do \
sed --in-place -e 's/NON-INFRINGEMENT/NONINFRINGEMENT/' $f ;\
done

As noted by Matt, both of these changes match the MIT license text found
at http://opensource.org/licenses/MIT.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
aa1a5c0c9e0de71ecd15e7190c121d6dd98471a6 20-Aug-2015 Ian Romanick <ian.d.romanick@intel.com> i965: Remove horizontal bars from file header comments

Why was that ever a thing?

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
f3a483069a6f0d38c10cec88417ae2b5b5aa3392 19-May-2015 Nanley Chery <nanley.g.chery@intel.com> i965: advertise ASTC support for Skylake

v2: remove OES ASTC extension reference.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
e5851cff45169f4e635299da4ed5b41aeb0d2f83 28-Apr-2015 Martin Peres <martin.peres@linux.intel.com> i965: enable GL_ARB_shader_image_size

Signed-off-by: Martin Peres <martin.peres@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
d03c65793a5ee31f1138cbd0fba6fac6cd942428 07-May-2015 Francisco Jerez <currojerez@riseup.net> i965: Expose ARB_shader_image_load_store.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
80511d176a49e754a18ce585bab413db7af63bf7 21-Jul-2015 Dave Airlie <airlied@redhat.com> i965: add support for ARB_shader_subroutine

This just adds some missing pieces to nir/i965,
it is lightly tested on my Haswell.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
f1d08c4f75794add30d1714a4cd9ce2bf335148d 01-May-2015 Chris Wilson <chris@chris-wilson.co.uk> i965: Move pipecontrol workaround bo to brw_pipe_control

With the exception of gen8, the sole user of the workaround bo are for
emitting pipe controls. Move it out of the purview of the batchbuffer
and into the pipecontrol.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
c8d3ebaffc0d7d915c1c19d54dba61fd1e57b338 29-Apr-2015 Chris Wilson <chris@chris-wilson.co.uk> i965: Query whether we have kernel support for the TIMESTAMP register once

Move the query for the TIMESTAMP register from context init to the
screen, so that it is only queried once for all contexts.

On 32bit systems, some old kernels trigger a hw bug resulting in the
TIMESTAMP register being shifted and the low 32bits always zero. Detect
this by repeating the read a few times and check the register is
incrementing every 80ns as expected and not stuck on zero (as would be
the case with the buggy kernel/hw.).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4b35ab9bdb4e663f41ff5c9ae5bbcc650b6093f9 30-Apr-2015 Chris Wilson <chris@chris-wilson.co.uk> i965: Rename intel_emit* to reflect their new location in brw_pipe_control

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
83199998310591b9162ab12e922ed79ee235b5c8 17-Jun-2015 Kevin Rogovin <kevin.rogovin@intel.com> i965: enable ARB_framebuffer_no_attachments for Gen7+

Enable GL_ARB_framebuffer_no_attachments in i965 for Gen7 and higher.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4bc00b1a4b34abc3e6e26f126686608ccfa33f52 18-May-2015 Ian Romanick <ian.d.romanick@intel.com> Revert "i965: Enable ARB_direct_state_access"

This reverts commit a57feba0a35de35728269aeb26b039e4f2393d69.

Acked-by: Fredrik Höglund <fredrik@kde.org>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
a57feba0a35de35728269aeb26b039e4f2393d69 10-May-2015 Fredrik Höglund <fredrik@kde.org> i965: Enable ARB_direct_state_access

Signed-off-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
426023050d1d3cd1b5fc0b3508dd7e1ee3b061e7 04-Nov-2014 Neil Roberts <neil@linux.intel.com> i965: Use predicate enable bit for conditional rendering w/o stalling

Previously whenever a primitive is drawn the driver would call
_mesa_check_conditional_render which blocks waiting for the result of
the query to determine whether to render. On Gen7+ there is a bit in
the 3DPRIMITIVE command which can be used to disable the primitive
based on the value of a state bit. This state bit can be set based on
whether two registers have different values using the MI_PREDICATE
command. We can load these two registers with the pixel count values
stored in the query begin and end to implement conditional rendering
without stalling.

Unfortunately these two source registers were not in the whitelist of
available registers in the kernel driver until v3.19. This patch uses
the command parser version from intel_screen to detect whether to
attempt to set the predicate data registers.

The predicate enable bit is currently only used for drawing 3D
primitives. For blits, clears, bitmaps, copypixels and drawpixels it
still causes a stall. For most of these it would probably just work to
call the new brw_check_conditional_render function instead of
_mesa_check_conditional_render because they already work in terms of
rendering primitives. However it's a bit trickier for blits because it
can use the BLT ring or the blorp codepath. I think these operations
are less useful for conditional rendering than rendering primitives so
it might be best to leave it for a later patch.

v2: Use the command parser version to detect whether we can write to
the predicate data registers instead of trying to execute a
register load command.
v3: Simple rebase
v4: Changes suggested by Kenneth Graunke: Split the
load_64bit_register function out to a separate patch so it can be
a shared public function. Avoid calling
_mesa_check_conditional_render if we've already determined that
there's no query object. Some styling fixes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
51e3453785bc57087bb868dc93afbf620935b703 21-Apr-2015 Ian Romanick <ian.d.romanick@intel.com> i965: Sort extension enable lists

Sort by GEN, then sort by extension name.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
5fc23375e80dd2084f30700bdd3216082f662acc 06-May-2015 Chris Forbes <chrisf@ijw.co.nz> i965/gen6: Enable ARB_viewport_array and AMD_vertex_shader_viewport_index

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
ff6ee39c19adc59225d1f0664695c669cd7e5a94 24-Apr-2015 Matt Turner <mattst88@gmail.com> i965: Enable ARB_gpu_shader5 on Gen8+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
fdd90fcb15c109f3dcbf5e46fa8a1f8284b9c266 29-Mar-2015 Mathias Fröhlich <Mathias.Froehlich@gmx.net> i965: Implement support for ARB_clip_control.

Switch between the two clip space definitions already available
in hardware. Update winding order dependent state according
to the clip control state.
This change did not introduce new piglit quick.test regressions on
an Ivybridge Mobile and a GM45 Express chipset.
Also it enables and passes the clip-control and clip-control-depth-precision
tests on these two chipsets.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
e206785b5790c97743b7d3929563c21ad87aa765 03-Dec-2014 Ben Widawsky <benjamin.widawsky@intel.com> i965: implement ARB_pipeline_statistics_query

NOTE: The implementation was initially one patch, this. All the history is kept
here, even though all the core mesa changes were moved to the parent of this
patch.

This patch implements ARB_pipeline_statistics_query. This addition to GL does
not add a new API. Instead, it adds new tokens to the existing query APIs. The
work to hook up the new tokens is trivial due to it's similarity to the previous
work done for the query APIs. I've implemented all the new tokens to some
degree, but have stubbed out the untested ones at the entry point for Begin().
Doing this should allow the remainder of the code to be left in.

The new tokens give GL clients a way to obtain stats about the GL pipeline.
Generally, you get the number of things going in, invocations, and number of
things coming out, primitives, of the various stages. There are two immediate
uses for this, performance information, and debugging various types of
misrendering. I doubt one can use these for debugging very complex applications,
but for piglit tests, it should be quite useful.

Tessellation shaders, and compute shaders are not addressed in this patch
because there is no upstream implementation. I've implemented how I believe
tessellation shader stats will work for Intel hardware (though there is a bit of
ambiguity). Compute shaders are a bit more interesting though, and I don't yet
know what we'll do there.

For the lazy, here is a link to the relevant part of the spec:
https://www.opengl.org/registry/specs/ARB/pipeline_statistics_query.txt

Running the piglit tests
http://lists.freedesktop.org/archives/piglit/2014-November/013321.html
(http://cgit.freedesktop.org/~bwidawsk/piglit/log/?h=pipe_stats)
yield the following results:

> piglit-run.py -t stats tests/all.py output/pipeline_stats
> [5/5] pass: 5 Running Test(s): 5

v2:
- Don't allow pipeline_stats to be per stream (Ilia). This may (not sure) be
needed for AMD_transform_feedback4, which we do not support.
> If AMD_transform_feedback4 is supported then GEOMETRY_SHADER_PRIMITIVES_-
> EMITTED_ARB counts primitives emitted to any of the vertex streams for
> which STREAM_RASTERIZATION_AMD is enabled.
- Remove comment from GL3.txt because it is only used for extensions that are
part of required versions (Ilia)
- Move the new tokens to a new XML doc instead of using the main GL4x.xml (Ilia)
- Add a fallthrough comment (Ilia)
- Only divide PS invocations by 4 on HSW+ (Ben)

v3:
- Add ARB_pipeline_statistics_query to relnotes.html
- Add ARB_pipeline_statistics_query.xml to the Makefile.am, and master XML (Ilia)
- Correct extension number (Ilia)
- Add link to xml in the main GL API xml (Ilia)
- remove special GS case from gen6_end_query (Ian)
- Make lookup table static so gcc doesn't initialized it on every call (Ian)
- Use if (_mesa_has_geometry_shaders(ctx)) instead of explicit checks (Ian)
- Core mesa parts moved into a prep patch (Ilia)

v4:
- Change to 10.6 relnotes since we missed 10.5 window
- Moved compute shader stuff into the switch statement (Jordan)
- Jordan: Add compute shader support

v5:
- Fixed relnote style (Ilia)

v6:
- Rebased on master which beat me to adding the first relnotes - essentially
this undoes v5 (which had a typo anyway)
- Some code style fixes (Ken)
- Remove some excess comments (Ken)
- Unify tessellation failure style - unreachable (Ken)
- Fix workaround comment for PS invocations (Ken)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
2ce29ce5afbace43836fb55e8a5b5a989a222529 31-Dec-2014 Ilia Mirkin <imirkin@alum.mit.edu> i965/gen6+: enable EXT_polygon_offset_clamp

Replace the hard-coded 0's with the context clamp value.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
e638841b87a5d9454739195b49c403ca9a22a59e 08-Jan-2015 Kalyan Kondapally <kondapallykalyancontribute@gmail.com> Mesa: Advertise GL_OES_texture_*float* extensions support with i965.

This patch advertises support for GL_OES_texture_*float* extensions
when using i965 drivers.

Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
b7f14e03e3de218aedf4ba9439384c7bcbc091eb 22-Dec-2014 Kenneth Graunke <kenneth@whitecape.org> i965: Cache register write capability checks.

Our ability to perform register writes depends on the hardware and
kernel version. It shouldn't ever change on a per-context basis,
so we only need to check once.

Checking introduces a synchronization point between the CPU and GPU:
even though we submit very few GPU commands, the GPU might be busy doing
other work, which could cause us to stall for a while.

On an idle i7 4750HQ, this improves performance in OglDrvCtx (a context
creation microbenchmark) by 6.14748% +/- 1.6837% (n=20). With Unigine
Valley running in the background (to keep the GPU busy), it improves
performance in OglDrvCtx by 2290.92% +/- 29.5274% (n=5).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
94841b6d5dac6dcb445a30f083ec6e9858ad2f7d 30-Sep-2014 Kenneth Graunke <kenneth@whitecape.org> i965: Fix register write checks.

When mapping the buffer a second time, we need to use the new pointer,
not the one from the previous mapping. Otherwise, we will most likely
crash.

Apparently, we've just been getting lucky and getting the same
bo->virtual pointer in both cases. libdrm probably has a hand in that.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4330fa970bbca624ee93d0f9417984050acf970e 04-Sep-2014 Anuj Phogat <anuj.phogat@gmail.com> i965: Enable EXT_framebuffer_multisample_blit_scaled for gen8

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
c4ed6c730f5fab03e19bf009d1ed85da3fd966db 20-Sep-2014 Chris Forbes <chrisf@ijw.co.nz> i965/gen6: Enable GL 3.3 and GLSL 3.30

Tested on my snb-gt2:

4 tests skip->pass in spec/EXT_texture_array
51 tests skip->pass in spec.glsl-3.30
4 tests skip->pass in spec/!OpenGL 3.3
No regressions; no skip->fail changes.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
74d7ff2efda8e33e097ed6e3f9853fc1c8d45618 09-Jul-2014 Samuel Iglesias Gonsalvez <siglesias@igalia.com> i965/gen6: enable GLSL 1.50, OpenGL 3.2 and GL_AMD_vertex_shader_layered

Geometry shaders was the only thing we needed to enable GLSL 1.50 and
OpenGL 3.2 in gen6.

v2: Layered clears do not work properly in gen6 with OpenGL 3.2. Kenneth
and Jordan realized that for this to work we also need
GL_AMD_vertex_shader_layered (which requires OpenGL 3.2, so it could not be
enabled before this patch), so we agreed to enable this together with
OpenGL 3.2 in this patch.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
06ca96daadf88713a74c58761cb14edc5867e9b4 19-Aug-2014 Chris Forbes <chrisf@ijw.co.nz> i965: Enable ARB_conditional_render_inverted on Gen6+.

The extension requires GL 3.0, so enable on just the generations
exposing that.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4a3667993e8c3bace135791efbe2163a82bbfc56 10-Aug-2014 Chris Forbes <chrisf@ijw.co.nz> i965: Enable ARB_gpu_shader5 on Gen7

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
654b7788ebe7db63a3c5442d4eb1144b9284e9af 14-Aug-2014 Chris Forbes <chrisf@ijw.co.nz> i965: Enable ARB_derivative_control on Gen7+.

The extension says GL 4.0 is required. We'll meet the spirit
of that restriction by enabling on just those generations which will
soon support GL 4.0 (Gen7+), although it's technically supportable on
all generations.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
9782b8a80c1fbb41246f6ae94ac2944a91aa70da 17-Jul-2014 Neil Roberts <neil@linux.intel.com> i965: Enable the GL_ARB_texture_compression_bptc extension

Enables the BPTC extension on Gen>=7 and adds the necessary format mappings to
get the right surface type value.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
d9a6f4360a617fccfb3987f9ec276012a9a14b75 03-Aug-2014 Marek Olšák <marek.olsak@amd.com> mesa: make _mesa_override_glsl_version context-independent

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
410fea8dd9cc0b1b500477a8b6f68c950f7c895a 28-Jun-2014 Jason Ekstrand <jason.ekstrand@intel.com> i965: Add support for ARB_copy_image

This, together with the meta path, provides a complete implemetation of
ARB_copy_image.

v2: Add a fallback memcpy path for when the texture is too big for the
blitter
v3: Properly support copying between two places on the same texture in the
memcpy fallback
v4: Properly handle blit between the same two images in the fallback path
v5: Properly handle blit between the same two compressed images in the
fallback path
v6: Fix a typo in a comment

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
0779f37e1589b0ba4f1443a889f34dd83607c117 10-Jun-2014 Neil Roberts <neil@linux.intel.com> meta: Add a meta implementation of GL_ARB_clear_texture

Adds an implementation of the ClearTexSubImage driver entry point that tries
to set up an FBO to render to the texture and then calls glClearBuffer with a
scissor to perform the actual clear. If an FBO can't be created for the
texture then it will fall back to using _mesa_store_ClearTexSubImage.

When used in combination with _mesa_store_ClearTexSubImage this should provide
an implementation that works for all DRI-based drivers. However as this has
only been tested with the i965 driver it is currently only enabled there.

v2: Only enable the extension for the i965 driver instead of all DRI drivers.
Remove an unnecessary goto. Don't require GL_ARB_framebuffer_object. Add
some more comments.

v3: Use glClearBuffer* to avoid having to modify glClearColor and friends.
Handle sRGB textures. Explicitly disable dithering.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
7666a9f4ae3a058882a0aff66c8bf92c3da498f0 02-Jul-2014 Ilia Mirkin <imirkin@alum.mit.edu> i965: expose AMD_vertex_shader_viewport_index on gen7+

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4000c0112a49c28793844f454278b50e00943173 27-Jun-2014 Jason Ekstrand <jason.ekstrand@intel.com> Remove the ATI_envmap_bumpmap extension

As far as I can tell, the Intel mesa driver is the only driver in the world
still supporting this legacy extension. If someone wants to do bump
mapping, they can use shaders.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1]
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
Reviewed-by: Ian Romanick <idr@freedesktop.org> [v3]
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
10e03b4401b025f84b97f7e578a716a63c687196 08-Jun-2014 Jordan Justen <jordan.l.justen@intel.com> i965/cs: Use override structure rather than separate env var

In 25268b93, we added a new environment variable
(INTEL_COMPUTE_SHADER) to allow some constant values to be upgraded
for the ARB_compute_shader extension.

Now, we can look to see if the extension was enabled via the
MESA_EXTENSION_OVERRIDE environment variable.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
f3750a2c8667961c0595f5813b15be1476d13079 05-Mar-2014 Tapani Pälli <tapani.palli@intel.com> Enable GL_ARB_explicit_uniform_location in the drivers.

v2: enable also for i915 (Ian)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Petri Latvala <petri.latvala@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
0b96d362bf3f01b2b16d9216153fa3a1543bc2f5 14-May-2014 Kenneth Graunke <kenneth@whitecape.org> mesa: Disable GL_EXT_framebuffer_multisample_blit_scaled on Broadwell.

It's not properly implemented in the meta code, and we don't have time
to fix it for 10.2.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
ecfc418b68d3368df0f72116adad153c19d8c6d8 07-May-2014 Kenneth Graunke <kenneth@whitecape.org> i965: Enable GL_ARB_texture_view on Broadwell.

This is a port of commit c9c08867ed07ceb10b67ffac5f0a33812710a5e8.
A tiny bit of extra work was necessary to not break stencil texturing.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
b4363c8ea411cee5414ce267c3128a0fb551a730 23-Apr-2014 Petri Latvala <petri.latvala@intel.com> i965: Enable INTEL_performance_query for Gen5+.

Signed-off-by: Petri Latvala <petri.latvala@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
fb615feafb848bbccbdb751f552263bd32a37d82 26-Mar-2014 Ian Romanick <ian.d.romanick@intel.com> mesa: Remove support for desktop OpenGL GL_EXT_separate_shader_objects

I don't know of any applications that actually use it. Now that Mesa
supports GL_ARB_separate_shader_objects in all drivers, this extension
is just cruft.

The entrypoints for the extension remain in the XML. This is done so
that a new libGL will continue to provide dispatch support for old
drivers that try to expose this extension.

Future patches will add OpenGL ES GL_EXT_separate_shader_objects, but
that's a different thing.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
2a2f8cd9d2174eba98943ca6014bab126eb979e8 15-Feb-2014 Chris Forbes <chrisf@ijw.co.nz> i965: Enable ARB_texture_view on Gen7

V4: Don't enable this for Gen8 yet -- that still needs wired up.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
26ae030fcc364a4cfcdec0cbac2ca87d096c6cd0 08-Apr-2014 Kenneth Graunke <kenneth@whitecape.org> i965: Stop advertising GL_MESA_ycbcr_texture.

The "new" fragment shader backend has never supported the necessary
color conversion code for this to work. We began using the new backend
in Mesa 7.10 for GLSL (commit a81d423d93f22a948f3aa4bf73, October 2010),
and for ARB_fragment_program in Mesa 9.1 (commit 97615b2d8c7c3cea6fd3a4,
August 2012).

I haven't heard any complaints, so I don't think anyone will miss this
feature. I believe mplayer used it at one point, but these days
defaults to other paths anyway.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <idr@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
351e13c5ad81757a15ab319f2ef521b3921a345c 21-Mar-2014 Chris Forbes <chrisf@ijw.co.nz> i965: Enable ARB_vertex_type_10f_11f_11f_rev for Gen4/5 also.

Tested on ILK and CTG (with the GL3isms taken out of the piglits).

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
2f879356b552ad75bebbafc8d4bc1c97834b8b79 25-Feb-2014 Eric Anholt <eric@anholt.net> i965: Add support for GL_ARB_buffer_storage.

It turns out we can allow COHERENT storage/mappings all the time,
regardless of LLC vs non-LLC. It just means never using temporary
mappings to avoid GPU stalls, and on non-LLC we have to use the GTT intead
of CPU mappings. If we were to use CPU maps on non-LLC (which might be
useful if apps end up using buffer_storage on PBO reads, to avoid WC read
slowness), those would be PERSISTENT but not COHERENT, but doing that
would require us driving the clflushes from userspace somehow.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
dfa1ab0e52dde185c80f83b8e354a821f46c2949 24-Feb-2014 Kenneth Graunke <kenneth@whitecape.org> i965: Implement ARB_stencil_texturing on Gen8+.

On earlier hardware, we had to implement math in the shader to translate
Y-tiled or untiled coordinates to W-tiled coordinates (which is what
BLORP does today in order to texture from stencil buffers).

On Broadwell, we can simply state that it's W-tiled in SURFACE_STATE,
and adjust the pitch. This is much easier.

In the surface state code, I chose to handle the "should we sample depth
or stencil?" question separately from the setup for sampling from
stencil. This should make it work with the BindRenderbufferTexImage
hook as well, and hopefully be reusable for GL_ARB_texture_stencil8
someday.

v2: Update docs/GL3.txt (caught by Matt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
1edca151a00134778b959366d5e7c0a3b63cc8f7 14-Jan-2014 Ian Romanick <ian.d.romanick@intel.com> mesa: GL_ARB_half_float_pixel is not optional

Almost every driver already supported it. All current and future
Gallium drivers always support it, and most existing classic drivers
support it.

This only changes radeon and nouveau.

This extension only adds data types that can be passed to, for example,
glTexImage2D. It does not add internal formats. Since you can already
pass GL_FLOAT to glTexImage2D this shouldn't pose any additional issues
with those drivers. Note that r200 and i915 already supported this
extension, and they don't support floating-point textures either.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
0c14c5c62a1b4648381c05f024db730e4a0f90c5 02-Feb-2014 Chris Forbes <chrisf@ijw.co.nz> i965: Enable ARB_texture_gather for one component on Gen6.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
25268b930dbd9bc89c0cce83746c5ca2f534c016 07-Jan-2014 Paul Berry <stereotype441@gmail.com> i965/cs: Allow ARB_compute_shader to be enabled via env var.

This will allow testing of compute shader functionality before it is
completed.

To enable ARB_compute_shader functionality in the i965 driver, set
INTEL_COMPUTE_SHADER=1.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
a6729731af700d5a44525d583a83619b5e454084 13-Nov-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: GL_EXT_framebuffer_blit is not optional

Every driver supports it. All current and future Gallium drivers always
support it, and all existing classic drivers support it.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
7837f425e7242bfc12f3d6d57d343609071ea6aa 13-Nov-2013 Courtney Goeltzenleuchter <courtney@LunarG.com> i965: Enable ARB_viewport_array

v2 (idr): Only enable the extension on GEN7+ w/core profile because it
requires geometry shaders.

v3 (idr): Add some casting to fix setting of ViewportBounds.Min.
Negating an unsigned value, then casting to float doesn't do what you
might think it does.

Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com>
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
877128505431adaf817dc8069172ebe4a1cdf5d8 17-Jan-2014 José Fonseca <jfonseca@vmware.com> s/Tungsten Graphics/VMware/

Tungsten Graphics Inc. was acquired by VMware Inc. in 2008. Leaving the
old copyright name is creating unnecessary confusion, hence this change.

This was the sed script I used:

$ cat tg2vmw.sed
# Run as:
#
# git reset --hard HEAD && find include scons src -type f -not -name 'sed*' -print0 | xargs -0 sed -i -f tg2vmw.sed
#

# Rename copyrights
s/Tungsten Gra\(ph\|hp\)ics,\? [iI]nc\.\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./g
/Copyright/s/Tungsten Graphics\(,\? [iI]nc\.\)\?\(, Cedar Park\)\?\(, Austin\)\?\(, \(Texas\|TX\)\)\?\.\?/VMware, Inc./
s/TUNGSTEN GRAPHICS/VMWARE/g

# Rename emails
s/alanh@tungstengraphics.com/alanh@vmware.com/
s/jens@tungstengraphics.com/jowen@vmware.com/g
s/jrfonseca-at-tungstengraphics-dot-com/jfonseca-at-vmware-dot-com/
s/jrfonseca\?@tungstengraphics.com/jfonseca@vmware.com/g
s/keithw\?@tungstengraphics.com/keithw@vmware.com/g
s/michel@tungstengraphics.com/daenzer@vmware.com/g
s/thomas-at-tungstengraphics-dot-com/thellstom-at-vmware-dot-com/
s/zack@tungstengraphics.com/zackr@vmware.com/

# Remove dead links
s@Tungsten Graphics (http://www.tungstengraphics.com)@Tungsten Graphics@g

# C string src/gallium/state_trackers/vega/api_misc.c
s/"Tungsten Graphics, Inc"/"VMware, Inc"/

Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
a92b9e60aba8cd1fc5d935abc9fd8f37cae89168 13-Nov-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: GL_EXT_packed_depth_stencil is not optional

Every driver supports it. All current and future Gallium drivers always
support it, and all existing classic drivers support it.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
a7bdd4cba8ddcab8dff59ecaaa7efbd436c6c307 26-Nov-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Drop trailing whitespace from the rest of the driver.

Performed via:
$ for file in *; do sed -i 's/ *//g'; done

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
538a7f2a8082e748caa599636c01833332bd039a 20-Nov-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: Use a single enable for GL_EXT_texture_array and GL_MESA_texture_array

Every driver that enables one also enables the other. The difference
between the two is MESA adds support for fixed-function and assembly
fragment shaders, but EXT only adds support for GLSL. The MESA
extension was created back when Mesa did not support GLSL.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
decf070258f396223aac6f57e22540a304986e54 04-Nov-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Skip the register write check on Broadwell.

MI_STORE_REGISTER_MEM has to take a 48-bit address, so the existing code
doesn't work. But supposedly Broadwell has a register whitelist and
just works out of the box anyway, so there's no need to check.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
e6a0eca45e5f760656542035b25238a9d5dfdbd0 30-Sep-2013 Chris Forbes <chrisf@ijw.co.nz> i965: Enable ARB_draw_indirect (and ARB_multi_draw_indirect) on Gen7+

.. and mark them off on the extensions list as done.

V2: Enable only if pipelined register writes work.
V3: Also update relnotes

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
bd00c66500712b9eb594cd6a7ff501811f170f78 27-Mar-2013 Jordan Justen <jordan.l.justen@intel.com> intel: enable GL_AMD_vertex_shader_layer extension for gen7+

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
7a70f033b5fbb8d3e5956cc4df30b84f0d4d9653 14-Nov-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Enable the AMD_performance_monitor extension on Gen5+.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
597634556e4d24c5a3aec2da227034a733693571 20-Oct-2013 Francisco Jerez <currojerez@riseup.net> i965/gen7: Expose ARB_shader_atomic_counters.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
30f61c471de5a9637e5d830e2b5b9dc4145f94d2 23-Oct-2013 Kenneth Graunke <kenneth@whitecape.org> Revert "i965: Add support for GL_AMD_performance_monitor on Ironlake."

This reverts most of commit 0f2da773070c06b6d20ad264d3abb19c4dfd9761.
(I chose to leave the additions to brw_defines.h.)

My previous Ironlake implementation was somewhat broken: counter data
was global, rather than per-context. This meant that performance
monitors captured data from your compositor, 2D driver, and other 3D
programs.

Originally, I believed that Sandybridge and later had an easy way to
avoid this problem (setting per-context flags in OACONTROL), while
Ironlake did not. So I'd intended to leave it as a known limitation of
performance monitoring support on Ironlake. However, this turned out
not to be true.

Unfortunately, our hardware only has one set of aggregating performance
counters shared between all 3D programs, and their values are not saved
or restored by hardware contexts. Also, at least on Sandybridge and
Ivybridge, the counters lose their values if the GPU goes to sleep.

To work around both of these problems, we have to snapshot the
performance counters at the beginning and end of each batch, similar to
how we handle query objects on platforms that don't support hardware
contexts.

For occlusion queries, this batch bookending approach is fairly simple:
only one occlusion query can be active at a time, and the result is a
single integer. Performance monitors are more complex: an arbitrary
number of monitors can be active at a time, each monitoring some subset
of our ~30 observability counters. Individual monitors can be started
and stopped at any point during the batch. Tracking where each monitor
started/ended relative to batch flushes ends up being a pain. And you
can run out of space in the buffer.

Properly supporting this required some serious rearchitecting of the
code. Rather than writing patches to try and morph a broken system into
a working one (which operates quite differently), I decided it would be
simplest to revert the old code and start fresh. Parts will look
familiar, but other parts are new.

I also decided it would be best to include Sandybridge and Ivybridge
support from the start, since the newer platforms have added complexity
that I wanted to make sure worked. They're also what most people care
about these days.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
5e61c746d53a0b65c642a22fad21a1876147d6d0 07-Nov-2013 Chris Forbes <chrisf@ijw.co.nz> i965: Enable ARB_vertex_type_10f_11f_11f_rev on Gen6+.

This theoretically works on earlier hardware as well, but the extension
requires at least GL3.0.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
625a6313837f001196bfb8fde8f9f0b4c291aaad 30-Aug-2013 Anuj Phogat <anuj.phogat@gmail.com> i965: Enable ARB_sample_shading on intel hardware >= gen6

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Ken Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
0eeaf11edf72bbd2943a4b9bffa5f8d5bfe77dd5 26-Oct-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Enable the ARB_transform_feedback_instanced extension on Gen7+.

This depends on ARB_transform_feedback2, so I've predicated it on the
ability to do register writes.

It also depends on ARB_transform_feedback3, which is the only reason we
couldn't expose it previously.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
c4ec0ad8a90c2023cb77e578d39dddb0cddeada9 26-Oct-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Enable the ARB_transform_feedback3 extension on Gen7+.

This extension is written a bit strangely. Although it introduces the
concept of multiple transform feedback streams, it doesn't actually
provide more than a single stream.

The ARB_gpu_shader5 extension is what introduces the ability to write to
streams other than stream #0 and increases the required number of streams.

Since we don't yet support ARB_gpu_shader5, we can safely enable
ARB_transform_feedback3 even though we only support a single stream.
This does provide some useful functionality: applications can now use
more than one interleaved transform feedback buffer.

v2: Only expose the extension if ARB_transform_feedback2 is also
available, to avoid confusing applications (suggested by Ian).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
129da5b1c87e4fd45b117a092e5d022ad7041e66 28-May-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Enable ARB_transform_feedback2 on Gen7+ if register writes work.

With Linux 3.12, register writes work on Ivybridge and Baytrail, but not
Haswell. That will be fixed in a future kernel revision, at which point
this extension will automatically be enabled.

v2: Use I915_GEM_DOMAIN_INSTRUCTION for the register read, and also
correctly set the writeable flag when mapping (caught by Eric).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
a5e2e7f9a4bc813ce85f4a10bcd6086f21aa8a32 05-Oct-2013 Eric Anholt <eric@anholt.net> i965: Add support for GL_ARB_texture_buffer_range.

Supporting this extension turns out to simplify our code a bit over not
supporting this extension, once the glBufferSubData() synchronization code
lands.

v2: Use 16 byte alignment like we do for uniform buffers, due to unaligned
access penalties.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
2d3282188e3f95c0a81aca01f01e0c4424127320 21-Oct-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Implement ARB_texture_mirror_clamp_to_edge.

This passes Piglit's texwrap tests.

v2: Remove _EXT suffix.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Rico Schüller <kgbricola@web.de>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
567445e2b9f64cdb0a97ec883a9dfd5ed59d21fc 18-Oct-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Enable OpenGL 3.3 and GLSL 3.30.

Everything necessary for these appears to be implemented. We'll want to
add more tests to guard against bugs, but it should be functionally
complete.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
b6d6ea396c692b451b0195f07613e160b731d986 22-Mar-2013 Paul Berry <stereotype441@gmail.com> i965: Turn on GLSL 1.50 and GL 3.2 support for i965 gen7.

Geometry shaders were the last thing we needed to finish before
turning on GLSL 1.50 and GL 3.2 support. They are now working well,
with just a few piglit failures left to fix.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
7ec46686967b8b8aab5a2ef36416e59e9d83d5fb 05-Oct-2013 Chris Forbes <chrisf@ijw.co.nz> i965: Enable ARB_conservative_depth for Gen7+.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
317e172677541771d3dbfadba852f067d8d881a1 05-Oct-2013 Chris Forbes <chrisf@ijw.co.nz> i965: enable ARB_texture_query_levels on Gen6+

Theoretically would work on Gen5 as well but requires GLSL 1.30, which
is not (yet) enabled by default there.

V2: Enable for Gen5 conditionally on GLSL version.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
7df985ad47df831f842843f2db9f7658b11d3df2 24-Mar-2013 Chris Forbes <chrisf@ijw.co.nz> i965: Enable ARB_texture_gather on Gen7

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
0f2da773070c06b6d20ad264d3abb19c4dfd9761 11-Apr-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Add support for GL_AMD_performance_monitor on Ironlake.

Ironlake's counters are always enabled; userspace can simply send a
MI_REPORT_PERF_COUNT packet to take a snapshot of them. This makes it
easy to implement.

The counters are documented in the source code for the intel-gpu-tools
intel_perf_counters utility.

v2: Adjust for core data structure changes. Add a table mapping buffer
object offsets to exposed counters (which changes each generation).
Finally, add report ID assertions to sanity check the BO layout
(thanks to Carl Worth).

v3: Update for core BeginPerfMonitor hook changes (requested by Brian).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
ea373f03e8d7783f70c78f700cd80032fd6dc8c4 12-Sep-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: Rename MESA_shader_integer_mix to EXT_shader_integer_mix

Everyone at the Khronos meeting was as surprised that GLSL didn't
already support this as we were. Several vendors said they'd ship it,
but there didn't seem to be enough interest to put in the effort to make
it ARB or KHR.

v2: Fix a couple typos and rename the spec file to
EXT_shader_integer_mix.spec. Suggested by Roland.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
d83221c2d33dcad3e5d3f8d8fa6abddea63b8817 07-Sep-2013 Matt Turner <mattst88@gmail.com> i965: Enable MESA_shader_integer_mix.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
2937d704dcae4451b2baa7d02f97205e73b37c8c 04-Sep-2013 Ian Romanick <ian.d.romanick@intel.com> i965: Enable AMD_seamless_cubemap_per_texture

The change is very small. Do seamless filtering if either the context
enable is set or the sampler enable is set.

The AMD_seamless_cubemap_per_texture says:

"If TEXTURE_CUBE_MAP_SEAMLESS_ARB is emabled (sic) globally or the
value of the texture's TEXTURE_CUBE_MAP_SEAMLESS_ARB parameter is
TRUE, seamless cube map sampling is enabled..."

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
f5947c2bc72a630d1abd2a12221d8dafd3a24be4 12-Nov-2012 Topi Pohjolainen <topi.pohjolainen@intel.com> i965: enable image external sampling for imported dma-buffers

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
46d9baf3e3186078ca5a74f9d3e70ad493f899cb 18-Jul-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Enable the GL_ARB_shading_language_420pack extension on Gen6+.

While all the work is in the shared GLSL compiler, this extension
requires GLSL 1.30, which is currently only supported on Gen6+.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
53631be4ebaa4fb13a7f129727c1cdd32fcc6f3d 06-Jul-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Move intel_context::gen and gt fields to brw_context.

Most functions no longer use intel_context, so this patch additionally
removes the local "intel" variables to avoid compiler warnings.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
e3c2bb1eb4ef73c1c9576f0d5b747605b5de47ef 04-Jul-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Shorten context base class dereference chains.

ctx->DrawBuffer is much more sensible than brw->intel.ctx.DrawBuffer.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
eeb75b41f1d7be609861d3e98b64b6fffd13bb4f 03-Jul-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Move intel_context::bufmgr to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
fbdd3891e1d08f388571c20db96516f39fe11898 03-Jul-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Move intel_context::optionCache to brw_context.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
a69274454b6bde265a910ca5bd3199217431f5b5 03-Jul-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Replace #include "intel_context.h" with brw_context.h.

brw_context.h includes intel_context.h, but additionally makes the
brw_context structure available. Switching this allows us to start
using brw_context in more places.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
7d8e70f301cf9712826b3a3cf935c0a7eceaa08b 02-Jul-2013 Kenneth Graunke <kenneth@whitecape.org> i965: Move contents of intel_extensions.h to intel_context.h.

Having an entire header file for a single prototype seems a bit
excessive.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
722721d718ffe989426279ff06c21e58be287333 14-May-2013 Anuj Phogat <anuj.phogat@gmail.com> i965: Enable ext_framebuffer_multisample_blit_scaled on intel h/w

This patch enables ext_framebuffer_multisample_blit_scaled extension
on intel h/w >= gen6.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
927f572c27f0e734896fa2b4f93210c7daf1a62a 28-Jun-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: GL_EXT_shadow_funcs is not optional with GL_ARB_shadow

Every driver left in Mesa that enables one also enables the other.
There's no reason to let it be optional.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
41853b598c0a49b2e75d7013658806d46beceec0 28-Jun-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: GL_ARB_texture_storage_multisample is not optional with GL_ARB_texture_multisample

In Mesa, this extension is implemented purely in software. Drivers may
*optionally* provide optimized paths. If a driver enables,
GL_ARB_texture_multisample, it gets GL_ARB_texture_storage_multisample
for free.

NOTE: This has the side effect of enabling the extension in Gallium
drivers that enable GL_ARB_texture_multisample.

v2 (Ken): Still prevent multisample texture targets in TexParameter for
implementations that don't support multisampling.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
d5b6b7a39ba91f21278a2ad24c4ad00d454c73c6 28-Jun-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: GL_ARB_texture_storage is not optional

In Mesa, this extension is implemented purely in software. Drivers may
*optionally* provide optimized paths.

NOTE: This has the side effect of enabling the extension in the radeon,
r200, and nouveau drivers.

v2: Minor whitespace tidying (suggested by Brian).

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
70966570f3e4275dc15b5a94c70698f6aef64150 28-Jun-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: GL_ARB_shading_language_100 is not optional

This extension just provides some of the most basic software framework
for GLSL. Without GL_ARB_vertex_shader or GL_ARB_fragment_shader,
applications still cannot use GLSL. There's no value in
conditionalizing support for this extension.

NOTE: This has the side effect of enabling the extension in the radeon,
r200, and nouveau drivers.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
e6ec425d6eeac95f466174267b2c18c0bffca3f0 28-Jun-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: GL_ARB_shader_objects is not optional

This extension just provides some of the most basic software framework
for GLSL. Without GL_ARB_vertex_shader or GL_ARB_fragment_shader,
applications still cannot use GLSL. There's no value in
conditionalizing support for this extension.

NOTE: This has the side effect of enabling the extension in the radeon,
r200, and nouveau drivers.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
9bc24b4fc4ee1eda60d4f4bde662f7a1d8474cc1 28-Jun-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: GL_NV_blend_square is not optional

Every driver left in Mesa enables this extension all the time. There's
no reason to let it be optional.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
338ea2e4d14b5bf30fe2820facd71333d5acd527 28-Jun-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: GL_EXT_fog_coord is not optional

Every driver left in Mesa enables this extension all the time. There's
no reason to let it be optional.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
c139708087ead063da7ac64126af69f2fe7bcf1e 28-Jun-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: GL_EXT_secondary_color is not optional

Every driver left in Mesa enables this extension all the time. There's
no reason to let it be optional.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
b5305a303bd13f91a00f36f205b767d1bfef2ab5 28-Jun-2013 Ian Romanick <ian.d.romanick@intel.com> mesa: GL_EXT_framebuffer_object is not optional

Every driver left in Mesa enables this extension all the time. There's
no reason to let it be optional.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
0b9398c74f0189b7d7904749e24934e08a0a4cfb 28-Jun-2013 Ian Romanick <ian.d.romanick@intel.com> i965: Merge the two GEN >= 6 extension enable blocks

There's no reason for these blocks to be separate.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
ae66a656fd3e205d81284f45bbc0422c7e198da6 28-Jun-2013 Ian Romanick <ian.d.romanick@intel.com> i965: Move GEN >= 4 extensions into the "always on" list

This copy of the source file is only used for GEN >= 4, so extensions
that are enabled for GEN >= 4 are always enabled.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4ed976f6b5866e69ea84fe19fb9143766cf08c5e 28-Jun-2013 Ian Romanick <ian.d.romanick@intel.com> i965: Move GEN >= 3 extensions into the "always on" list

This copy of the source file is only used for GEN >= 4, so extensions
that are enabled for GEN >= 3 are always enabled.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
3dbba95b72262344b82fba018b7c2c1208754cd2 21-Jun-2013 Eric Anholt <eric@anholt.net> i965: Move the remaining intel code to the i965 directory.

Now that i915's forked off, they don't need to live in a shared directory.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad.versace@linux.intel.com>
Acked-by: Adam Jackson <ajax@redhat.com>
(and I hear second hand that idr is OK with it, too)
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c
4006c5e4526a1cdb910500764590e39d32750967 26-Jan-2009 Brian Paul <brianp@vmware.com> intel: move intelInitExtensions() and related code into new intel_extensions.c
/external/mesa3d/src/mesa/drivers/dri/i965/intel_extensions.c