intel_extensions.c revision bd00c66500712b9eb594cd6a7ff501811f170f78 
1/**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "main/version.h"
29
30#include "brw_context.h"
31#include "intel_batchbuffer.h"
32#include "intel_reg.h"
33#include "utils.h"
34
35/**
36 * Test if we can use MI_LOAD_REGISTER_MEM from an untrusted batchbuffer.
37 *
38 * Some combinations of hardware and kernel versions allow this feature,
39 * while others don't.  Instead of trying to enumerate every case, just
40 * try and write a register and see if works.
41 */
42static bool
43can_do_pipelined_register_writes(struct brw_context *brw)
44{
45   /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the
46    * statistics registers), and we already reset it to zero before using it.
47    */
48   const int reg = GEN7_SO_WRITE_OFFSET(0);
49   const int expected_value = 0x1337d0d0;
50   const int offset = 100;
51
52   /* The register we picked only exists on Gen7+. */
53   assert(brw->gen >= 7);
54
55   uint32_t *data;
56   /* Set a value in a BO to a known quantity.  The workaround BO already
57    * exists and doesn't contain anything important, so we may as well use it.
58    */
59   drm_intel_bo_map(brw->batch.workaround_bo, true);
60   data = brw->batch.workaround_bo->virtual;
61   data[offset] = 0xffffffff;
62   drm_intel_bo_unmap(brw->batch.workaround_bo);
63
64   /* Write the register. */
65   BEGIN_BATCH(3);
66   OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
67   OUT_BATCH(reg);
68   OUT_BATCH(expected_value);
69   ADVANCE_BATCH();
70
71   intel_batchbuffer_emit_mi_flush(brw);
72
73   /* Save the register's value back to the buffer. */
74   BEGIN_BATCH(3);
75   OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
76   OUT_BATCH(reg);
77   OUT_RELOC(brw->batch.workaround_bo,
78             I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
79             offset * sizeof(uint32_t));
80   ADVANCE_BATCH();
81
82   intel_batchbuffer_flush(brw);
83
84   /* Check whether the value got written. */
85   drm_intel_bo_map(brw->batch.workaround_bo, false);
86   bool success = data[offset] == expected_value;
87   drm_intel_bo_unmap(brw->batch.workaround_bo);
88
89   return success;
90}
91
92static bool
93can_write_oacontrol(struct brw_context *brw)
94{
95   if (brw->gen < 6 || brw->gen >= 8)
96      return false;
97
98   /* Set "Select Context ID" to a particular address (which is likely not a
99    * context), but leave all counting disabled.  This should be harmless.
100    */
101   const int expected_value = 0x31337000;
102   const int offset = 110;
103
104   uint32_t *data;
105   /* Set a value in a BO to a known quantity.  The workaround BO already
106    * exists and doesn't contain anything important, so we may as well use it.
107    */
108   drm_intel_bo_map(brw->batch.workaround_bo, true);
109   data = brw->batch.workaround_bo->virtual;
110   data[offset] = 0xffffffff;
111   drm_intel_bo_unmap(brw->batch.workaround_bo);
112
113   /* Write OACONTROL. */
114   BEGIN_BATCH(3);
115   OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
116   OUT_BATCH(OACONTROL);
117   OUT_BATCH(expected_value);
118   ADVANCE_BATCH();
119
120   intel_batchbuffer_emit_mi_flush(brw);
121
122   /* Save the register's value back to the buffer. */
123   BEGIN_BATCH(3);
124   OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
125   OUT_BATCH(OACONTROL);
126   OUT_RELOC(brw->batch.workaround_bo,
127             I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
128             offset * sizeof(uint32_t));
129   ADVANCE_BATCH();
130
131   intel_batchbuffer_emit_mi_flush(brw);
132
133   /* Set OACONTROL back to zero (everything off). */
134   BEGIN_BATCH(3);
135   OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
136   OUT_BATCH(OACONTROL);
137   OUT_BATCH(0);
138   ADVANCE_BATCH();
139
140   intel_batchbuffer_flush(brw);
141
142   /* Check whether the value got written. */
143   drm_intel_bo_map(brw->batch.workaround_bo, false);
144   bool success = data[offset] == expected_value;
145   drm_intel_bo_unmap(brw->batch.workaround_bo);
146
147   return success;
148}
149
150/**
151 * Initializes potential list of extensions if ctx == NULL, or actually enables
152 * extensions for a context.
153 */
154void
155intelInitExtensions(struct gl_context *ctx)
156{
157   struct brw_context *brw = brw_context(ctx);
158
159   assert(brw->gen >= 4);
160
161   ctx->Extensions.ARB_depth_buffer_float = true;
162   ctx->Extensions.ARB_depth_clamp = true;
163   ctx->Extensions.ARB_depth_texture = true;
164   ctx->Extensions.ARB_draw_elements_base_vertex = true;
165   ctx->Extensions.ARB_draw_instanced = true;
166   ctx->Extensions.ARB_ES2_compatibility = true;
167   ctx->Extensions.ARB_explicit_attrib_location = true;
168   ctx->Extensions.ARB_fragment_coord_conventions = true;
169   ctx->Extensions.ARB_fragment_program = true;
170   ctx->Extensions.ARB_fragment_program_shadow = true;
171   ctx->Extensions.ARB_fragment_shader = true;
172   ctx->Extensions.ARB_framebuffer_object = true;
173   ctx->Extensions.ARB_half_float_pixel = true;
174   ctx->Extensions.ARB_half_float_vertex = true;
175   ctx->Extensions.ARB_instanced_arrays = true;
176   ctx->Extensions.ARB_internalformat_query = true;
177   ctx->Extensions.ARB_map_buffer_range = true;
178   ctx->Extensions.ARB_occlusion_query = true;
179   ctx->Extensions.ARB_occlusion_query2 = true;
180   ctx->Extensions.ARB_point_sprite = true;
181   ctx->Extensions.ARB_seamless_cube_map = true;
182   ctx->Extensions.ARB_shader_bit_encoding = true;
183   ctx->Extensions.ARB_shader_texture_lod = true;
184   ctx->Extensions.ARB_shadow = true;
185   ctx->Extensions.ARB_sync = true;
186   ctx->Extensions.ARB_texture_border_clamp = true;
187   ctx->Extensions.ARB_texture_compression_rgtc = true;
188   ctx->Extensions.ARB_texture_cube_map = true;
189   ctx->Extensions.ARB_texture_env_combine = true;
190   ctx->Extensions.ARB_texture_env_crossbar = true;
191   ctx->Extensions.ARB_texture_env_dot3 = true;
192   ctx->Extensions.ARB_texture_float = true;
193   ctx->Extensions.ARB_texture_mirror_clamp_to_edge = true;
194   ctx->Extensions.ARB_texture_non_power_of_two = true;
195   ctx->Extensions.ARB_texture_rg = true;
196   ctx->Extensions.ARB_texture_rgb10_a2ui = true;
197   ctx->Extensions.ARB_vertex_program = true;
198   ctx->Extensions.ARB_vertex_shader = true;
199   ctx->Extensions.ARB_vertex_type_2_10_10_10_rev = true;
200   ctx->Extensions.EXT_blend_color = true;
201   ctx->Extensions.EXT_blend_equation_separate = true;
202   ctx->Extensions.EXT_blend_func_separate = true;
203   ctx->Extensions.EXT_blend_minmax = true;
204   ctx->Extensions.EXT_draw_buffers2 = true;
205   ctx->Extensions.EXT_framebuffer_blit = true;
206   ctx->Extensions.EXT_framebuffer_sRGB = true;
207   ctx->Extensions.EXT_gpu_program_parameters = true;
208   ctx->Extensions.EXT_packed_depth_stencil = true;
209   ctx->Extensions.EXT_packed_float = true;
210   ctx->Extensions.EXT_pixel_buffer_object = true;
211   ctx->Extensions.EXT_point_parameters = true;
212   ctx->Extensions.EXT_provoking_vertex = true;
213   ctx->Extensions.EXT_separate_shader_objects = true;
214   ctx->Extensions.EXT_texture_array = true;
215   ctx->Extensions.EXT_texture_env_dot3 = true;
216   ctx->Extensions.EXT_texture_filter_anisotropic = true;
217   ctx->Extensions.EXT_texture_integer = true;
218   ctx->Extensions.EXT_texture_shared_exponent = true;
219   ctx->Extensions.EXT_texture_snorm = true;
220   ctx->Extensions.EXT_texture_sRGB = true;
221   ctx->Extensions.EXT_texture_sRGB_decode = true;
222   ctx->Extensions.EXT_texture_swizzle = true;
223   ctx->Extensions.EXT_stencil_two_side = true;
224   ctx->Extensions.EXT_vertex_array_bgra = true;
225   ctx->Extensions.AMD_seamless_cubemap_per_texture = true;
226   ctx->Extensions.APPLE_object_purgeable = true;
227   ctx->Extensions.ATI_envmap_bumpmap = true;
228   ctx->Extensions.ATI_separate_stencil = true;
229   ctx->Extensions.ATI_texture_env_combine3 = true;
230   ctx->Extensions.MESA_pack_invert = true;
231   ctx->Extensions.MESA_texture_array = true;
232   ctx->Extensions.MESA_ycbcr_texture = true;
233   ctx->Extensions.NV_conditional_render = true;
234   ctx->Extensions.NV_primitive_restart = true;
235   ctx->Extensions.NV_texture_env_combine4 = true;
236   ctx->Extensions.NV_texture_rectangle = true;
237   ctx->Extensions.TDFX_texture_compression_FXT1 = true;
238   ctx->Extensions.OES_compressed_ETC1_RGB8_texture = true;
239   ctx->Extensions.OES_EGL_image = true;
240   ctx->Extensions.OES_draw_texture = true;
241   ctx->Extensions.OES_standard_derivatives = true;
242   ctx->Extensions.OES_EGL_image_external = true;
243
244   if (brw->gen >= 7)
245      ctx->Const.GLSLVersion = 330;
246   else if (brw->gen >= 6)
247      ctx->Const.GLSLVersion = 140;
248   else
249      ctx->Const.GLSLVersion = 120;
250   _mesa_override_glsl_version(ctx);
251
252   if (brw->gen >= 6) {
253      uint64_t dummy;
254
255      ctx->Extensions.EXT_framebuffer_multisample = true;
256      ctx->Extensions.EXT_transform_feedback = true;
257      ctx->Extensions.EXT_framebuffer_multisample_blit_scaled = true;
258      ctx->Extensions.ARB_blend_func_extended = !driQueryOptionb(&brw->optionCache, "disable_blend_func_extended");
259      ctx->Extensions.ARB_draw_buffers_blend = true;
260      ctx->Extensions.ARB_ES3_compatibility = true;
261      ctx->Extensions.ARB_uniform_buffer_object = true;
262      ctx->Extensions.ARB_shading_language_420pack = true;
263      ctx->Extensions.ARB_texture_buffer_object = true;
264      ctx->Extensions.ARB_texture_buffer_object_rgb32 = true;
265      ctx->Extensions.ARB_texture_buffer_range = true;
266      ctx->Extensions.ARB_texture_cube_map_array = true;
267      ctx->Extensions.OES_depth_texture_cube_map = true;
268      ctx->Extensions.ARB_shading_language_packing = true;
269      ctx->Extensions.ARB_texture_multisample = true;
270      ctx->Extensions.ARB_sample_shading = true;
271      ctx->Extensions.ARB_vertex_type_10f_11f_11f_rev = true;
272
273      /* Test if the kernel has the ioctl. */
274      if (drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &dummy) == 0)
275         ctx->Extensions.ARB_timer_query = true;
276   }
277
278   if (brw->gen >= 5) {
279      ctx->Extensions.ARB_texture_query_lod = true;
280      ctx->Extensions.EXT_timer_query = true;
281      ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130;
282      ctx->Extensions.ARB_texture_query_levels = ctx->Const.GLSLVersion >= 130;
283   }
284
285   if (brw->gen >= 7) {
286      ctx->Extensions.ARB_texture_gather = true;
287      ctx->Extensions.ARB_conservative_depth = true;
288      ctx->Extensions.AMD_vertex_shader_layer = true;
289      if (can_do_pipelined_register_writes(brw)) {
290         ctx->Extensions.ARB_transform_feedback2 = true;
291         ctx->Extensions.ARB_transform_feedback3 = true;
292         ctx->Extensions.ARB_transform_feedback_instanced = true;
293      }
294   }
295
296   if (brw->gen == 5 || can_write_oacontrol(brw))
297      ctx->Extensions.AMD_performance_monitor = true;
298
299   if (ctx->API == API_OPENGL_CORE)
300      ctx->Extensions.ARB_base_instance = true;
301   if (ctx->API != API_OPENGL_CORE)
302      ctx->Extensions.ARB_color_buffer_float = true;
303
304   if (ctx->Mesa_DXTn || driQueryOptionb(&brw->optionCache, "force_s3tc_enable"))
305      ctx->Extensions.EXT_texture_compression_s3tc = true;
306
307   ctx->Extensions.ANGLE_texture_compression_dxt = true;
308
309   if (brw->gen >= 7)
310      ctx->Extensions.ARB_shader_atomic_counters = true;
311}
312