1//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This class prints an PPC MCInst to a .s file. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "asm-printer" 15#include "PPCInstPrinter.h" 16#include "MCTargetDesc/PPCBaseInfo.h" 17#include "MCTargetDesc/PPCPredicates.h" 18#include "llvm/MC/MCExpr.h" 19#include "llvm/MC/MCInst.h" 20#include "llvm/Support/raw_ostream.h" 21using namespace llvm; 22 23#define GET_INSTRUCTION_NAME 24#include "PPCGenAsmWriter.inc" 25 26StringRef PPCInstPrinter::getOpcodeName(unsigned Opcode) const { 27 return getInstructionName(Opcode); 28} 29 30void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 31 OS << getRegisterName(RegNo); 32} 33 34void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, 35 StringRef Annot) { 36 // Check for slwi/srwi mnemonics. 37 if (MI->getOpcode() == PPC::RLWINM) { 38 unsigned char SH = MI->getOperand(2).getImm(); 39 unsigned char MB = MI->getOperand(3).getImm(); 40 unsigned char ME = MI->getOperand(4).getImm(); 41 bool useSubstituteMnemonic = false; 42 if (SH <= 31 && MB == 0 && ME == (31-SH)) { 43 O << "\tslwi "; useSubstituteMnemonic = true; 44 } 45 if (SH <= 31 && MB == (32-SH) && ME == 31) { 46 O << "\tsrwi "; useSubstituteMnemonic = true; 47 SH = 32-SH; 48 } 49 if (useSubstituteMnemonic) { 50 printOperand(MI, 0, O); 51 O << ", "; 52 printOperand(MI, 1, O); 53 O << ", " << (unsigned int)SH; 54 55 printAnnotation(O, Annot); 56 return; 57 } 58 } 59 60 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && 61 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { 62 O << "\tmr "; 63 printOperand(MI, 0, O); 64 O << ", "; 65 printOperand(MI, 1, O); 66 printAnnotation(O, Annot); 67 return; 68 } 69 70 if (MI->getOpcode() == PPC::RLDICR) { 71 unsigned char SH = MI->getOperand(2).getImm(); 72 unsigned char ME = MI->getOperand(3).getImm(); 73 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH 74 if (63-SH == ME) { 75 O << "\tsldi "; 76 printOperand(MI, 0, O); 77 O << ", "; 78 printOperand(MI, 1, O); 79 O << ", " << (unsigned int)SH; 80 printAnnotation(O, Annot); 81 return; 82 } 83 } 84 85 printInstruction(MI, O); 86 printAnnotation(O, Annot); 87} 88 89 90void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo, 91 raw_ostream &O, 92 const char *Modifier) { 93 assert(Modifier && "Must specify 'cc' or 'reg' as predicate op modifier!"); 94 unsigned Code = MI->getOperand(OpNo).getImm(); 95 if (StringRef(Modifier) == "cc") { 96 switch ((PPC::Predicate)Code) { 97 default: assert(0 && "Invalid predicate"); 98 case PPC::PRED_ALWAYS: return; // Don't print anything for always. 99 case PPC::PRED_LT: O << "lt"; return; 100 case PPC::PRED_LE: O << "le"; return; 101 case PPC::PRED_EQ: O << "eq"; return; 102 case PPC::PRED_GE: O << "ge"; return; 103 case PPC::PRED_GT: O << "gt"; return; 104 case PPC::PRED_NE: O << "ne"; return; 105 case PPC::PRED_UN: O << "un"; return; 106 case PPC::PRED_NU: O << "nu"; return; 107 } 108 } 109 110 assert(StringRef(Modifier) == "reg" && 111 "Need to specify 'cc' or 'reg' as predicate op modifier!"); 112 // Don't print the register for 'always'. 113 if (Code == PPC::PRED_ALWAYS) return; 114 printOperand(MI, OpNo+1, O); 115} 116 117void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo, 118 raw_ostream &O) { 119 char Value = MI->getOperand(OpNo).getImm(); 120 Value = (Value << (32-5)) >> (32-5); 121 O << (int)Value; 122} 123 124void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo, 125 raw_ostream &O) { 126 unsigned char Value = MI->getOperand(OpNo).getImm(); 127 assert(Value <= 31 && "Invalid u5imm argument!"); 128 O << (unsigned int)Value; 129} 130 131void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo, 132 raw_ostream &O) { 133 unsigned char Value = MI->getOperand(OpNo).getImm(); 134 assert(Value <= 63 && "Invalid u6imm argument!"); 135 O << (unsigned int)Value; 136} 137 138void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo, 139 raw_ostream &O) { 140 O << (short)MI->getOperand(OpNo).getImm(); 141} 142 143void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, 144 raw_ostream &O) { 145 O << (unsigned short)MI->getOperand(OpNo).getImm(); 146} 147 148void PPCInstPrinter::printS16X4ImmOperand(const MCInst *MI, unsigned OpNo, 149 raw_ostream &O) { 150 if (MI->getOperand(OpNo).isImm()) 151 O << (short)(MI->getOperand(OpNo).getImm()*4); 152 else 153 printOperand(MI, OpNo, O); 154} 155 156void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo, 157 raw_ostream &O) { 158 if (!MI->getOperand(OpNo).isImm()) 159 return printOperand(MI, OpNo, O); 160 161 // Branches can take an immediate operand. This is used by the branch 162 // selection pass to print $+8, an eight byte displacement from the PC. 163 O << "$+"; 164 printAbsAddrOperand(MI, OpNo, O); 165} 166 167void PPCInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo, 168 raw_ostream &O) { 169 O << (int)MI->getOperand(OpNo).getImm()*4; 170} 171 172 173void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo, 174 raw_ostream &O) { 175 unsigned CCReg = MI->getOperand(OpNo).getReg(); 176 unsigned RegNo; 177 switch (CCReg) { 178 default: assert(0 && "Unknown CR register"); 179 case PPC::CR0: RegNo = 0; break; 180 case PPC::CR1: RegNo = 1; break; 181 case PPC::CR2: RegNo = 2; break; 182 case PPC::CR3: RegNo = 3; break; 183 case PPC::CR4: RegNo = 4; break; 184 case PPC::CR5: RegNo = 5; break; 185 case PPC::CR6: RegNo = 6; break; 186 case PPC::CR7: RegNo = 7; break; 187 } 188 O << (0x80 >> RegNo); 189} 190 191void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo, 192 raw_ostream &O) { 193 printSymbolLo(MI, OpNo, O); 194 O << '('; 195 if (MI->getOperand(OpNo+1).getReg() == PPC::R0) 196 O << "0"; 197 else 198 printOperand(MI, OpNo+1, O); 199 O << ')'; 200} 201 202void PPCInstPrinter::printMemRegImmShifted(const MCInst *MI, unsigned OpNo, 203 raw_ostream &O) { 204 if (MI->getOperand(OpNo).isImm()) 205 printS16X4ImmOperand(MI, OpNo, O); 206 else 207 printSymbolLo(MI, OpNo, O); 208 O << '('; 209 210 if (MI->getOperand(OpNo+1).getReg() == PPC::R0) 211 O << "0"; 212 else 213 printOperand(MI, OpNo+1, O); 214 O << ')'; 215} 216 217 218void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo, 219 raw_ostream &O) { 220 // When used as the base register, r0 reads constant zero rather than 221 // the value contained in the register. For this reason, the darwin 222 // assembler requires that we print r0 as 0 (no r) when used as the base. 223 if (MI->getOperand(OpNo).getReg() == PPC::R0) 224 O << "0"; 225 else 226 printOperand(MI, OpNo, O); 227 O << ", "; 228 printOperand(MI, OpNo+1, O); 229} 230 231 232 233/// stripRegisterPrefix - This method strips the character prefix from a 234/// register name so that only the number is left. Used by for linux asm. 235static const char *stripRegisterPrefix(const char *RegName) { 236 switch (RegName[0]) { 237 case 'r': 238 case 'f': 239 case 'v': return RegName + 1; 240 case 'c': if (RegName[1] == 'r') return RegName + 2; 241 } 242 243 return RegName; 244} 245 246void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 247 raw_ostream &O) { 248 const MCOperand &Op = MI->getOperand(OpNo); 249 if (Op.isReg()) { 250 const char *RegName = getRegisterName(Op.getReg()); 251 // The linux and AIX assembler does not take register prefixes. 252 if (!isDarwinSyntax()) 253 RegName = stripRegisterPrefix(RegName); 254 255 O << RegName; 256 return; 257 } 258 259 if (Op.isImm()) { 260 O << Op.getImm(); 261 return; 262 } 263 264 assert(Op.isExpr() && "unknown operand kind in printOperand"); 265 O << *Op.getExpr(); 266} 267 268void PPCInstPrinter::printSymbolLo(const MCInst *MI, unsigned OpNo, 269 raw_ostream &O) { 270 if (MI->getOperand(OpNo).isImm()) 271 return printS16ImmOperand(MI, OpNo, O); 272 273 // FIXME: This is a terrible hack because we can't encode lo16() as an operand 274 // flag of a subtraction. See the FIXME in GetSymbolRef in PPCMCInstLower. 275 if (MI->getOperand(OpNo).isExpr() && 276 isa<MCBinaryExpr>(MI->getOperand(OpNo).getExpr())) { 277 O << "lo16("; 278 printOperand(MI, OpNo, O); 279 O << ')'; 280 } else { 281 printOperand(MI, OpNo, O); 282 } 283} 284 285void PPCInstPrinter::printSymbolHi(const MCInst *MI, unsigned OpNo, 286 raw_ostream &O) { 287 if (MI->getOperand(OpNo).isImm()) 288 return printS16ImmOperand(MI, OpNo, O); 289 290 // FIXME: This is a terrible hack because we can't encode lo16() as an operand 291 // flag of a subtraction. See the FIXME in GetSymbolRef in PPCMCInstLower. 292 if (MI->getOperand(OpNo).isExpr() && 293 isa<MCBinaryExpr>(MI->getOperand(OpNo).getExpr())) { 294 O << "ha16("; 295 printOperand(MI, OpNo, O); 296 O << ')'; 297 } else { 298 printOperand(MI, OpNo, O); 299 } 300} 301 302 303