176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * modified 476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * by Steve M. Gehlbach <steve@kesa.com> 576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Originally from linux/drivers/video/vga16.c by 776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz> 876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Copyright 1999 Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz> 976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm 1076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Based on VESA framebuffer (c) 1998 Gerd Knorr <kraxel@goldbach.in-berlin.de> 1176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 1276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 1376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#ifndef VGA_H_INCL 1576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VGA_H_INCL 1 1676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman//#include <cpu/p5/io.h> 1876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define u8 unsigned char 2076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define u16 unsigned short 2176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define u32 unsigned int 2276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define __u32 u32 2376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VERROR -1 2576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CHAR_HEIGHT 16 2676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define LINES 25 2776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define COLS 80 2876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman// macros for writing to vga regs 3076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define write_crtc(data,addr) outb(addr,CRT_IC); outb(data,CRT_DC) 3176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define write_att(data,addr) inb(IS1_RC); inb(0x80); outb(addr,ATT_IW); inb(0x80); outb(data,ATT_IW); inb(0x80) 3276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define write_seq(data,addr) outb(addr,SEQ_I); outb(data,SEQ_D) 3376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define write_gra(data,addr) outb(addr,GRA_I); outb(data,GRA_D) 3476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanu8 read_seq_b(u16 addr); 3576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanu8 read_gra_b(u16 addr); 3676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanu8 read_crtc_b(u16 addr); 3776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanu8 read_att_b(u16 addr); 3876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 3976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#ifdef VGA_HARDWARE_FIXUP 4176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanvoid vga_hardware_fixup(void); 4276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#else 4376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define vga_hardware_fixup() do{} while(0) 4476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#endif 4576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 4676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */ 4776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */ 4876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SYNC_EXT 4 /* external sync */ 4976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SYNC_COMP_HIGH_ACT 8 /* composite sync high active */ 5076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SYNC_BROADCAST 16 /* broadcast video timings */ 5176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* vtotal = 144d/288n/576i => PAL */ 5276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* vtotal = 121d/242n/484i => NTSC */ 5376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SYNC_ON_GREEN 32 /* sync on green */ 5576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 5676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VMODE_NONINTERLACED 0 /* non interlaced */ 5776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VMODE_INTERLACED 1 /* interlaced */ 5876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VMODE_DOUBLE 2 /* double scan */ 5976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VMODE_MASK 255 6076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VMODE_YWRAP 256 /* ywrap instead of panning */ 6276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */ 6376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VMODE_CONUPDATE 512 /* don't update x/yoffset */ 6476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 6576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* VGA data register ports */ 6676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */ 6776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */ 6876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ATT_R 0x3C1 /* Attribute Controller Data Read Register */ 6976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GRA_D 0x3CF /* Graphics Controller Data Register */ 7076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SEQ_D 0x3C5 /* Sequencer Data Register */ 7176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define MIS_R 0x3CC // Misc Output Read Register 7376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define MIS_W 0x3C2 // Misc Output Write Register 7476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 7576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define IS1_RC 0x3DA /* Input Status Register 1 - color emulation */ 7676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */ 7776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PEL_D 0x3C9 /* PEL Data Register */ 7876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PEL_MSK 0x3C6 /* PEL mask register */ 7976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* EGA-specific registers */ 8176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GRA_E0 0x3CC /* Graphics enable processor 0 */ 8276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GRA_E1 0x3CA /* Graphics enable processor 1 */ 8376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 8576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* VGA index register ports */ 8676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRT_IC 0x3D4 /* CRT Controller Index - color emulation */ 8776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */ 8876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */ 8976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GRA_I 0x3CE /* Graphics Controller Index */ 9076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SEQ_I 0x3C4 /* Sequencer Index */ 9176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PEL_IW 0x3C8 /* PEL Write Index */ 9276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define PEL_IR 0x3C7 /* PEL Read Index */ 9376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 9476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* standard VGA indexes max counts */ 9576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_C 25 /* 25 CRT Controller Registers sequentially set*/ 9676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman // the remainder are not in the par array 9776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ATT_C 21 /* 21 Attribute Controller Registers */ 9876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GRA_C 9 /* 9 Graphics Controller Registers */ 9976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SEQ_C 5 /* 5 Sequencer Registers */ 10076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define MIS_C 1 /* 1 Misc Output Register */ 10176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 10276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_H_TOTAL 0 10376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_H_DISP 1 10476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_H_BLANK_START 2 10576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_H_BLANK_END 3 10676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_H_SYNC_START 4 10776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_H_SYNC_END 5 10876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_V_TOTAL 6 10976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_OVERFLOW 7 11076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_PRESET_ROW 8 11176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_MAX_SCAN 9 11276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_CURSOR_START 0x0A 11376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_CURSOR_END 0x0B 11476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_START_HI 0x0C 11576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_START_LO 0x0D 11676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_CURSOR_HI 0x0E 11776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_CURSOR_LO 0x0F 11876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_V_SYNC_START 0x10 11976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_V_SYNC_END 0x11 12076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_V_DISP_END 0x12 12176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_OFFSET 0x13 12276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_UNDERLINE 0x14 12376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_V_BLANK_START 0x15 12476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_V_BLANK_END 0x16 12576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_MODE 0x17 12676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define CRTC_LINE_COMPARE 0x18 12776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 12876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ATC_MODE 0x10 12976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ATC_OVERSCAN 0x11 13076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ATC_PLANE_ENABLE 0x12 13176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ATC_PEL 0x13 13276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ATC_COLOR_PAGE 0x14 13376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SEQ_CLOCK_MODE 0x01 13576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SEQ_PLANE_WRITE 0x02 13676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SEQ_CHARACTER_MAP 0x03 13776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define SEQ_MEMORY_MODE 0x04 13876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 13976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GDC_SR_VALUE 0x00 14076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GDC_SR_ENABLE 0x01 14176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GDC_COMPARE_VALUE 0x02 14276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GDC_DATA_ROTATE 0x03 14376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GDC_PLANE_READ 0x04 14476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GDC_MODE 0x05 14576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GDC_MISC 0x06 14676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GDC_COMPARE_MASK 0x07 14776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define GDC_BIT_MASK 0x08 14876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 14976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman// text attributes 15076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VGA_ATTR_CLR_RED 0x4 15176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VGA_ATTR_CLR_GRN 0x2 15276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VGA_ATTR_CLR_BLU 0x1 15376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VGA_ATTR_CLR_YEL (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN) 15476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VGA_ATTR_CLR_CYN (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU) 15576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VGA_ATTR_CLR_MAG (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED) 15676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VGA_ATTR_CLR_BLK 0 15776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VGA_ATTR_CLR_WHT (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU) 15876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VGA_ATTR_BNK 0x80 15976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define VGA_ATTR_ITN 0x08 16076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 16176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 16276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * vga register parameters 16376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * these are copied to the 16476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * registers. 16576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 16676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 16776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct vga_par { 16876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 crtc[CRTC_C]; 16976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 atc[ATT_C]; 17076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 gdc[GRA_C]; 17176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 seq[SEQ_C]; 17276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 misc; // the misc register, MIS_W 17376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 vss; 17476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 17576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 17776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* Interpretation of offset for color fields: All offsets are from the right, 17876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you 17976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * can use the offset as right argument to <<). A pixel afterwards is a bit 18076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * stream and is written to video memory as that unmodified. This implies 18176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * big-endian byte order if bits_per_pixel is greater than 8. 18276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 18376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct fb_bitfield { 18476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 offset; /* beginning of bitfield */ 18576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 length; /* length of bitfield */ 18676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 msb_right; /* != 0 : Most significant bit is */ 18776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* right */ 18876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 18976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct screeninfo { 19176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 xres; /* visible resolution */ 19276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 yres; 19376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 xres_virtual; /* virtual resolution */ 19476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 yres_virtual; 19576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 xoffset; /* offset from virtual to visible */ 19676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 yoffset; /* resolution */ 19776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 bits_per_pixel; /* guess what */ 19976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 grayscale; /* != 0 Graylevels instead of colors */ 20076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct fb_bitfield red; /* bitfield in fb mem if true color, */ 20276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct fb_bitfield green; /* else only length is significant */ 20376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct fb_bitfield blue; 20476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct fb_bitfield transp; /* transparency */ 20576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 nonstd; /* != 0 Non standard pixel format */ 20776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 activate; /* see FB_ACTIVATE_* */ 20976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 21076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 height; /* height of picture in mm */ 21176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 width; /* width of picture in mm */ 21276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 21376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 accel_flags; /* acceleration flags (hints) */ 21476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 21576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman /* Timing: All values in pixclocks, except pixclock (of course) */ 21676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 pixclock; /* pixel clock in ps (pico seconds) */ 21776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 left_margin; /* time from sync to picture */ 21876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 right_margin; /* time from picture to sync */ 21976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 upper_margin; /* time from sync to picture */ 22076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 lower_margin; 22176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 hsync_len; /* length of horizontal sync */ 22276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 vsync_len; /* length of vertical sync */ 22376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 sync; /* sync polarity */ 22476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 vmode; /* interlaced etc */ 22576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman __u32 reserved[6]; /* Reserved for future compatibility */ 22676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 22776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#endif 229