1/* 2 This software is available to you under a choice of one of two 3 licenses. You may choose to be licensed under the terms of the GNU 4 General Public License (GPL) Version 2, available at 5 <http://www.fsf.org/copyleft/gpl.html>, or the OpenIB.org BSD 6 license, available in the LICENSE.TXT file accompanying this 7 software. These details are also available at 8 <http://openib.org/license.html>. 9 10 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 11 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 12 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 13 NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 14 BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 15 ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 16 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 17 SOFTWARE. 18 19 Copyright (c) 2004 Mellanox Technologies Ltd. All rights reserved. 20*/ 21 22FILE_LICENCE ( GPL2_ONLY ); 23 24/*** 25 *** This file was generated at "Mon Apr 16 23:22:02 2007" 26 *** by: 27 *** % csp_bf -copyright=/mswg/misc/license-header.txt -prefix hermonprm_ -bits -fixnames MT25408_PRM.csp 28 ***/ 29 30#ifndef H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H 31#define H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H 32 33/* UD Address Vector */ 34 35struct hermonprm_ud_address_vector_st { /* Little Endian */ 36 pseudo_bit_t pd[0x00018]; /* Protection Domain */ 37 pseudo_bit_t port_number[0x00002]; /* Port number 38 1 - Port 1 39 2 - Port 2 40 other - reserved */ 41 pseudo_bit_t reserved0[0x00005]; 42 pseudo_bit_t fl[0x00001]; /* force loopback */ 43/* -------------- */ 44 pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ 45 pseudo_bit_t my_lid_path_bits[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ 46 pseudo_bit_t g[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ 47 pseudo_bit_t reserved1[0x00008]; 48/* -------------- */ 49 pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ 50 pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control. 51 0 - 4X injection rate 52 1 - 1X injection rate 53 other - reserved 54 */ 55 pseudo_bit_t reserved2[0x00004]; 56 pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table 57 mgid_index = (port_number-1) * 2^log_max_gid + gid_index 58 Where: 59 1. log_max_gid is taken from QUERY_DEV_CAP command 60 2. gid_index is the index to the GID table */ 61 pseudo_bit_t reserved3[0x00009]; 62/* -------------- */ 63 pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ 64 pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ 65 pseudo_bit_t sl[0x00004]; /* InfiniBand Service Level (SL) */ 66/* -------------- */ 67 pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ 68/* -------------- */ 69 pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ 70/* -------------- */ 71 pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ 72/* -------------- */ 73 pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] if G bit is set. Must be set to 0x2 if G bit is cleared. */ 74/* -------------- */ 75}; 76 77/* Send doorbell */ 78 79struct hermonprm_send_doorbell_st { /* Little Endian */ 80 pseudo_bit_t nopcode[0x00005]; /* Opcode of descriptor to be executed */ 81 pseudo_bit_t f[0x00001]; /* Fence bit. If set, descriptor is fenced */ 82 pseudo_bit_t reserved0[0x00002]; 83 pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted to the QP since its creation excluding the newly posted WQEs in this doorbell. Should be zero for the first doorbell on the QP */ 84 pseudo_bit_t wqe_cnt[0x00008]; /* Number of WQEs posted with this doorbell. Must be grater then zero. */ 85/* -------------- */ 86 pseudo_bit_t nds[0x00006]; /* Next descriptor size (in 16-byte chunks) */ 87 pseudo_bit_t reserved1[0x00002]; 88 pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ 89/* -------------- */ 90}; 91 92/* Send wqe segment data inline */ 93 94struct hermonprm_wqe_segment_data_inline_st { /* Little Endian */ 95 pseudo_bit_t byte_count[0x0000a]; /* Not including padding for 16Byte chunks */ 96 pseudo_bit_t reserved0[0x00015]; 97 pseudo_bit_t always1[0x00001]; 98/* -------------- */ 99 pseudo_bit_t data[0x00018]; /* Data may be more this segment size - in 16Byte chunks */ 100 pseudo_bit_t reserved1[0x00008]; 101/* -------------- */ 102 pseudo_bit_t reserved2[0x00040]; 103/* -------------- */ 104}; 105 106/* Send wqe segment data ptr */ 107 108struct hermonprm_wqe_segment_data_ptr_st { /* Little Endian */ 109 pseudo_bit_t byte_count[0x0001f]; 110 pseudo_bit_t always0[0x00001]; 111/* -------------- */ 112 pseudo_bit_t l_key[0x00020]; 113/* -------------- */ 114 pseudo_bit_t local_address_h[0x00020]; 115/* -------------- */ 116 pseudo_bit_t local_address_l[0x00020]; 117/* -------------- */ 118}; 119 120/* Send wqe segment rd */ 121 122struct hermonprm_local_invalidate_segment_st { /* Little Endian */ 123 pseudo_bit_t reserved0[0x00040]; 124/* -------------- */ 125 pseudo_bit_t mem_key[0x00018]; 126 pseudo_bit_t reserved1[0x00008]; 127/* -------------- */ 128 pseudo_bit_t reserved2[0x000a0]; 129/* -------------- */ 130}; 131 132/* Fast_Registration_Segment ####michal - doesn't match PRM (fields were added, see below) new table size in bytes - 0x30 */ 133 134struct hermonprm_fast_registration_segment_st { /* Little Endian */ 135 pseudo_bit_t reserved0[0x0001b]; 136 pseudo_bit_t lr[0x00001]; /* If set - Local Read access will be enabled */ 137 pseudo_bit_t lw[0x00001]; /* If set - Local Write access will be enabled */ 138 pseudo_bit_t rr[0x00001]; /* If set - Remote Read access will be enabled */ 139 pseudo_bit_t rw[0x00001]; /* If set - Remote Write access will be enabled */ 140 pseudo_bit_t a[0x00001]; /* If set - Remote Atomic access will be enabled */ 141/* -------------- */ 142 pseudo_bit_t pbl_ptr_63_32[0x00020];/* Physical address pointer [63:32] to the physical buffer list ### michal - this field is replaced with mem_key .32 */ 143/* -------------- */ 144 pseudo_bit_t mem_key[0x00020]; /* Memory Key on which the fast registration is executed on. ###michal-this field is replaced with pbl_ptr_63_32 */ 145/* -------------- */ 146 pseudo_bit_t page_size[0x00005]; /* Page size used for the region. Actual size is [4K]*2^Page_size bytes. 147 page_size should be less than 20. ###michal - field doesn't exsist (see replacement above) */ 148 pseudo_bit_t reserved1[0x00002]; 149 pseudo_bit_t zb[0x00001]; /* Zero Based Region ###michal - field doesn't exsist (see replacement above) */ 150 pseudo_bit_t pbl_ptr_31_8[0x00018]; /* Physical address pointer [31:8] to the physical buffer list ###michal - field doesn't exsist (see replacement above) */ 151/* -------------- */ 152 pseudo_bit_t start_address_h[0x00020];/* Start Address[63:32] - Virtual Address where this region starts */ 153/* -------------- */ 154 pseudo_bit_t start_address_l[0x00020];/* Start Address[31:0] - Virtual Address where this region starts */ 155/* -------------- */ 156 pseudo_bit_t reg_len_h[0x00020]; /* Region Length[63:32] */ 157/* -------------- */ 158 pseudo_bit_t reg_len_l[0x00020]; /* Region Length[31:0] */ 159/* -------------- */ 160}; 161 162/* Send wqe segment atomic */ 163 164struct hermonprm_wqe_segment_atomic_st { /* Little Endian */ 165 pseudo_bit_t swap_add_h[0x00020]; 166/* -------------- */ 167 pseudo_bit_t swap_add_l[0x00020]; 168/* -------------- */ 169 pseudo_bit_t compare_h[0x00020]; 170/* -------------- */ 171 pseudo_bit_t compare_l[0x00020]; 172/* -------------- */ 173}; 174 175/* Send wqe segment remote address */ 176 177struct hermonprm_wqe_segment_remote_address_st { /* Little Endian */ 178 pseudo_bit_t remote_virt_addr_h[0x00020]; 179/* -------------- */ 180 pseudo_bit_t remote_virt_addr_l[0x00020]; 181/* -------------- */ 182 pseudo_bit_t rkey[0x00020]; 183/* -------------- */ 184 pseudo_bit_t reserved0[0x00020]; 185/* -------------- */ 186}; 187 188/* end wqe segment bind */ 189 190struct hermonprm_wqe_segment_bind_st { /* Little Endian */ 191 pseudo_bit_t reserved0[0x0001d]; 192 pseudo_bit_t rr[0x00001]; /* If set, Remote Read Enable for bound window. */ 193 pseudo_bit_t rw[0x00001]; /* If set, Remote Write Enable for bound window. 194 */ 195 pseudo_bit_t a[0x00001]; /* If set, Atomic Enable for bound window. */ 196/* -------------- */ 197 pseudo_bit_t reserved1[0x0001e]; 198 pseudo_bit_t zb[0x00001]; /* If set, Window is Zero Based. */ 199 pseudo_bit_t type[0x00001]; /* Window type. 200 0 - Type one window 201 1 - Type two window 202 */ 203/* -------------- */ 204 pseudo_bit_t new_rkey[0x00020]; /* The new RKey of window to bind */ 205/* -------------- */ 206 pseudo_bit_t region_lkey[0x00020]; /* Local key of region, which window will be bound to */ 207/* -------------- */ 208 pseudo_bit_t start_address_h[0x00020]; 209/* -------------- */ 210 pseudo_bit_t start_address_l[0x00020]; 211/* -------------- */ 212 pseudo_bit_t length_h[0x00020]; 213/* -------------- */ 214 pseudo_bit_t length_l[0x00020]; 215/* -------------- */ 216}; 217 218/* Send wqe segment ud */ 219 220struct hermonprm_wqe_segment_ud_st { /* Little Endian */ 221 struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ 222/* -------------- */ 223 pseudo_bit_t destination_qp[0x00018]; 224 pseudo_bit_t reserved0[0x00008]; 225/* -------------- */ 226 pseudo_bit_t q_key[0x00020]; 227/* -------------- */ 228 pseudo_bit_t reserved1[0x00040]; 229/* -------------- */ 230}; 231 232/* Send wqe segment rd */ 233 234struct hermonprm_wqe_segment_rd_st { /* Little Endian */ 235 pseudo_bit_t destination_qp[0x00018]; 236 pseudo_bit_t reserved0[0x00008]; 237/* -------------- */ 238 pseudo_bit_t q_key[0x00020]; 239/* -------------- */ 240 pseudo_bit_t reserved1[0x00040]; 241/* -------------- */ 242}; 243 244/* Send wqe segment ctrl */ 245 246struct hermonprm_wqe_segment_ctrl_send_st { /* Little Endian */ 247 pseudo_bit_t opcode[0x00005]; 248 pseudo_bit_t reserved0[0x0001a]; 249 pseudo_bit_t owner[0x00001]; 250/* -------------- */ 251 pseudo_bit_t ds[0x00006]; /* descriptor (wqe) size in 16bytes chunk */ 252 pseudo_bit_t f[0x00001]; /* fence */ 253 pseudo_bit_t reserved1[0x00019]; 254/* -------------- */ 255 pseudo_bit_t fl[0x00001]; /* Force LoopBack */ 256 pseudo_bit_t s[0x00001]; /* Remote Solicited Event */ 257 pseudo_bit_t c[0x00002]; /* completion required: 0b00 - no 0b11 - yes */ 258 pseudo_bit_t ip[0x00001]; /* When set, InfiniHost III Ex will calculate the IP checksum of the IP header that is present immediately after the IPoverIB encapsulation header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first IP header following the IPoverIB encapsulation header. Not Valid for IPv6 packets */ 259 pseudo_bit_t tcp_udp[0x00001]; /* When set, InfiniHost III Ex will calculate the TCP/UDP checksum of the packet that is present immediately after the IP header. In the case of multiple headers (encapsulation), InfiniHost III Ex will calculate the checksum only for the first TCP header following the IP header. This bit may be set only if the entire TCP/UDP segment is present in one IB packet */ 260 pseudo_bit_t reserved2[0x00001]; 261 pseudo_bit_t so[0x00001]; /* Strong Ordering - when set, the WQE will be executed only after all previous WQEs have been executed. Can be set for RC WQEs only. This bit must be set in type two BIND, Fast Registration and Local invalidate operations. */ 262 pseudo_bit_t src_remote_buf[0x00018]; 263/* -------------- */ 264 pseudo_bit_t immediate[0x00020]; /* If the OpCode encodes an operation with Immediate (RDMA-write/SEND), This field will hold the Immediate data to be sent. If the OpCode encodes send and invalidate operations, this field holds the Invalidation key to be inserted into the packet; otherwise, this field is reserved. */ 265/* -------------- */ 266}; 267 268/* Address Path # ###michal - match to PRM */ 269 270struct hermonprm_address_path_st { /* Little Endian */ 271 pseudo_bit_t pkey_index[0x00007]; /* PKey table index */ 272 pseudo_bit_t reserved0[0x00016]; 273 pseudo_bit_t sv[0x00001]; /* Service VLAN on QP */ 274 pseudo_bit_t cv[0x00001]; /* Customer VLAN in QP */ 275 pseudo_bit_t fl[0x00001]; /* Force LoopBack */ 276/* -------------- */ 277 pseudo_bit_t rlid[0x00010]; /* Remote (Destination) LID */ 278 pseudo_bit_t my_lid_smac_idx[0x00007];/* Source LID - the lower 7 bits (upper bits are taken from PortInfo) */ 279 pseudo_bit_t grh_ip[0x00001]; /* Global address enable - if set, GRH will be formed for packet header */ 280 pseudo_bit_t reserved1[0x00008]; 281/* -------------- */ 282 pseudo_bit_t hop_limit[0x00008]; /* IPv6 hop limit */ 283 pseudo_bit_t max_stat_rate[0x00004];/* Maximum static rate control. 284 0 - 100% injection rate 285 1 - 25% injection rate 286 2 - 12.5% injection rate 287 3 - 50% injection rate 288 7: 2.5 Gb/s. 289 8: 10 Gb/s. 290 9: 30 Gb/s. 291 10: 5 Gb/s. 292 11: 20 Gb/s. 293 12: 40 Gb/s. 294 13: 60 Gb/s. 295 14: 80 Gb/s. 296 15: 120 Gb/s. */ 297 pseudo_bit_t reserved2[0x00004]; 298 pseudo_bit_t mgid_index[0x00007]; /* Index to port GID table */ 299 pseudo_bit_t reserved3[0x00004]; 300 pseudo_bit_t ack_timeout[0x00005]; /* Local ACK timeout - Transport timer for activation of retransmission mechanism. Refer to IB spec Vol1 9.7.6.1.3 for further details. 301 The transport timer is set to 4.096us*2^ack_timeout, if ack_timeout is 0 then transport timer is disabled. */ 302/* -------------- */ 303 pseudo_bit_t flow_label[0x00014]; /* IPv6 flow label */ 304 pseudo_bit_t tclass[0x00008]; /* IPv6 TClass */ 305 pseudo_bit_t reserved4[0x00004]; 306/* -------------- */ 307 pseudo_bit_t rgid_127_96[0x00020]; /* Remote GID[127:96] */ 308/* -------------- */ 309 pseudo_bit_t rgid_95_64[0x00020]; /* Remote GID[95:64] */ 310/* -------------- */ 311 pseudo_bit_t rgid_63_32[0x00020]; /* Remote GID[63:32] */ 312/* -------------- */ 313 pseudo_bit_t rgid_31_0[0x00020]; /* Remote GID[31:0] */ 314/* -------------- */ 315 pseudo_bit_t reserved5[0x00008]; 316 pseudo_bit_t sp[0x00001]; /* if set, spoofing protection is enforced on this QP and Ethertype headers are restricted */ 317 pseudo_bit_t reserved6[0x00002]; 318 pseudo_bit_t fvl[0x00001]; /* force VLAN */ 319 pseudo_bit_t fsip[0x00001]; /* force source IP */ 320 pseudo_bit_t fsm[0x00001]; /* force source MAC */ 321 pseudo_bit_t reserved7[0x0000a]; 322 pseudo_bit_t sched_queue[0x00008]; 323/* -------------- */ 324 pseudo_bit_t dmac_47_32[0x00010]; 325 pseudo_bit_t vlan_index[0x00007]; 326 pseudo_bit_t reserved8[0x00001]; 327 pseudo_bit_t counter_index[0x00008];/* Index to a table of counters that counts egress packets and bytes, 0xFF not valid */ 328/* -------------- */ 329 pseudo_bit_t dmac_31_0[0x00020]; 330/* -------------- */ 331}; 332 333/* HCA Command Register (HCR) #### michal - match PRM */ 334 335struct hermonprm_hca_command_register_st { /* Little Endian */ 336 pseudo_bit_t in_param_h[0x00020]; /* Input Parameter: parameter[63:32] or pointer[63:32] to input mailbox (see command description) */ 337/* -------------- */ 338 pseudo_bit_t in_param_l[0x00020]; /* Input Parameter: parameter[31:0] or pointer[31:0] to input mailbox (see command description) */ 339/* -------------- */ 340 pseudo_bit_t input_modifier[0x00020];/* Input Parameter Modifier */ 341/* -------------- */ 342 pseudo_bit_t out_param_h[0x00020]; /* Output Parameter: parameter[63:32] or pointer[63:32] to output mailbox (see command description) */ 343/* -------------- */ 344 pseudo_bit_t out_param_l[0x00020]; /* Output Parameter: parameter[31:0] or pointer[31:0] to output mailbox (see command description) */ 345/* -------------- */ 346 pseudo_bit_t reserved0[0x00010]; 347 pseudo_bit_t token[0x00010]; /* Software assigned token to the command, to uniquely identify it. The token is returned to the software in the EQE reported. */ 348/* -------------- */ 349 pseudo_bit_t opcode[0x0000c]; /* Command opcode */ 350 pseudo_bit_t opcode_modifier[0x00004];/* Opcode Modifier, see specific description for each command. */ 351 pseudo_bit_t reserved1[0x00005]; 352 pseudo_bit_t t[0x00001]; /* Toggle */ 353 pseudo_bit_t e[0x00001]; /* Event Request 354 0 - Don't report event (software will poll the GO bit) 355 1 - Report event to EQ when the command completes */ 356 pseudo_bit_t go[0x00001]; /* Go (0=Software ownership for the HCR, 1=Hardware ownership for the HCR) 357 Software can write to the HCR only if Go bit is cleared. 358 Software must set the Go bit to trigger the HW to execute the command. Software must not write to this register value other than 1 for the Go bit. */ 359 pseudo_bit_t status[0x00008]; /* Command execution status report. Valid only if command interface in under SW ownership (Go bit is cleared) 360 0 - command completed without error. If different than zero, command execution completed with error. Syndrom encoding is depended on command executed and is defined for each command */ 361/* -------------- */ 362}; 363 364/* CQ Doorbell */ 365 366struct hermonprm_cq_cmd_doorbell_st { /* Little Endian */ 367 pseudo_bit_t cqn[0x00018]; /* CQ number accessed */ 368 pseudo_bit_t cmd[0x00003]; /* Command to be executed on CQ 369 0x0 - Reserved 370 0x1 - Request notification for next Solicited completion event. CQ_param specifies the current CQ Consumer Counter. 371 0x2 - Request notification for next Solicited or Unsolicited completion event. CQ_param specifies the current CQ Consumer Counter. 372 0x3 - Request notification for multiple completions (Arm-N). CQ_param specifies the value of the CQ Counter that when reached by HW (i.e. HW generates a CQE into this Counter) Event will be generated 373 Other - Reserved */ 374 pseudo_bit_t reserved0[0x00001]; 375 pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - This field should be incremented upon receiving completion notification of the respective CQ. 376 This transition is done by ringing Request notification for next Solicited, Request notification for next Solicited or Unsolicited 377 completion or Request notification for multiple completions doorbells after receiving completion notification. 378 This field is initialized to Zero */ 379 pseudo_bit_t reserved1[0x00002]; 380/* -------------- */ 381 pseudo_bit_t cq_param[0x00020]; /* parameter to be used by CQ command */ 382/* -------------- */ 383}; 384 385/* RD-send doorbell */ 386 387struct hermonprm_rd_send_doorbell_st { /* Little Endian */ 388 pseudo_bit_t reserved0[0x00008]; 389 pseudo_bit_t een[0x00018]; /* End-to-end context number (reliable datagram) 390 Must be zero for Nop and Bind operations */ 391/* -------------- */ 392 pseudo_bit_t reserved1[0x00008]; 393 pseudo_bit_t qpn[0x00018]; /* QP number this doorbell is rung on */ 394/* -------------- */ 395 struct hermonprm_send_doorbell_st send_doorbell;/* Send Parameters */ 396/* -------------- */ 397}; 398 399/* Multicast Group Member QP #### michal - match PRM */ 400 401struct hermonprm_mgmqp_st { /* Little Endian */ 402 pseudo_bit_t qpn_i[0x00018]; /* QPN_i: QP number which is a member in this multicast group. Valid only if Qi bit is set. Length of the QPN_i list is set in INIT_HCA */ 403 pseudo_bit_t reserved0[0x00006]; 404 pseudo_bit_t blck_lb[0x00001]; /* Block self-loopback messages arriving to this qp */ 405 pseudo_bit_t qi[0x00001]; /* Qi: QPN_i is valid */ 406/* -------------- */ 407}; 408 409/* vsd */ 410 411struct hermonprm_vsd_st { /* Little Endian */ 412 pseudo_bit_t vsd_dw0[0x00020]; 413/* -------------- */ 414 pseudo_bit_t vsd_dw1[0x00020]; 415/* -------------- */ 416 pseudo_bit_t vsd_dw2[0x00020]; 417/* -------------- */ 418 pseudo_bit_t vsd_dw3[0x00020]; 419/* -------------- */ 420 pseudo_bit_t vsd_dw4[0x00020]; 421/* -------------- */ 422 pseudo_bit_t vsd_dw5[0x00020]; 423/* -------------- */ 424 pseudo_bit_t vsd_dw6[0x00020]; 425/* -------------- */ 426 pseudo_bit_t vsd_dw7[0x00020]; 427/* -------------- */ 428 pseudo_bit_t vsd_dw8[0x00020]; 429/* -------------- */ 430 pseudo_bit_t vsd_dw9[0x00020]; 431/* -------------- */ 432 pseudo_bit_t vsd_dw10[0x00020]; 433/* -------------- */ 434 pseudo_bit_t vsd_dw11[0x00020]; 435/* -------------- */ 436 pseudo_bit_t vsd_dw12[0x00020]; 437/* -------------- */ 438 pseudo_bit_t vsd_dw13[0x00020]; 439/* -------------- */ 440 pseudo_bit_t vsd_dw14[0x00020]; 441/* -------------- */ 442 pseudo_bit_t vsd_dw15[0x00020]; 443/* -------------- */ 444 pseudo_bit_t vsd_dw16[0x00020]; 445/* -------------- */ 446 pseudo_bit_t vsd_dw17[0x00020]; 447/* -------------- */ 448 pseudo_bit_t vsd_dw18[0x00020]; 449/* -------------- */ 450 pseudo_bit_t vsd_dw19[0x00020]; 451/* -------------- */ 452 pseudo_bit_t vsd_dw20[0x00020]; 453/* -------------- */ 454 pseudo_bit_t vsd_dw21[0x00020]; 455/* -------------- */ 456 pseudo_bit_t vsd_dw22[0x00020]; 457/* -------------- */ 458 pseudo_bit_t vsd_dw23[0x00020]; 459/* -------------- */ 460 pseudo_bit_t vsd_dw24[0x00020]; 461/* -------------- */ 462 pseudo_bit_t vsd_dw25[0x00020]; 463/* -------------- */ 464 pseudo_bit_t vsd_dw26[0x00020]; 465/* -------------- */ 466 pseudo_bit_t vsd_dw27[0x00020]; 467/* -------------- */ 468 pseudo_bit_t vsd_dw28[0x00020]; 469/* -------------- */ 470 pseudo_bit_t vsd_dw29[0x00020]; 471/* -------------- */ 472 pseudo_bit_t vsd_dw30[0x00020]; 473/* -------------- */ 474 pseudo_bit_t vsd_dw31[0x00020]; 475/* -------------- */ 476 pseudo_bit_t vsd_dw32[0x00020]; 477/* -------------- */ 478 pseudo_bit_t vsd_dw33[0x00020]; 479/* -------------- */ 480 pseudo_bit_t vsd_dw34[0x00020]; 481/* -------------- */ 482 pseudo_bit_t vsd_dw35[0x00020]; 483/* -------------- */ 484 pseudo_bit_t vsd_dw36[0x00020]; 485/* -------------- */ 486 pseudo_bit_t vsd_dw37[0x00020]; 487/* -------------- */ 488 pseudo_bit_t vsd_dw38[0x00020]; 489/* -------------- */ 490 pseudo_bit_t vsd_dw39[0x00020]; 491/* -------------- */ 492 pseudo_bit_t vsd_dw40[0x00020]; 493/* -------------- */ 494 pseudo_bit_t vsd_dw41[0x00020]; 495/* -------------- */ 496 pseudo_bit_t vsd_dw42[0x00020]; 497/* -------------- */ 498 pseudo_bit_t vsd_dw43[0x00020]; 499/* -------------- */ 500 pseudo_bit_t vsd_dw44[0x00020]; 501/* -------------- */ 502 pseudo_bit_t vsd_dw45[0x00020]; 503/* -------------- */ 504 pseudo_bit_t vsd_dw46[0x00020]; 505/* -------------- */ 506 pseudo_bit_t vsd_dw47[0x00020]; 507/* -------------- */ 508 pseudo_bit_t vsd_dw48[0x00020]; 509/* -------------- */ 510 pseudo_bit_t vsd_dw49[0x00020]; 511/* -------------- */ 512 pseudo_bit_t vsd_dw50[0x00020]; 513/* -------------- */ 514 pseudo_bit_t vsd_dw51[0x00020]; 515/* -------------- */ 516 pseudo_bit_t vsd_dw52[0x00020]; 517/* -------------- */ 518 pseudo_bit_t vsd_dw53[0x00020]; 519/* -------------- */ 520 pseudo_bit_t vsd_dw54[0x00020]; 521/* -------------- */ 522 pseudo_bit_t vsd_dw55[0x00020]; 523/* -------------- */ 524}; 525 526/* UAR Parameters */ 527 528struct hermonprm_uar_params_st { /* Little Endian */ 529 pseudo_bit_t reserved0[0x00040]; 530/* -------------- */ 531 pseudo_bit_t uar_page_sz[0x00008]; /* This field defines the size of each UAR page. 532 Size of UAR Page is 4KB*2^UAR_Page_Size */ 533 pseudo_bit_t log_max_uars[0x00004]; /* Number of UARs supported is 2^log_max_UARs */ 534 pseudo_bit_t reserved1[0x00014]; 535/* -------------- */ 536 pseudo_bit_t reserved2[0x000a0]; 537/* -------------- */ 538}; 539 540/* Translation and Protection Tables Parameters */ 541 542struct hermonprm_tptparams_st { /* Little Endian */ 543 pseudo_bit_t dmpt_base_adr_h[0x00020];/* dMPT - Memory Protection Table base physical address [63:32]. 544 Entry size is 64 bytes. 545 Table must be aligned to its size. 546 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 547/* -------------- */ 548 pseudo_bit_t dmpt_base_adr_l[0x00020];/* dMPT - Memory Protection Table base physical address [31:0]. 549 Entry size is 64 bytes. 550 Table must be aligned to its size. 551 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 552/* -------------- */ 553 pseudo_bit_t log_dmpt_sz[0x00006]; /* Log (base 2) of the number of region/windows entries in the dMPT table. */ 554 pseudo_bit_t reserved0[0x00002]; 555 pseudo_bit_t pfto[0x00005]; /* Page Fault RNR Timeout - 556 The field returned in RNR Naks generated when a page fault is detected. 557 It has no effect when on-demand-paging is not used. */ 558 pseudo_bit_t reserved1[0x00013]; 559/* -------------- */ 560 pseudo_bit_t reserved2[0x00020]; 561/* -------------- */ 562 pseudo_bit_t mtt_base_addr_h[0x00020];/* MTT - Memory Translation table base physical address [63:32]. 563 Table must be aligned to its size. 564 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 565/* -------------- */ 566 pseudo_bit_t mtt_base_addr_l[0x00020];/* MTT - Memory Translation table base physical address [31:0]. 567 Table must be aligned to its size. 568 Address may be set to 0xFFFFFFFF if address translation and protection is not supported. */ 569/* -------------- */ 570 pseudo_bit_t cmpt_base_adr_h[0x00020];/* cMPT - Memory Protection Table base physical address [63:32]. 571 Entry size is 64 bytes. 572 Table must be aligned to its size. */ 573/* -------------- */ 574 pseudo_bit_t cmpt_base_adr_l[0x00020];/* cMPT - Memory Protection Table base physical address [31:0]. 575 Entry size is 64 bytes. 576 Table must be aligned to its size. */ 577/* -------------- */ 578}; 579 580/* Multicast Support Parameters #### michal - match PRM */ 581 582struct hermonprm_multicastparam_st { /* Little Endian */ 583 pseudo_bit_t mc_base_addr_h[0x00020];/* Base Address of the Multicast Table [63:32]. 584 The base address must be aligned to the entry size. 585 Address may be set to 0xFFFFFFFF if multicast is not supported. */ 586/* -------------- */ 587 pseudo_bit_t mc_base_addr_l[0x00020];/* Base Address of the Multicast Table [31:0]. 588 The base address must be aligned to the entry size. 589 Address may be set to 0xFFFFFFFF if multicast is not supported. */ 590/* -------------- */ 591 pseudo_bit_t reserved0[0x00040]; 592/* -------------- */ 593 pseudo_bit_t log_mc_table_entry_sz[0x00005];/* Log2 of the Size of multicast group member (MGM) entry. 594 Must be greater than 5 (to allow CTRL and GID sections). 595 That implies the number of QPs per MC table entry. */ 596 pseudo_bit_t reserved1[0x0000b]; 597 pseudo_bit_t reserved2[0x00010]; 598/* -------------- */ 599 pseudo_bit_t log_mc_table_hash_sz[0x00005];/* Number of entries in multicast DGID hash table (must be power of 2) 600 INIT_HCA - the required number of entries 601 QUERY_HCA - the actual number of entries assigned by firmware (will be less than or equal to the amount required in INIT_HCA) */ 602 pseudo_bit_t reserved3[0x0001b]; 603/* -------------- */ 604 pseudo_bit_t log_mc_table_sz[0x00005];/* Log2 of the overall number of MC entries in the MCG table (includes both hash and auxiliary tables) */ 605 pseudo_bit_t reserved4[0x00013]; 606 pseudo_bit_t mc_hash_fn[0x00003]; /* Multicast hash function 607 0 - Default hash function 608 other - reserved */ 609 pseudo_bit_t reserved5[0x00005]; 610/* -------------- */ 611 pseudo_bit_t reserved6[0x00020]; 612/* -------------- */ 613}; 614 615/* QPC/EEC/CQC/EQC/RDB Parameters #### michal - doesn't match PRM (field name are differs. see below) */ 616 617struct hermonprm_qpcbaseaddr_st { /* Little Endian */ 618 pseudo_bit_t reserved0[0x00080]; 619/* -------------- */ 620 pseudo_bit_t qpc_base_addr_h[0x00020];/* QPC Base Address [63:32] 621 Table must be aligned on its size */ 622/* -------------- */ 623 pseudo_bit_t log_num_of_qp[0x00005];/* Log base 2 of number of supported QPs */ 624 pseudo_bit_t qpc_base_addr_l[0x0001b];/* QPC Base Address [31:7] 625 Table must be aligned on its size */ 626/* -------------- */ 627 pseudo_bit_t reserved1[0x00040]; 628/* -------------- */ 629 pseudo_bit_t reserved2[0x00040]; 630/* -------------- */ 631 pseudo_bit_t srqc_base_addr_h[0x00020];/* SRQ Context Base Address [63:32] 632 Table must be aligned on its size 633 Address may be set to 0xFFFFFFFF if SRQ is not supported. */ 634/* -------------- */ 635 pseudo_bit_t log_num_of_srq[0x00005];/* Log base 2 of number of supported SRQs. */ 636 pseudo_bit_t srqc_base_addr_l[0x0001b];/* SRQ Context Base Address [31:5] 637 Table must be aligned on its size 638 Address may be set to 0xFFFFFFFF if SRQ is not supported. */ 639/* -------------- */ 640 pseudo_bit_t cqc_base_addr_h[0x00020];/* CQC Base Address [63:32] 641 Table must be aligned on its size */ 642/* -------------- */ 643 pseudo_bit_t log_num_of_cq[0x00005];/* Log base 2 of number of supported CQs. */ 644 pseudo_bit_t cqc_base_addr_l[0x0001b];/* CQC Base Address [31:6] 645 Table must be aligned on its size */ 646/* -------------- */ 647 pseudo_bit_t reserved3[0x00040]; 648/* -------------- */ 649 pseudo_bit_t altc_base_addr_h[0x00020];/* AltC Base Address (altc_base_addr_h) [63:32] 650 Table has same number of entries as QPC table. 651 Table must be aligned to entry size. */ 652/* -------------- */ 653 pseudo_bit_t altc_base_addr_l[0x00020];/* AltC Base Address (altc_base_addr_l) [31:0] 654 Table has same number of entries as QPC table. 655 Table must be aligned to entry size. */ 656/* -------------- */ 657 pseudo_bit_t reserved4[0x00040]; 658/* -------------- */ 659 pseudo_bit_t auxc_base_addr_h[0x00020]; 660/* -------------- */ 661 pseudo_bit_t auxc_base_addr_l[0x00020]; 662/* -------------- */ 663 pseudo_bit_t reserved5[0x00040]; 664/* -------------- */ 665 pseudo_bit_t eqc_base_addr_h[0x00020];/* EQC Base Address [63:32] 666 Address may be set to 0xFFFFFFFF if EQs are not supported. 667 Table must be aligned to entry size. */ 668/* -------------- */ 669 pseudo_bit_t log_num_of_eq[0x00005];/* Log base 2 of number of supported EQs. 670 Must be 6 or less in InfiniHost-III-EX. */ 671 pseudo_bit_t eqc_base_addr_l[0x0001b];/* EQC Base Address [31:6] 672 Address may be set to 0xFFFFFFFF if EQs are not supported. 673 Table must be aligned to entry size. */ 674/* -------------- */ 675 pseudo_bit_t reserved6[0x00040]; 676/* -------------- */ 677 pseudo_bit_t rdmardc_base_addr_h[0x00020];/* rdmardc_base_addr_h: Base address of table that holds remote read and remote atomic requests [63:32]. */ 678/* -------------- */ 679 pseudo_bit_t log_num_rd[0x00003]; /* Log (base 2) of the maximum number of RdmaRdC entries per QP. This denotes the maximum number of outstanding reads/atomics as a responder. */ 680 pseudo_bit_t reserved7[0x00002]; 681 pseudo_bit_t rdmardc_base_addr_l[0x0001b];/* rdmardc_base_addr_l: Base address of table that holds remote read and remote atomic requests [31:0]. 682 Table must be aligned to RDB entry size (32 bytes). */ 683/* -------------- */ 684 pseudo_bit_t reserved8[0x00040]; 685/* -------------- */ 686}; 687 688/* Header_Log_Register */ 689 690struct hermonprm_header_log_register_st { /* Little Endian */ 691 pseudo_bit_t place_holder[0x00020]; 692/* -------------- */ 693 pseudo_bit_t reserved0[0x00060]; 694/* -------------- */ 695}; 696 697/* Performance Monitors */ 698 699struct hermonprm_performance_monitors_st { /* Little Endian */ 700 pseudo_bit_t e0[0x00001]; /* Enables counting of respective performance counter */ 701 pseudo_bit_t e1[0x00001]; /* Enables counting of respective performance counter */ 702 pseudo_bit_t e2[0x00001]; /* Enables counting of respective performance counter */ 703 pseudo_bit_t reserved0[0x00001]; 704 pseudo_bit_t r0[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 705 pseudo_bit_t r1[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 706 pseudo_bit_t r2[0x00001]; /* If written to as '1 - resets respective performance counter, if written to az '0 - no change to matter */ 707 pseudo_bit_t reserved1[0x00001]; 708 pseudo_bit_t i0[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 709 pseudo_bit_t i1[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 710 pseudo_bit_t i2[0x00001]; /* Interrupt enable on respective counter overflow. '1 - interrupt enabled, '0 - interrupt disabled. */ 711 pseudo_bit_t reserved2[0x00001]; 712 pseudo_bit_t f0[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 713 pseudo_bit_t f1[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 714 pseudo_bit_t f2[0x00001]; /* Overflow flag. If set, overflow occurred on respective counter. Cleared if written to as '1 */ 715 pseudo_bit_t reserved3[0x00001]; 716 pseudo_bit_t ev_cnt1[0x00005]; /* Specifies event to be counted by Event_counter1 See XXX for events' definition. */ 717 pseudo_bit_t reserved4[0x00003]; 718 pseudo_bit_t ev_cnt2[0x00005]; /* Specifies event to be counted by Event_counter2 See XXX for events' definition. */ 719 pseudo_bit_t reserved5[0x00003]; 720/* -------------- */ 721 pseudo_bit_t clock_counter[0x00020]; 722/* -------------- */ 723 pseudo_bit_t event_counter1[0x00020]; 724/* -------------- */ 725 pseudo_bit_t event_counter2[0x00020];/* Read/write event counter, counting events specified by EvCntl and EvCnt2 fields repsectively. When the event counter reaches is maximum value of 0xFFFFFF, the next event will cause it to roll over to zero, set F1 or F2 bit respectively and generate interrupt by I1 I2 bit respectively. */ 726/* -------------- */ 727}; 728 729/* MLX WQE segment format */ 730 731struct hermonprm_wqe_segment_ctrl_mlx_st { /* Little Endian */ 732 pseudo_bit_t opcode[0x00005]; /* must be 0xA = SEND */ 733 pseudo_bit_t reserved0[0x0001a]; 734 pseudo_bit_t owner[0x00001]; 735/* -------------- */ 736 pseudo_bit_t ds[0x00006]; /* Descriptor Size */ 737 pseudo_bit_t reserved1[0x0001a]; 738/* -------------- */ 739 pseudo_bit_t fl[0x00001]; /* Force LoopBack */ 740 pseudo_bit_t reserved2[0x00001]; 741 pseudo_bit_t c[0x00002]; /* Create CQE (for "requested signalling" QP) */ 742 pseudo_bit_t icrc[0x00001]; /* last dword of the packet: 0 - Calculate ICRC and put it instead of last dword. 1 - Leave last dword as is. */ 743 pseudo_bit_t reserved3[0x00003]; 744 pseudo_bit_t sl[0x00004]; 745 pseudo_bit_t max_statrate[0x00004]; 746 pseudo_bit_t slr[0x00001]; /* 0= take slid from port. 1= take slid from given headers */ 747 pseudo_bit_t v15[0x00001]; /* Send packet over VL15 */ 748 pseudo_bit_t reserved4[0x0000e]; 749/* -------------- */ 750 pseudo_bit_t reserved5[0x00010]; 751 pseudo_bit_t rlid[0x00010]; /* Destination LID (must match given headers) */ 752/* -------------- */ 753}; 754 755/* Send WQE segment format */ 756 757struct hermonprm_send_wqe_segment_st { /* Little Endian */ 758 struct hermonprm_wqe_segment_ctrl_send_st wqe_segment_ctrl_send;/* Send wqe segment ctrl */ 759/* -------------- */ 760 struct hermonprm_wqe_segment_rd_st wqe_segment_rd;/* Send wqe segment rd */ 761/* -------------- */ 762 struct hermonprm_wqe_segment_ud_st wqe_segment_ud;/* Send wqe segment ud */ 763/* -------------- */ 764 struct hermonprm_wqe_segment_bind_st wqe_segment_bind;/* Send wqe segment bind */ 765/* -------------- */ 766 pseudo_bit_t reserved0[0x00180]; 767/* -------------- */ 768 struct hermonprm_wqe_segment_remote_address_st wqe_segment_remote_address;/* Send wqe segment remote address */ 769/* -------------- */ 770 struct hermonprm_wqe_segment_atomic_st wqe_segment_atomic;/* Send wqe segment atomic */ 771/* -------------- */ 772 struct hermonprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ 773/* -------------- */ 774 struct hermonprm_local_invalidate_segment_st local_invalidate_segment;/* local invalidate segment */ 775/* -------------- */ 776 struct hermonprm_wqe_segment_data_ptr_st wqe_segment_data_ptr;/* Send wqe segment data ptr */ 777/* -------------- */ 778 struct hermonprm_wqe_segment_data_inline_st wqe_segment_data_inline;/* Send wqe segment data inline */ 779/* -------------- */ 780 pseudo_bit_t reserved1[0x00200]; 781/* -------------- */ 782}; 783 784/* QP and EE Context Entry */ 785 786struct hermonprm_queue_pair_ee_context_entry_st { /* Little Endian */ 787 pseudo_bit_t reserved0[0x00008]; 788 pseudo_bit_t reserved1[0x00001]; 789 pseudo_bit_t reserved2[0x00002]; 790 pseudo_bit_t pm_state[0x00002]; /* Path migration state (Migrated, Armed or Rearm) 791 11-Migrated 792 00-Armed 793 01-Rearm 794 10-Reserved 795 Should be set to 11 for UD QPs and for QPs which do not support APM */ 796 pseudo_bit_t reserved3[0x00003]; 797 pseudo_bit_t st[0x00004]; /* Transport Service Type: RC: 0, UC: 1, RD: 2, UD: 3, FCMND:4, FEXCH:5, SRC:6, MLX 7, Raw Eth 11 */ 798 pseudo_bit_t reserved4[0x00008]; 799 pseudo_bit_t state[0x00004]; /* QP/EE state: 800 0 - RST 801 1 - INIT 802 2 - RTR 803 3 - RTS 804 4 - SQEr 805 5 - SQD (Send Queue Drained) 806 6 - ERR 807 7 - Send Queue Draining 808 8 - Reserved 809 9 - Suspended 810 A- F - Reserved 811 (Valid for QUERY_QPEE and ERR2RST_QPEE commands only) */ 812/* -------------- */ 813 pseudo_bit_t pd[0x00018]; 814 pseudo_bit_t reserved5[0x00008]; 815/* -------------- */ 816 pseudo_bit_t reserved6[0x00004]; 817 pseudo_bit_t rlky[0x00001]; /* When set this QP can use the Reserved L_Key */ 818 pseudo_bit_t reserved7[0x00003]; 819 pseudo_bit_t log_sq_stride[0x00003];/* Stride on the send queue. WQ entry is 16*(2^log_SQ_stride) bytes. 820 Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ 821 pseudo_bit_t log_sq_size[0x00004]; /* Log2 of the Number of WQEs in the Send Queue. */ 822 pseudo_bit_t reserved8[0x00001]; 823 pseudo_bit_t log_rq_stride[0x00003];/* Stride on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. 824 Stride must be equal or bigger then 64 bytes (minimum log_RQ_stride value allowed is 2). */ 825 pseudo_bit_t log_rq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. */ 826 pseudo_bit_t reserved9[0x00001]; 827 pseudo_bit_t msg_max[0x00005]; /* Max message size allowed on the QP. Maximum message size is 2^msg_Max. 828 Must be equal to MTU for UD and MLX QPs. */ 829 pseudo_bit_t mtu[0x00003]; /* MTU of the QP (Must be the same for both paths: primary and alternative): 830 0x1 - 256 bytes 831 0x2 - 512 832 0x3 - 1024 833 0x4 - 2048 834 other - reserved 835 836 Should be configured to 0x4 for UD and MLX QPs. */ 837/* -------------- */ 838 pseudo_bit_t usr_page[0x00018]; /* UAR number to ring doorbells for this QP (aliased to doorbell and Blue Flame pages) */ 839 pseudo_bit_t reserved10[0x00008]; 840/* -------------- */ 841 pseudo_bit_t local_qpn_een[0x00018];/* Local QP/EE number Lower bits determine position of this record in QPC table, and - thus - constrained 842 This field is valid for QUERY and ERR2RST commands only. */ 843 pseudo_bit_t reserved11[0x00008]; 844/* -------------- */ 845 pseudo_bit_t remote_qpn_een[0x00018];/* Remote QP/EE number */ 846 pseudo_bit_t reserved12[0x00008]; 847/* -------------- */ 848 struct hermonprm_address_path_st primary_address_path;/* Primary address path for the QP/EE */ 849/* -------------- */ 850 struct hermonprm_address_path_st alternative_address_path;/* Alternate address path for the QP/EE */ 851/* -------------- */ 852 pseudo_bit_t reserved13[0x00003]; 853 pseudo_bit_t reserved14[0x00001]; 854 pseudo_bit_t reserved15[0x00001]; 855 pseudo_bit_t cur_retry_cnt[0x00003];/* Current transport retry counter (QUERY_QPEE only). 856 The current transport retry counter can vary from retry_count down to 1, where 1 means that the last retry attempt is currently executing. */ 857 pseudo_bit_t cur_rnr_retry[0x00003];/* Current RNR retry counter (QUERY_QPEE only). 858 The current RNR retry counter can vary from rnr_retry to 1, where 1 means that the last retry attempt is currently executing. */ 859 pseudo_bit_t fre[0x00001]; /* Fast Registration Work Request Enabled. (Reserved for EE) */ 860 pseudo_bit_t reserved16[0x00001]; 861 pseudo_bit_t rnr_retry[0x00003]; 862 pseudo_bit_t retry_count[0x00003]; /* Transport timeout Retry count */ 863 pseudo_bit_t reserved17[0x00002]; 864 pseudo_bit_t sra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed in the send queue. Maximum number is 2^SRA_Max. Must be zero in EE context. */ 865 pseudo_bit_t reserved18[0x00004]; 866 pseudo_bit_t ack_req_freq[0x00004]; /* ACK required frequency. ACK required bit will be set in every 2^AckReqFreq packets at least. Not valid for RD QP. */ 867/* -------------- */ 868 pseudo_bit_t reserved19[0x00020]; 869/* -------------- */ 870 pseudo_bit_t next_send_psn[0x00018];/* Next PSN to be sent */ 871 pseudo_bit_t reserved20[0x00008]; 872/* -------------- */ 873 pseudo_bit_t cqn_snd[0x00018]; /* CQ number completions from the send queue to be reported to. Not valid (reserved) in EE context. */ 874 pseudo_bit_t reserved21[0x00008]; 875/* -------------- */ 876 pseudo_bit_t reserved22[0x00040]; 877/* -------------- */ 878 pseudo_bit_t last_acked_psn[0x00018];/* The last acknowledged PSN for the requester (QUERY_QPEE only) */ 879 pseudo_bit_t reserved23[0x00008]; 880/* -------------- */ 881 pseudo_bit_t ssn[0x00018]; /* Requester Send Sequence Number (QUERY_QPEE only) */ 882 pseudo_bit_t reserved24[0x00008]; 883/* -------------- */ 884 pseudo_bit_t reserved25[0x00004]; 885 pseudo_bit_t ric[0x00001]; /* Invalid Credits. 886 1 - place "Invalid Credits" to ACKs sent from this queue. 887 0 - ACKs report the actual number of end to end credits on the connection. 888 Not valid (reserved) in EE context. 889 Must be set to 1 on QPs which are attached to SRQ. */ 890 pseudo_bit_t reserved26[0x00001]; 891 pseudo_bit_t page_offset[0x00006]; /* start address of wqes in first page (11:6), bits [5:0] reserved */ 892 pseudo_bit_t reserved27[0x00001]; 893 pseudo_bit_t rae[0x00001]; /* If set - Atomic operations enabled. on receive queue. Not valid (reserved) in EE context. */ 894 pseudo_bit_t rwe[0x00001]; /* If set - RDMA - write enabled on receive queue. Not valid (reserved) in EE context. */ 895 pseudo_bit_t rre[0x00001]; /* If set - RDMA - read enabled on receive queue. Not valid (reserved) in EE context. */ 896 pseudo_bit_t reserved28[0x00005]; 897 pseudo_bit_t rra_max[0x00003]; /* Maximum number of outstanding RDMA-read/Atomic operations allowed on receive queue is 2^RRA_Max. 898 Must be 0 for EE context. */ 899 pseudo_bit_t reserved29[0x00008]; 900/* -------------- */ 901 pseudo_bit_t next_rcv_psn[0x00018]; /* Next (expected) PSN on receive */ 902 pseudo_bit_t min_rnr_nak[0x00005]; /* Minimum RNR NAK timer value (TTTTT field encoding according to the IB spec Vol1 9.7.5.2.8). 903 Not valid (reserved) in EE context. */ 904 pseudo_bit_t reserved30[0x00003]; 905/* -------------- */ 906 pseudo_bit_t srcd[0x00010]; /* Scalable Reliable Connection Domain. Valid for SRC transport service */ 907 pseudo_bit_t reserved31[0x00010]; 908/* -------------- */ 909 pseudo_bit_t cqn_rcv[0x00018]; /* CQ number completions from receive queue to be reported to. Not valid (reserved) in EE context. */ 910 pseudo_bit_t reserved32[0x00008]; 911/* -------------- */ 912 pseudo_bit_t db_record_addr_h[0x00020];/* QP DB Record physical address */ 913/* -------------- */ 914 pseudo_bit_t reserved33[0x00002]; 915 pseudo_bit_t db_record_addr_l[0x0001e];/* QP DB Record physical address */ 916/* -------------- */ 917 pseudo_bit_t q_key[0x00020]; /* Q_Key to be validated against received datagrams. 918 On send datagrams, if Q_Key[31] specified in the WQE is set, then this Q_Key will be transmitted in the outgoing message. 919 Not valid (reserved) in EE context. */ 920/* -------------- */ 921 pseudo_bit_t srqn[0x00018]; /* SRQN - Shared Receive Queue Number - specifies the SRQ number from which the QP dequeues receive descriptors. 922 SRQN is valid only if SRQ bit is set. Not valid (reserved) in EE context. */ 923 pseudo_bit_t srq[0x00001]; /* SRQ - Shared Receive Queue. If this bit is set, then the QP is associated with a SRQ. Not valid (reserved) in EE context. */ 924 pseudo_bit_t reserved34[0x00007]; 925/* -------------- */ 926 pseudo_bit_t rmsn[0x00018]; /* Responder current message sequence number (QUERY_QPEE only) */ 927 pseudo_bit_t reserved35[0x00008]; 928/* -------------- */ 929 pseudo_bit_t sq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the SQ. 930 Must be 0x0 in SQ initialization. 931 (QUERY_QPEE only). */ 932 pseudo_bit_t rq_wqe_counter[0x00010];/* A 16bits counter that is incremented for each WQE posted to the RQ. 933 Must be 0x0 in RQ initialization. 934 (QUERY_QPEE only). */ 935/* -------------- */ 936 pseudo_bit_t reserved36[0x00040]; 937/* -------------- */ 938 pseudo_bit_t rmc_parent_qpn[0x00018];/* reliable multicast parent queue number */ 939 pseudo_bit_t hs[0x00001]; /* Header Separation. If set, the byte count of the first scatter entry will be ignored. The buffer specified by the first scatter entry will contain packet headers (up to TCP). CQE will report number of bytes scattered to the first scatter entry. Intended for use on IPoverIB on UD QP or Raw Ethernet QP. */ 940 pseudo_bit_t is[0x00001]; /* when set - inline scatter is enabled for this RQ */ 941 pseudo_bit_t reserved37[0x00001]; 942 pseudo_bit_t rme[0x00002]; /* Reliable Multicast 943 00 - disabled 944 01 - parent QP (requester) 945 10 - child QP (requester) 946 11 - responder QP 947 Note that Reliable Multicast is a preliminary definition which can be subject to change. */ 948 pseudo_bit_t reserved38[0x00002]; 949 pseudo_bit_t mkey_rmp[0x00001]; /* If set, MKey used to access TPT for incoming RDMA-write request is calculated by adding MKey from the packet to base_MKey field in the QPC. Can be set only for QPs that are not target for RDMA-read request. */ 950/* -------------- */ 951 pseudo_bit_t base_mkey[0x00018]; /* Base Mkey bits [31:8]. Lower 8 bits must be zero. */ 952 pseudo_bit_t num_rmc_peers[0x00008];/* Number of remote peers in Reliable Multicast group */ 953/* -------------- */ 954 pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ 955 pseudo_bit_t reserved39[0x00010]; 956 pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ 957 pseudo_bit_t reserved40[0x00002]; 958/* -------------- */ 959 pseudo_bit_t reserved41[0x00003]; 960 pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ 961/* -------------- */ 962 pseudo_bit_t vft_lan[0x0000c]; 963 pseudo_bit_t vft_prio[0x00003]; /* The Priority filed in the VFT header for FCP */ 964 pseudo_bit_t reserved42[0x00001]; 965 pseudo_bit_t cs_ctl[0x00009]; /* The Priority filed in the VFT header for FCP */ 966 pseudo_bit_t reserved43[0x00006]; 967 pseudo_bit_t ve[0x00001]; /* Should we add/check the VFT header */ 968/* -------------- */ 969 pseudo_bit_t exch_base[0x00010]; /* For init QP only - The base exchanges */ 970 pseudo_bit_t reserved44[0x00008]; 971 pseudo_bit_t exch_size[0x00004]; /* For CMMD QP only - The size (from base) exchanges is 2exchanges_size */ 972 pseudo_bit_t reserved45[0x00003]; 973 pseudo_bit_t fc[0x00001]; /* When set it mean that this QP is used for FIBRE CHANNEL. */ 974/* -------------- */ 975 pseudo_bit_t remote_id[0x00018]; /* Peer NX port ID */ 976 pseudo_bit_t reserved46[0x00008]; 977/* -------------- */ 978 pseudo_bit_t fcp_mtu[0x0000a]; /* In 4*Bytes units. The MTU Size */ 979 pseudo_bit_t reserved47[0x00006]; 980 pseudo_bit_t my_id_indx[0x00008]; /* Index to My NX port ID table */ 981 pseudo_bit_t vft_hop_count[0x00008];/* HopCnt value for the VFT header */ 982/* -------------- */ 983 pseudo_bit_t reserved48[0x000c0]; 984/* -------------- */ 985}; 986 987/* */ 988 989struct hermonprm_mcg_qp_dw_st { /* Little Endian */ 990 pseudo_bit_t qpn[0x00018]; 991 pseudo_bit_t reserved0[0x00006]; 992 pseudo_bit_t blck_lb[0x00001]; 993 pseudo_bit_t reserved1[0x00001]; 994/* -------------- */ 995}; 996 997/* Clear Interrupt [63:0] #### michal - match to PRM */ 998 999struct hermonprm_clr_int_st { /* Little Endian */ 1000 pseudo_bit_t clr_int_h[0x00020]; /* Clear Interrupt [63:32] 1001 Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 1002 This register is write-only. Reading from this register will cause undefined result 1003 */ 1004/* -------------- */ 1005 pseudo_bit_t clr_int_l[0x00020]; /* Clear Interrupt [31:0] 1006 Write transactions to this register will clear (de-assert) the virtual interrupt output pins of InfiniHost-III-EX. The value to be written in this register is obtained by executing QUERY_ADAPTER command on command interface after system boot. 1007 This register is write-only. Reading from this register will cause undefined result */ 1008/* -------------- */ 1009}; 1010 1011/* EQ Set CI DBs Table */ 1012 1013struct hermonprm_eq_set_ci_table_st { /* Little Endian */ 1014 pseudo_bit_t eq0_set_ci[0x00020]; /* EQ0_Set_CI */ 1015/* -------------- */ 1016 pseudo_bit_t reserved0[0x00020]; 1017/* -------------- */ 1018 pseudo_bit_t eq1_set_ci[0x00020]; /* EQ1_Set_CI */ 1019/* -------------- */ 1020 pseudo_bit_t reserved1[0x00020]; 1021/* -------------- */ 1022 pseudo_bit_t eq2_set_ci[0x00020]; /* EQ2_Set_CI */ 1023/* -------------- */ 1024 pseudo_bit_t reserved2[0x00020]; 1025/* -------------- */ 1026 pseudo_bit_t eq3_set_ci[0x00020]; /* EQ3_Set_CI */ 1027/* -------------- */ 1028 pseudo_bit_t reserved3[0x00020]; 1029/* -------------- */ 1030 pseudo_bit_t eq4_set_ci[0x00020]; /* EQ4_Set_CI */ 1031/* -------------- */ 1032 pseudo_bit_t reserved4[0x00020]; 1033/* -------------- */ 1034 pseudo_bit_t eq5_set_ci[0x00020]; /* EQ5_Set_CI */ 1035/* -------------- */ 1036 pseudo_bit_t reserved5[0x00020]; 1037/* -------------- */ 1038 pseudo_bit_t eq6_set_ci[0x00020]; /* EQ6_Set_CI */ 1039/* -------------- */ 1040 pseudo_bit_t reserved6[0x00020]; 1041/* -------------- */ 1042 pseudo_bit_t eq7_set_ci[0x00020]; /* EQ7_Set_CI */ 1043/* -------------- */ 1044 pseudo_bit_t reserved7[0x00020]; 1045/* -------------- */ 1046 pseudo_bit_t eq8_set_ci[0x00020]; /* EQ8_Set_CI */ 1047/* -------------- */ 1048 pseudo_bit_t reserved8[0x00020]; 1049/* -------------- */ 1050 pseudo_bit_t eq9_set_ci[0x00020]; /* EQ9_Set_CI */ 1051/* -------------- */ 1052 pseudo_bit_t reserved9[0x00020]; 1053/* -------------- */ 1054 pseudo_bit_t eq10_set_ci[0x00020]; /* EQ10_Set_CI */ 1055/* -------------- */ 1056 pseudo_bit_t reserved10[0x00020]; 1057/* -------------- */ 1058 pseudo_bit_t eq11_set_ci[0x00020]; /* EQ11_Set_CI */ 1059/* -------------- */ 1060 pseudo_bit_t reserved11[0x00020]; 1061/* -------------- */ 1062 pseudo_bit_t eq12_set_ci[0x00020]; /* EQ12_Set_CI */ 1063/* -------------- */ 1064 pseudo_bit_t reserved12[0x00020]; 1065/* -------------- */ 1066 pseudo_bit_t eq13_set_ci[0x00020]; /* EQ13_Set_CI */ 1067/* -------------- */ 1068 pseudo_bit_t reserved13[0x00020]; 1069/* -------------- */ 1070 pseudo_bit_t eq14_set_ci[0x00020]; /* EQ14_Set_CI */ 1071/* -------------- */ 1072 pseudo_bit_t reserved14[0x00020]; 1073/* -------------- */ 1074 pseudo_bit_t eq15_set_ci[0x00020]; /* EQ15_Set_CI */ 1075/* -------------- */ 1076 pseudo_bit_t reserved15[0x00020]; 1077/* -------------- */ 1078 pseudo_bit_t eq16_set_ci[0x00020]; /* EQ16_Set_CI */ 1079/* -------------- */ 1080 pseudo_bit_t reserved16[0x00020]; 1081/* -------------- */ 1082 pseudo_bit_t eq17_set_ci[0x00020]; /* EQ17_Set_CI */ 1083/* -------------- */ 1084 pseudo_bit_t reserved17[0x00020]; 1085/* -------------- */ 1086 pseudo_bit_t eq18_set_ci[0x00020]; /* EQ18_Set_CI */ 1087/* -------------- */ 1088 pseudo_bit_t reserved18[0x00020]; 1089/* -------------- */ 1090 pseudo_bit_t eq19_set_ci[0x00020]; /* EQ19_Set_CI */ 1091/* -------------- */ 1092 pseudo_bit_t reserved19[0x00020]; 1093/* -------------- */ 1094 pseudo_bit_t eq20_set_ci[0x00020]; /* EQ20_Set_CI */ 1095/* -------------- */ 1096 pseudo_bit_t reserved20[0x00020]; 1097/* -------------- */ 1098 pseudo_bit_t eq21_set_ci[0x00020]; /* EQ21_Set_CI */ 1099/* -------------- */ 1100 pseudo_bit_t reserved21[0x00020]; 1101/* -------------- */ 1102 pseudo_bit_t eq22_set_ci[0x00020]; /* EQ22_Set_CI */ 1103/* -------------- */ 1104 pseudo_bit_t reserved22[0x00020]; 1105/* -------------- */ 1106 pseudo_bit_t eq23_set_ci[0x00020]; /* EQ23_Set_CI */ 1107/* -------------- */ 1108 pseudo_bit_t reserved23[0x00020]; 1109/* -------------- */ 1110 pseudo_bit_t eq24_set_ci[0x00020]; /* EQ24_Set_CI */ 1111/* -------------- */ 1112 pseudo_bit_t reserved24[0x00020]; 1113/* -------------- */ 1114 pseudo_bit_t eq25_set_ci[0x00020]; /* EQ25_Set_CI */ 1115/* -------------- */ 1116 pseudo_bit_t reserved25[0x00020]; 1117/* -------------- */ 1118 pseudo_bit_t eq26_set_ci[0x00020]; /* EQ26_Set_CI */ 1119/* -------------- */ 1120 pseudo_bit_t reserved26[0x00020]; 1121/* -------------- */ 1122 pseudo_bit_t eq27_set_ci[0x00020]; /* EQ27_Set_CI */ 1123/* -------------- */ 1124 pseudo_bit_t reserved27[0x00020]; 1125/* -------------- */ 1126 pseudo_bit_t eq28_set_ci[0x00020]; /* EQ28_Set_CI */ 1127/* -------------- */ 1128 pseudo_bit_t reserved28[0x00020]; 1129/* -------------- */ 1130 pseudo_bit_t eq29_set_ci[0x00020]; /* EQ29_Set_CI */ 1131/* -------------- */ 1132 pseudo_bit_t reserved29[0x00020]; 1133/* -------------- */ 1134 pseudo_bit_t eq30_set_ci[0x00020]; /* EQ30_Set_CI */ 1135/* -------------- */ 1136 pseudo_bit_t reserved30[0x00020]; 1137/* -------------- */ 1138 pseudo_bit_t eq31_set_ci[0x00020]; /* EQ31_Set_CI */ 1139/* -------------- */ 1140 pseudo_bit_t reserved31[0x00020]; 1141/* -------------- */ 1142 pseudo_bit_t eq32_set_ci[0x00020]; /* EQ32_Set_CI */ 1143/* -------------- */ 1144 pseudo_bit_t reserved32[0x00020]; 1145/* -------------- */ 1146 pseudo_bit_t eq33_set_ci[0x00020]; /* EQ33_Set_CI */ 1147/* -------------- */ 1148 pseudo_bit_t reserved33[0x00020]; 1149/* -------------- */ 1150 pseudo_bit_t eq34_set_ci[0x00020]; /* EQ34_Set_CI */ 1151/* -------------- */ 1152 pseudo_bit_t reserved34[0x00020]; 1153/* -------------- */ 1154 pseudo_bit_t eq35_set_ci[0x00020]; /* EQ35_Set_CI */ 1155/* -------------- */ 1156 pseudo_bit_t reserved35[0x00020]; 1157/* -------------- */ 1158 pseudo_bit_t eq36_set_ci[0x00020]; /* EQ36_Set_CI */ 1159/* -------------- */ 1160 pseudo_bit_t reserved36[0x00020]; 1161/* -------------- */ 1162 pseudo_bit_t eq37_set_ci[0x00020]; /* EQ37_Set_CI */ 1163/* -------------- */ 1164 pseudo_bit_t reserved37[0x00020]; 1165/* -------------- */ 1166 pseudo_bit_t eq38_set_ci[0x00020]; /* EQ38_Set_CI */ 1167/* -------------- */ 1168 pseudo_bit_t reserved38[0x00020]; 1169/* -------------- */ 1170 pseudo_bit_t eq39_set_ci[0x00020]; /* EQ39_Set_CI */ 1171/* -------------- */ 1172 pseudo_bit_t reserved39[0x00020]; 1173/* -------------- */ 1174 pseudo_bit_t eq40_set_ci[0x00020]; /* EQ40_Set_CI */ 1175/* -------------- */ 1176 pseudo_bit_t reserved40[0x00020]; 1177/* -------------- */ 1178 pseudo_bit_t eq41_set_ci[0x00020]; /* EQ41_Set_CI */ 1179/* -------------- */ 1180 pseudo_bit_t reserved41[0x00020]; 1181/* -------------- */ 1182 pseudo_bit_t eq42_set_ci[0x00020]; /* EQ42_Set_CI */ 1183/* -------------- */ 1184 pseudo_bit_t reserved42[0x00020]; 1185/* -------------- */ 1186 pseudo_bit_t eq43_set_ci[0x00020]; /* EQ43_Set_CI */ 1187/* -------------- */ 1188 pseudo_bit_t reserved43[0x00020]; 1189/* -------------- */ 1190 pseudo_bit_t eq44_set_ci[0x00020]; /* EQ44_Set_CI */ 1191/* -------------- */ 1192 pseudo_bit_t reserved44[0x00020]; 1193/* -------------- */ 1194 pseudo_bit_t eq45_set_ci[0x00020]; /* EQ45_Set_CI */ 1195/* -------------- */ 1196 pseudo_bit_t reserved45[0x00020]; 1197/* -------------- */ 1198 pseudo_bit_t eq46_set_ci[0x00020]; /* EQ46_Set_CI */ 1199/* -------------- */ 1200 pseudo_bit_t reserved46[0x00020]; 1201/* -------------- */ 1202 pseudo_bit_t eq47_set_ci[0x00020]; /* EQ47_Set_CI */ 1203/* -------------- */ 1204 pseudo_bit_t reserved47[0x00020]; 1205/* -------------- */ 1206 pseudo_bit_t eq48_set_ci[0x00020]; /* EQ48_Set_CI */ 1207/* -------------- */ 1208 pseudo_bit_t reserved48[0x00020]; 1209/* -------------- */ 1210 pseudo_bit_t eq49_set_ci[0x00020]; /* EQ49_Set_CI */ 1211/* -------------- */ 1212 pseudo_bit_t reserved49[0x00020]; 1213/* -------------- */ 1214 pseudo_bit_t eq50_set_ci[0x00020]; /* EQ50_Set_CI */ 1215/* -------------- */ 1216 pseudo_bit_t reserved50[0x00020]; 1217/* -------------- */ 1218 pseudo_bit_t eq51_set_ci[0x00020]; /* EQ51_Set_CI */ 1219/* -------------- */ 1220 pseudo_bit_t reserved51[0x00020]; 1221/* -------------- */ 1222 pseudo_bit_t eq52_set_ci[0x00020]; /* EQ52_Set_CI */ 1223/* -------------- */ 1224 pseudo_bit_t reserved52[0x00020]; 1225/* -------------- */ 1226 pseudo_bit_t eq53_set_ci[0x00020]; /* EQ53_Set_CI */ 1227/* -------------- */ 1228 pseudo_bit_t reserved53[0x00020]; 1229/* -------------- */ 1230 pseudo_bit_t eq54_set_ci[0x00020]; /* EQ54_Set_CI */ 1231/* -------------- */ 1232 pseudo_bit_t reserved54[0x00020]; 1233/* -------------- */ 1234 pseudo_bit_t eq55_set_ci[0x00020]; /* EQ55_Set_CI */ 1235/* -------------- */ 1236 pseudo_bit_t reserved55[0x00020]; 1237/* -------------- */ 1238 pseudo_bit_t eq56_set_ci[0x00020]; /* EQ56_Set_CI */ 1239/* -------------- */ 1240 pseudo_bit_t reserved56[0x00020]; 1241/* -------------- */ 1242 pseudo_bit_t eq57_set_ci[0x00020]; /* EQ57_Set_CI */ 1243/* -------------- */ 1244 pseudo_bit_t reserved57[0x00020]; 1245/* -------------- */ 1246 pseudo_bit_t eq58_set_ci[0x00020]; /* EQ58_Set_CI */ 1247/* -------------- */ 1248 pseudo_bit_t reserved58[0x00020]; 1249/* -------------- */ 1250 pseudo_bit_t eq59_set_ci[0x00020]; /* EQ59_Set_CI */ 1251/* -------------- */ 1252 pseudo_bit_t reserved59[0x00020]; 1253/* -------------- */ 1254 pseudo_bit_t eq60_set_ci[0x00020]; /* EQ60_Set_CI */ 1255/* -------------- */ 1256 pseudo_bit_t reserved60[0x00020]; 1257/* -------------- */ 1258 pseudo_bit_t eq61_set_ci[0x00020]; /* EQ61_Set_CI */ 1259/* -------------- */ 1260 pseudo_bit_t reserved61[0x00020]; 1261/* -------------- */ 1262 pseudo_bit_t eq62_set_ci[0x00020]; /* EQ62_Set_CI */ 1263/* -------------- */ 1264 pseudo_bit_t reserved62[0x00020]; 1265/* -------------- */ 1266 pseudo_bit_t eq63_set_ci[0x00020]; /* EQ63_Set_CI */ 1267/* -------------- */ 1268 pseudo_bit_t reserved63[0x00020]; 1269/* -------------- */ 1270}; 1271 1272/* InfiniHost-III-EX Configuration Registers #### michal - match to PRM */ 1273 1274struct hermonprm_configuration_registers_st { /* Little Endian */ 1275 pseudo_bit_t reserved0[0x403400]; 1276/* -------------- */ 1277 struct hermonprm_hca_command_register_st hca_command_interface_register;/* HCA Command Register */ 1278/* -------------- */ 1279 pseudo_bit_t reserved1[0x3fcb20]; 1280/* -------------- */ 1281}; 1282 1283/* QP_DB_Record ### michal = gdror fixed */ 1284 1285struct hermonprm_qp_db_record_st { /* Little Endian */ 1286 pseudo_bit_t receive_wqe_counter[0x00010];/* Modulo-64K counter of WQEs posted to the QP since its creation. Should be initialized to zero. */ 1287 pseudo_bit_t reserved0[0x00010]; 1288/* -------------- */ 1289}; 1290 1291/* CQ_ARM_DB_Record */ 1292 1293struct hermonprm_cq_arm_db_record_st { /* Little Endian */ 1294 pseudo_bit_t counter[0x00020]; /* CQ counter for the arming request */ 1295/* -------------- */ 1296 pseudo_bit_t cmd[0x00003]; /* 0x0 - No command 1297 0x1 - Request notification for next Solicited completion event. Counter filed specifies the current CQ Consumer Counter. 1298 0x2 - Request notification for next Solicited or Unsolicited completion event. Counter filed specifies the current CQ Consumer counter. 1299 0x3 - Request notification for multiple completions (Arm-N). Counter filed specifies the value of the CQ Index that when reached by HW (i.e. HW generates a CQE into this Index) Event will be generated 1300 Other - Reserved */ 1301 pseudo_bit_t cmd_sn[0x00002]; /* Command Sequence Number - See Table 35, "CQ Doorbell Layout" for definition of this filed */ 1302 pseudo_bit_t res[0x00003]; /* Must be 0x2 */ 1303 pseudo_bit_t cq_number[0x00018]; /* CQ number */ 1304/* -------------- */ 1305}; 1306 1307/* CQ_CI_DB_Record */ 1308 1309struct hermonprm_cq_ci_db_record_st { /* Little Endian */ 1310 pseudo_bit_t counter[0x00020]; /* CQ counter */ 1311/* -------------- */ 1312 pseudo_bit_t reserved0[0x00005]; 1313 pseudo_bit_t res[0x00003]; /* Must be 0x1 */ 1314 pseudo_bit_t cq_number[0x00018]; /* CQ number */ 1315/* -------------- */ 1316}; 1317 1318/* Virtual_Physical_Mapping */ 1319 1320struct hermonprm_virtual_physical_mapping_st { /* Little Endian */ 1321 pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32]. Valid only for MAP_ICM command. */ 1322/* -------------- */ 1323 pseudo_bit_t reserved0[0x0000c]; 1324 pseudo_bit_t va_l[0x00014]; /* Virtual Address[31:12]. Valid only for MAP_ICM command. */ 1325/* -------------- */ 1326 pseudo_bit_t pa_h[0x00020]; /* Physical Address[63:32] */ 1327/* -------------- */ 1328 pseudo_bit_t log2size[0x00006]; /* Log2 of the size in 4KB pages of the physical and virtual contiguous memory that starts at PA_L/H and VA_L/H */ 1329 pseudo_bit_t reserved1[0x00006]; 1330 pseudo_bit_t pa_l[0x00014]; /* Physical Address[31:12] */ 1331/* -------------- */ 1332}; 1333 1334/* MOD_STAT_CFG #### michal - gdror fix */ 1335 1336struct hermonprm_mod_stat_cfg_st { /* Little Endian */ 1337 pseudo_bit_t reserved0[0x00010]; 1338 pseudo_bit_t rx_options[0x00004]; /* number of RX options to sweep when doing SerDes parameters AutoNegotiation. */ 1339 pseudo_bit_t reserved1[0x00003]; 1340 pseudo_bit_t rx_options_m[0x00001]; /* Modify rx_options */ 1341 pseudo_bit_t tx_options[0x00004]; /* number of TX options to sweep when doing SerDes parameters AutoNegotiation. */ 1342 pseudo_bit_t reserved2[0x00003]; 1343 pseudo_bit_t tx_options_m[0x00001]; /* Modify tx_options */ 1344/* -------------- */ 1345 pseudo_bit_t reserved3[0x00020]; 1346/* -------------- */ 1347 pseudo_bit_t pre_amp[0x00004]; /* Pre Amplitude */ 1348 pseudo_bit_t pre_emp_pre_amp[0x00004]; 1349 pseudo_bit_t pre_emp_out[0x00004]; /* Pre Emphasis Out */ 1350 pseudo_bit_t voltage[0x00004]; 1351 pseudo_bit_t equ[0x00004]; /* Equalization */ 1352 pseudo_bit_t reserved4[0x0000b]; 1353 pseudo_bit_t serdes_m[0x00001]; /* Modify serdes parameters */ 1354/* -------------- */ 1355 pseudo_bit_t lid[0x00010]; /* default LID */ 1356 pseudo_bit_t lid_m[0x00001]; /* Modify default LID */ 1357 pseudo_bit_t reserved5[0x00003]; 1358 pseudo_bit_t port_en[0x00001]; /* enable port (E_Key) */ 1359 pseudo_bit_t port_en_m[0x00001]; /* Modify port_en */ 1360 pseudo_bit_t reserved6[0x0000a]; 1361/* -------------- */ 1362 pseudo_bit_t reserved7[0x0001f]; 1363 pseudo_bit_t guid_hi_m[0x00001]; /* Modify guid_hi */ 1364/* -------------- */ 1365 pseudo_bit_t guid_hi[0x00020]; 1366/* -------------- */ 1367 pseudo_bit_t reserved8[0x0001f]; 1368 pseudo_bit_t guid_lo_m[0x00001]; /* Modify guid_lo */ 1369/* -------------- */ 1370 pseudo_bit_t guid_lo[0x00020]; 1371/* -------------- */ 1372 pseudo_bit_t reserved9[0x0001f]; 1373 pseudo_bit_t nodeguid_hi_m[0x00001]; 1374/* -------------- */ 1375 pseudo_bit_t nodeguid_hi[0x00020]; 1376/* -------------- */ 1377 pseudo_bit_t reserved10[0x0001f]; 1378 pseudo_bit_t nodeguid_lo_m[0x00001]; 1379/* -------------- */ 1380 pseudo_bit_t nodeguid_lo[0x00020]; 1381/* -------------- */ 1382 pseudo_bit_t reserved11[0x00680]; 1383/* -------------- */ 1384}; 1385 1386/* SRQ Context */ 1387 1388struct hermonprm_srq_context_st { /* Little Endian */ 1389 pseudo_bit_t srqn[0x00018]; /* SRQ number */ 1390 pseudo_bit_t log_srq_size[0x00004]; /* Log2 of the Number of WQEs in the Receive Queue. 1391 Maximum value is 0x10, i.e. 16M WQEs. */ 1392 pseudo_bit_t state[0x00004]; /* SRQ State: 1393 1111 - SW Ownership 1394 0000 - HW Ownership 1395 0001 - Error 1396 Valid only on QUERY_SRQ and HW2SW_SRQ commands. */ 1397/* -------------- */ 1398 pseudo_bit_t src_domain[0x00010]; /* The Scalable RC Domain. Messages coming to receive ports specifying this SRQ as receive queue will be served only if SRC_Domain of the SRQ matches SRC_Domain of the transport QP of this message. */ 1399 pseudo_bit_t reserved0[0x00008]; 1400 pseudo_bit_t log_srq_stride[0x00003];/* Stride (max WQE size) on the receive queue. WQ entry is 16*(2^log_RQ_stride) bytes. */ 1401 pseudo_bit_t reserved1[0x00005]; 1402/* -------------- */ 1403 pseudo_bit_t cqn[0x00018]; /* Completion Queue to report SRC messages directed to this SRQ. */ 1404 pseudo_bit_t page_offset[0x00006]; /* The offset of the first WQE from the beginning of 4Kbyte page (Figure 52,�Work Queue Buffer Structure�) */ 1405 pseudo_bit_t reserved2[0x00002]; 1406/* -------------- */ 1407 pseudo_bit_t reserved3[0x00020]; 1408/* -------------- */ 1409 pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ 1410 pseudo_bit_t reserved4[0x00010]; 1411 pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ 1412 pseudo_bit_t reserved5[0x00002]; 1413/* -------------- */ 1414 pseudo_bit_t reserved6[0x00003]; 1415 pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ 1416/* -------------- */ 1417 pseudo_bit_t pd[0x00018]; /* SRQ protection domain */ 1418 pseudo_bit_t reserved7[0x00008]; 1419/* -------------- */ 1420 pseudo_bit_t wqe_cnt[0x00010]; /* WQE count on the SRQ. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */ 1421 pseudo_bit_t lwm[0x00010]; /* Limit Water Mark - if the LWM is not zero, and the wqe_cnt drops below LWM when a WQE is dequeued from the SRQ, then an SRQ limit event is fired and the LWM is set to zero. Valid only upon QUERY_SRQ and HW2SW_SRQ commands. */ 1422/* -------------- */ 1423 pseudo_bit_t srq_wqe_counter[0x00010];/* A 16-bit counter incremented for each WQE posted to the SRQ. Must be 0x0 in SRQ initialization. Valid only upon the QUERY_SRQ command. */ 1424 pseudo_bit_t reserved8[0x00010]; 1425/* -------------- */ 1426 pseudo_bit_t reserved9[0x00020]; 1427/* -------------- */ 1428 pseudo_bit_t db_record_addr_h[0x00020];/* SRQ DB Record physical address [63:32] */ 1429/* -------------- */ 1430 pseudo_bit_t reserved10[0x00002]; 1431 pseudo_bit_t db_record_addr_l[0x0001e];/* SRQ DB Record physical address [31:2] */ 1432/* -------------- */ 1433}; 1434 1435/* PBL */ 1436 1437struct hermonprm_pbl_st { /* Little Endian */ 1438 pseudo_bit_t mtt_0_h[0x00020]; /* First MTT[63:32] */ 1439/* -------------- */ 1440 pseudo_bit_t mtt_0_l[0x00020]; /* First MTT[31:0] */ 1441/* -------------- */ 1442 pseudo_bit_t mtt_1_h[0x00020]; /* Second MTT[63:32] */ 1443/* -------------- */ 1444 pseudo_bit_t mtt_1_l[0x00020]; /* Second MTT[31:0] */ 1445/* -------------- */ 1446 pseudo_bit_t mtt_2_h[0x00020]; /* Third MTT[63:32] */ 1447/* -------------- */ 1448 pseudo_bit_t mtt_2_l[0x00020]; /* Third MTT[31:0] */ 1449/* -------------- */ 1450 pseudo_bit_t mtt_3_h[0x00020]; /* Fourth MTT[63:32] */ 1451/* -------------- */ 1452 pseudo_bit_t mtt_3_l[0x00020]; /* Fourth MTT[31:0] */ 1453/* -------------- */ 1454}; 1455 1456/* Performance Counters #### michal - gdror fixed */ 1457 1458struct hermonprm_performance_counters_st { /* Little Endian */ 1459 pseudo_bit_t reserved0[0x00080]; 1460/* -------------- */ 1461 pseudo_bit_t reserved1[0x00080]; 1462/* -------------- */ 1463 pseudo_bit_t reserved2[0x00080]; 1464/* -------------- */ 1465 pseudo_bit_t reserved3[0x00060]; 1466/* -------------- */ 1467 pseudo_bit_t reserved4[0x00620]; 1468/* -------------- */ 1469}; 1470 1471/* Transport and CI Error Counters */ 1472 1473struct hermonprm_transport_and_ci_error_counters_st { /* Little Endian */ 1474 pseudo_bit_t rq_num_lle[0x00020]; /* Responder - number of local length errors */ 1475/* -------------- */ 1476 pseudo_bit_t sq_num_lle[0x00020]; /* Requester - number of local length errors */ 1477/* -------------- */ 1478 pseudo_bit_t rq_num_lqpoe[0x00020]; /* Responder - number local QP operation error */ 1479/* -------------- */ 1480 pseudo_bit_t sq_num_lqpoe[0x00020]; /* Requester - number local QP operation error */ 1481/* -------------- */ 1482 pseudo_bit_t rq_num_leeoe[0x00020]; /* Responder - number local EE operation error */ 1483/* -------------- */ 1484 pseudo_bit_t sq_num_leeoe[0x00020]; /* Requester - number local EE operation error */ 1485/* -------------- */ 1486 pseudo_bit_t rq_num_lpe[0x00020]; /* Responder - number of local protection errors */ 1487/* -------------- */ 1488 pseudo_bit_t sq_num_lpe[0x00020]; /* Requester - number of local protection errors */ 1489/* -------------- */ 1490 pseudo_bit_t rq_num_wrfe[0x00020]; /* Responder - number of CQEs with error. 1491 Incremented each time a CQE with error is generated */ 1492/* -------------- */ 1493 pseudo_bit_t sq_num_wrfe[0x00020]; /* Requester - number of CQEs with error. 1494 Incremented each time a CQE with error is generated */ 1495/* -------------- */ 1496 pseudo_bit_t reserved0[0x00020]; 1497/* -------------- */ 1498 pseudo_bit_t sq_num_mwbe[0x00020]; /* Requester - number of memory window bind errors */ 1499/* -------------- */ 1500 pseudo_bit_t reserved1[0x00020]; 1501/* -------------- */ 1502 pseudo_bit_t sq_num_bre[0x00020]; /* Requester - number of bad response errors */ 1503/* -------------- */ 1504 pseudo_bit_t rq_num_lae[0x00020]; /* Responder - number of local access errors */ 1505/* -------------- */ 1506 pseudo_bit_t reserved2[0x00040]; 1507/* -------------- */ 1508 pseudo_bit_t sq_num_rire[0x00020]; /* Requester - number of remote invalid request errors 1509 NAK-Invalid Request on: 1510 1. Unsupported OpCode: Responder detected an unsupported OpCode. 1511 2. Unexpected OpCode: Responder detected an error in the sequence of OpCodes, such 1512 as a missing "Last" packet. 1513 Note: there is no PSN error, thus this does not indicate a dropped packet. */ 1514/* -------------- */ 1515 pseudo_bit_t rq_num_rire[0x00020]; /* Responder - number of remote invalid request errors. 1516 NAK may or may not be sent. 1517 1. QP Async Affiliated Error: Unsupported or Reserved OpCode (RC,RD only): 1518 Inbound request OpCode was either reserved, or was for a function not supported by this 1519 QP. (E.g. RDMA or ATOMIC on QP not set up for this). 1520 2. Misaligned ATOMIC: VA does not point to an aligned address on an atomic opera-tion. 1521 3. Too many RDMA READ or ATOMIC Requests: There were more requests received 1522 and not ACKed than allowed for the connection. 1523 4. Out of Sequence OpCode, current packet is "First" or "Only": The Responder 1524 detected an error in the sequence of OpCodes; a missing "Last" packet 1525 5. Out of Sequence OpCode, current packet is not "First" or "Only": The Responder 1526 detected an error in the sequence of OpCodes; a missing "First" packet 1527 6. Local Length Error: Inbound "Send" request message exceeded the responder.s avail-able 1528 buffer space. 1529 7. Length error: RDMA WRITE request message contained too much or too little pay-load 1530 data compared to the DMA length advertised in the first or only packet. 1531 8. Length error: Payload length was not consistent with the opcode: 1532 a: 0 byte <= "only" <= PMTU bytes 1533 b: ("first" or "middle") == PMTU bytes 1534 c: 1byte <= "last" <= PMTU bytes 1535 9. Length error: Inbound message exceeded the size supported by the CA port. */ 1536/* -------------- */ 1537 pseudo_bit_t sq_num_rae[0x00020]; /* Requester - number of remote access errors. 1538 NAK-Remote Access Error on: 1539 R_Key Violation: Responder detected an invalid R_Key while executing an RDMA 1540 Request. */ 1541/* -------------- */ 1542 pseudo_bit_t rq_num_rae[0x00020]; /* Responder - number of remote access errors. 1543 R_Key Violation Responder detected an R_Key violation while executing an RDMA 1544 request. 1545 NAK may or may not be sent. */ 1546/* -------------- */ 1547 pseudo_bit_t sq_num_roe[0x00020]; /* Requester - number of remote operation errors. 1548 NAK-Remote Operation Error on: 1549 Remote Operation Error: Responder encountered an error, (local to the responder), 1550 which prevented it from completing the request. */ 1551/* -------------- */ 1552 pseudo_bit_t rq_num_roe[0x00020]; /* Responder - number of remote operation errors. 1553 NAK-Remote Operation Error on: 1554 1. Malformed WQE: Responder detected a malformed Receive Queue WQE while pro-cessing 1555 the packet. 1556 2. Remote Operation Error: Responder encountered an error, (local to the responder), 1557 which prevented it from completing the request. */ 1558/* -------------- */ 1559 pseudo_bit_t sq_num_tree[0x00020]; /* Requester - number of transport retries exceeded errors */ 1560/* -------------- */ 1561 pseudo_bit_t reserved3[0x00020]; 1562/* -------------- */ 1563 pseudo_bit_t sq_num_rree[0x00020]; /* Requester - number of RNR nak retries exceeded errors */ 1564/* -------------- */ 1565 pseudo_bit_t rq_num_rnr[0x00020]; /* Responder - the number of RNR Naks sent */ 1566/* -------------- */ 1567 pseudo_bit_t sq_num_rnr[0x00020]; /* Requester - the number of RNR Naks received */ 1568/* -------------- */ 1569 pseudo_bit_t reserved4[0x00040]; 1570/* -------------- */ 1571 pseudo_bit_t reserved5[0x00020]; 1572/* -------------- */ 1573 pseudo_bit_t sq_num_rabrte[0x00020];/* Requester - number of remote aborted errors */ 1574/* -------------- */ 1575 pseudo_bit_t reserved6[0x00020]; 1576/* -------------- */ 1577 pseudo_bit_t sq_num_ieecne[0x00020];/* Requester - number of invalid EE context number errors */ 1578/* -------------- */ 1579 pseudo_bit_t reserved7[0x00020]; 1580/* -------------- */ 1581 pseudo_bit_t sq_num_ieecse[0x00020];/* Requester - invalid EE context state errors */ 1582/* -------------- */ 1583 pseudo_bit_t reserved8[0x00380]; 1584/* -------------- */ 1585 pseudo_bit_t rq_num_oos[0x00020]; /* Responder - number of out of sequence requests received */ 1586/* -------------- */ 1587 pseudo_bit_t sq_num_oos[0x00020]; /* Requester - number of out of sequence Naks received */ 1588/* -------------- */ 1589 pseudo_bit_t rq_num_mce[0x00020]; /* Responder - number of bad multicast packets received */ 1590/* -------------- */ 1591 pseudo_bit_t reserved9[0x00020]; 1592/* -------------- */ 1593 pseudo_bit_t rq_num_rsync[0x00020]; /* Responder - number of RESYNC operations */ 1594/* -------------- */ 1595 pseudo_bit_t sq_num_rsync[0x00020]; /* Requester - number of RESYNC operations */ 1596/* -------------- */ 1597 pseudo_bit_t rq_num_udsdprd[0x00020];/* The number of UD packets silently discarded on the receive queue due to lack of receive descriptor. */ 1598/* -------------- */ 1599 pseudo_bit_t reserved10[0x00020]; 1600/* -------------- */ 1601 pseudo_bit_t rq_num_ucsdprd[0x00020];/* The number of UC packets silently discarded on the receive queue due to lack of receive descriptor. */ 1602/* -------------- */ 1603 pseudo_bit_t reserved11[0x003e0]; 1604/* -------------- */ 1605 pseudo_bit_t num_cqovf[0x00020]; /* Number of CQ overflows */ 1606/* -------------- */ 1607 pseudo_bit_t num_eqovf[0x00020]; /* Number of EQ overflows */ 1608/* -------------- */ 1609 pseudo_bit_t num_baddb[0x00020]; /* Number of bad doorbells */ 1610/* -------------- */ 1611 pseudo_bit_t reserved12[0x002a0]; 1612/* -------------- */ 1613}; 1614 1615/* Event_data Field - HCR Completion Event #### michal - match PRM */ 1616 1617struct hermonprm_hcr_completion_event_st { /* Little Endian */ 1618 pseudo_bit_t token[0x00010]; /* HCR Token */ 1619 pseudo_bit_t reserved0[0x00010]; 1620/* -------------- */ 1621 pseudo_bit_t reserved1[0x00020]; 1622/* -------------- */ 1623 pseudo_bit_t status[0x00008]; /* HCR Status */ 1624 pseudo_bit_t reserved2[0x00018]; 1625/* -------------- */ 1626 pseudo_bit_t out_param_h[0x00020]; /* HCR Output Parameter [63:32] */ 1627/* -------------- */ 1628 pseudo_bit_t out_param_l[0x00020]; /* HCR Output Parameter [31:0] */ 1629/* -------------- */ 1630 pseudo_bit_t reserved3[0x00020]; 1631/* -------------- */ 1632}; 1633 1634/* Completion with Error CQE #### michal - gdror fixed */ 1635 1636struct hermonprm_completion_with_error_st { /* Little Endian */ 1637 pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */ 1638 pseudo_bit_t reserved0[0x00008]; 1639/* -------------- */ 1640 pseudo_bit_t reserved1[0x000a0]; 1641/* -------------- */ 1642 pseudo_bit_t syndrome[0x00008]; /* Completion with error syndrome: 1643 0x01 - Local Length Error 1644 0x02 - Local QP Operation Error 1645 0x03 - Local EE Context Operation Error 1646 0x04 - Local Protection Error 1647 0x05 - Work Request Flushed Error 1648 0x06 - Memory Window Bind Error 1649 0x10 - Bad Response Error 1650 0x11 - Local Access Error 1651 0x12 - Remote Invalid Request Error 1652 0x13 - Remote Access Error 1653 0x14 - Remote Operation Error 1654 0x15 - Transport Retry Counter Exceeded 1655 0x16 - RNR Retry Counter Exceeded 1656 0x20 - Local RDD Violation Error 1657 0x21 - Remote Invalid RD Request 1658 0x22 - Remote Aborted Error 1659 0x23 - Invalid EE Context Number 1660 0x24 - Invalid EE Context State 1661 other - Reserved 1662 Syndrome is defined according to the IB specification volume 1. For detailed explanation of the syndromes, refer to chapters 10-11 of the IB specification rev 1.1. */ 1663 pseudo_bit_t vendor_error_syndrome[0x00008]; 1664 pseudo_bit_t wqe_counter[0x00010]; 1665/* -------------- */ 1666 pseudo_bit_t opcode[0x00005]; /* The opcode of WQE completion is reported for. 1667 1668 The following values are reported in case of completion with error: 1669 0xFE - For completion with error on Receive Queues 1670 0xFF - For completion with error on Send Queues */ 1671 pseudo_bit_t reserved2[0x00001]; 1672 pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */ 1673 pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */ 1674 pseudo_bit_t reserved3[0x00018]; 1675/* -------------- */ 1676}; 1677 1678/* Resize CQ Input Mailbox */ 1679 1680struct hermonprm_resize_cq_st { /* Little Endian */ 1681 pseudo_bit_t reserved0[0x00040]; 1682/* -------------- */ 1683 pseudo_bit_t reserved1[0x00006]; 1684 pseudo_bit_t page_offset[0x00006]; 1685 pseudo_bit_t reserved2[0x00014]; 1686/* -------------- */ 1687 pseudo_bit_t reserved3[0x00018]; 1688 pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries) */ 1689 pseudo_bit_t reserved4[0x00003]; 1690/* -------------- */ 1691 pseudo_bit_t reserved5[0x00020]; 1692/* -------------- */ 1693 pseudo_bit_t mtt_base_addr_h[0x00008]; 1694 pseudo_bit_t reserved6[0x00010]; 1695 pseudo_bit_t log2_page_size[0x00006]; 1696 pseudo_bit_t reserved7[0x00002]; 1697/* -------------- */ 1698 pseudo_bit_t reserved8[0x00003]; 1699 pseudo_bit_t mtt_base_addr_l[0x0001d]; 1700/* -------------- */ 1701 pseudo_bit_t reserved9[0x00020]; 1702/* -------------- */ 1703 pseudo_bit_t reserved10[0x00100]; 1704/* -------------- */ 1705}; 1706 1707/* MAD_IFC Input Modifier */ 1708 1709struct hermonprm_mad_ifc_input_modifier_st { /* Little Endian */ 1710 pseudo_bit_t port_number[0x00008]; /* The packet reception port number (1 or 2). */ 1711 pseudo_bit_t mad_extended_info[0x00001];/* Mad_Extended_Info valid bit (MAD_IFC Input Mailbox data from offset 00100h and down). MAD_Extended_Info is read only if this bit is set. 1712 Required for trap generation when BKey check is enabled and for global routed packets. */ 1713 pseudo_bit_t reserved0[0x00007]; 1714 pseudo_bit_t rlid[0x00010]; /* Remote (source) LID from the received MAD. 1715 This field is required for trap generation upon MKey/BKey validation. */ 1716/* -------------- */ 1717}; 1718 1719/* MAD_IFC Input Mailbox ###michal -gdror fixed */ 1720 1721struct hermonprm_mad_ifc_st { /* Little Endian */ 1722 pseudo_bit_t request_mad_packet[64][0x00020];/* Request MAD Packet (256bytes) */ 1723/* -------------- */ 1724 pseudo_bit_t my_qpn[0x00018]; /* Destination QP number from the received MAD. 1725 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 1726 pseudo_bit_t reserved0[0x00008]; 1727/* -------------- */ 1728 pseudo_bit_t reserved1[0x00020]; 1729/* -------------- */ 1730 pseudo_bit_t rqpn[0x00018]; /* Remote (source) QP number from the received MAD. 1731 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 1732 pseudo_bit_t reserved2[0x00008]; 1733/* -------------- */ 1734 pseudo_bit_t reserved3[0x00010]; 1735 pseudo_bit_t ml_path[0x00007]; /* My (destination) LID path bits from the received MAD. 1736 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 1737 pseudo_bit_t g[0x00001]; /* If set, the GRH field in valid. 1738 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 1739 pseudo_bit_t reserved4[0x00004]; 1740 pseudo_bit_t sl[0x00004]; /* Service Level of the received MAD. 1741 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 1742/* -------------- */ 1743 pseudo_bit_t pkey_indx[0x00010]; /* Index in PKey table that matches PKey of the received MAD. 1744 This field is reserved if Mad_extended_info indication in the input modifier is clear. */ 1745 pseudo_bit_t reserved5[0x00010]; 1746/* -------------- */ 1747 pseudo_bit_t reserved6[0x00160]; 1748/* -------------- */ 1749 pseudo_bit_t grh[10][0x00020]; /* The GRH field of the MAD packet that was scattered to the first 40 bytes pointed to by the scatter list. 1750 Valid if Mad_extended_info bit (in the input modifier) and g bit are set. 1751 Otherwise this field is reserved. */ 1752/* -------------- */ 1753 pseudo_bit_t reserved7[0x004c0]; 1754/* -------------- */ 1755}; 1756 1757/* Query Debug Message #### michal - gdror fixed */ 1758 1759struct hermonprm_query_debug_msg_st { /* Little Endian */ 1760 pseudo_bit_t phy_addr_h[0x00020]; /* Translation of the address in firmware area. High 32 bits. */ 1761/* -------------- */ 1762 pseudo_bit_t v[0x00001]; /* Physical translation is valid */ 1763 pseudo_bit_t reserved0[0x0000b]; 1764 pseudo_bit_t phy_addr_l[0x00014]; /* Translation of the address in firmware area. Low 32 bits. */ 1765/* -------------- */ 1766 pseudo_bit_t fw_area_base[0x00020]; /* Firmware area base address. The format strings and the trace buffers may be located starting from this address. */ 1767/* -------------- */ 1768 pseudo_bit_t fw_area_size[0x00020]; /* Firmware area size */ 1769/* -------------- */ 1770 pseudo_bit_t trc_hdr_sz[0x00020]; /* Trace message header size in dwords. */ 1771/* -------------- */ 1772 pseudo_bit_t trc_arg_num[0x00020]; /* The number of arguments per trace message. */ 1773/* -------------- */ 1774 pseudo_bit_t reserved1[0x000c0]; 1775/* -------------- */ 1776 pseudo_bit_t dbg_msk_h[0x00020]; /* Debug messages mask [63:32] */ 1777/* -------------- */ 1778 pseudo_bit_t dbg_msk_l[0x00020]; /* Debug messages mask [31:0] */ 1779/* -------------- */ 1780 pseudo_bit_t reserved2[0x00040]; 1781/* -------------- */ 1782 pseudo_bit_t buff0_addr[0x00020]; /* Address in firmware area of Trace Buffer 0 */ 1783/* -------------- */ 1784 pseudo_bit_t buff0_size[0x00020]; /* Size of Trace Buffer 0 */ 1785/* -------------- */ 1786 pseudo_bit_t buff1_addr[0x00020]; /* Address in firmware area of Trace Buffer 1 */ 1787/* -------------- */ 1788 pseudo_bit_t buff1_size[0x00020]; /* Size of Trace Buffer 1 */ 1789/* -------------- */ 1790 pseudo_bit_t buff2_addr[0x00020]; /* Address in firmware area of Trace Buffer 2 */ 1791/* -------------- */ 1792 pseudo_bit_t buff2_size[0x00020]; /* Size of Trace Buffer 2 */ 1793/* -------------- */ 1794 pseudo_bit_t buff3_addr[0x00020]; /* Address in firmware area of Trace Buffer 3 */ 1795/* -------------- */ 1796 pseudo_bit_t buff3_size[0x00020]; /* Size of Trace Buffer 3 */ 1797/* -------------- */ 1798 pseudo_bit_t buff4_addr[0x00020]; /* Address in firmware area of Trace Buffer 4 */ 1799/* -------------- */ 1800 pseudo_bit_t buff4_size[0x00020]; /* Size of Trace Buffer 4 */ 1801/* -------------- */ 1802 pseudo_bit_t buff5_addr[0x00020]; /* Address in firmware area of Trace Buffer 5 */ 1803/* -------------- */ 1804 pseudo_bit_t buff5_size[0x00020]; /* Size of Trace Buffer 5 */ 1805/* -------------- */ 1806 pseudo_bit_t reserved3[0x00080]; 1807/* -------------- */ 1808 pseudo_bit_t hw_buff_addr[0x00020]; /* Dror Mux Bohrer tracer */ 1809/* -------------- */ 1810 pseudo_bit_t hw_buff_size[0x00020]; 1811/* -------------- */ 1812 pseudo_bit_t reserved4[0x003c0]; 1813/* -------------- */ 1814}; 1815 1816/* User Access Region */ 1817 1818struct hermonprm_uar_st { /* Little Endian */ 1819 struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* Reliable Datagram send doorbell */ 1820/* -------------- */ 1821 struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */ 1822/* -------------- */ 1823 pseudo_bit_t reserved0[0x00040]; 1824/* -------------- */ 1825 struct hermonprm_cq_cmd_doorbell_st cq_command_doorbell;/* CQ Doorbell */ 1826/* -------------- */ 1827 pseudo_bit_t reserved1[0x03ec0]; 1828/* -------------- */ 1829}; 1830 1831/* Receive doorbell */ 1832 1833struct hermonprm_receive_doorbell_st { /* Little Endian */ 1834 pseudo_bit_t reserved0[0x00008]; 1835 pseudo_bit_t wqe_counter[0x00010]; /* Modulo-64K counter of WQEs posted on this queue since its creation. Should be zero for the first doorbell on the QP */ 1836 pseudo_bit_t reserved1[0x00008]; 1837/* -------------- */ 1838 pseudo_bit_t reserved2[0x00005]; 1839 pseudo_bit_t srq[0x00001]; /* If set, this is a Shared Receive Queue */ 1840 pseudo_bit_t reserved3[0x00002]; 1841 pseudo_bit_t qpn[0x00018]; /* QP number or SRQ number this doorbell is rung on */ 1842/* -------------- */ 1843}; 1844 1845/* SET_IB Parameters */ 1846 1847struct hermonprm_set_ib_st { /* Little Endian */ 1848 pseudo_bit_t rqk[0x00001]; /* Reset QKey Violation Counter */ 1849 pseudo_bit_t reserved0[0x00011]; 1850 pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. 1851 system_image_guid and sig must be the same for all ports. */ 1852 pseudo_bit_t reserved1[0x0000d]; 1853/* -------------- */ 1854 pseudo_bit_t capability_mask[0x00020];/* PortInfo Capability Mask */ 1855/* -------------- */ 1856 pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set 1857 Must be the same for both ports. */ 1858/* -------------- */ 1859 pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set 1860 Must be the same for both ports. */ 1861/* -------------- */ 1862 pseudo_bit_t reserved2[0x00180]; 1863/* -------------- */ 1864}; 1865 1866/* Multicast Group Member #### michal - gdror fixed */ 1867 1868struct hermonprm_mgm_entry_st { /* Little Endian */ 1869 pseudo_bit_t reserved0[0x00006]; 1870 pseudo_bit_t next_gid_index[0x0001a];/* Index of next Multicast Group Member whose GID maps to same MGID_HASH number. 1871 The index is into the Multicast Group Table, which is the comprised the MGHT and AMGM tables. 1872 next_gid_index=0 means end of the chain. */ 1873/* -------------- */ 1874 pseudo_bit_t reserved1[0x00060]; 1875/* -------------- */ 1876 pseudo_bit_t mgid_128_96[0x00020]; /* Multicast group GID[128:96] in big endian format. 1877 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 1878/* -------------- */ 1879 pseudo_bit_t mgid_95_64[0x00020]; /* Multicast group GID[95:64] in big endian format. 1880 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 1881/* -------------- */ 1882 pseudo_bit_t mgid_63_32[0x00020]; /* Multicast group GID[63:32] in big endian format. 1883 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 1884/* -------------- */ 1885 pseudo_bit_t mgid_31_0[0x00020]; /* Multicast group GID[31:0] in big endian format. 1886 Use the Reserved GID 0:0:0:0:0:0:0:0 for an invalid entry. */ 1887/* -------------- */ 1888 struct hermonprm_mgmqp_st mgmqp_0; /* Multicast Group Member QP */ 1889/* -------------- */ 1890 struct hermonprm_mgmqp_st mgmqp_1; /* Multicast Group Member QP */ 1891/* -------------- */ 1892 struct hermonprm_mgmqp_st mgmqp_2; /* Multicast Group Member QP */ 1893/* -------------- */ 1894 struct hermonprm_mgmqp_st mgmqp_3; /* Multicast Group Member QP */ 1895/* -------------- */ 1896 struct hermonprm_mgmqp_st mgmqp_4; /* Multicast Group Member QP */ 1897/* -------------- */ 1898 struct hermonprm_mgmqp_st mgmqp_5; /* Multicast Group Member QP */ 1899/* -------------- */ 1900 struct hermonprm_mgmqp_st mgmqp_6; /* Multicast Group Member QP */ 1901/* -------------- */ 1902 struct hermonprm_mgmqp_st mgmqp_7; /* Multicast Group Member QP */ 1903/* -------------- */ 1904}; 1905 1906/* INIT_PORT Parameters #### michal - match PRM */ 1907 1908struct hermonprm_init_port_st { /* Little Endian */ 1909 pseudo_bit_t reserved0[0x00004]; 1910 pseudo_bit_t vl_cap[0x00004]; /* Maximum VLs supported on the port, excluding VL15. 1911 Legal values are 1,2,4 and 8. */ 1912 pseudo_bit_t port_width_cap[0x00004];/* IB Port Width 1913 1 - 1x 1914 3 - 1x, 4x 1915 11 - 1x, 4x or 12x (must not be used in InfiniHost-III-EX MT25208) 1916 else - Reserved */ 1917 pseudo_bit_t reserved1[0x00004]; 1918 pseudo_bit_t g0[0x00001]; /* Set port GUID0 to GUID0 specified */ 1919 pseudo_bit_t ng[0x00001]; /* Set node GUID to node_guid specified. 1920 node_guid and ng must be the same for all ports. */ 1921 pseudo_bit_t sig[0x00001]; /* Set System Image GUID to system_image_guid specified. 1922 system_image_guid and sig must be the same for all ports. */ 1923 pseudo_bit_t reserved2[0x0000d]; 1924/* -------------- */ 1925 pseudo_bit_t max_gid[0x00010]; /* Maximum number of GIDs for the port */ 1926 pseudo_bit_t mtu[0x00010]; /* Maximum MTU Supported in bytes 1927 must be: 256, 512, 1024, 2048 or 4096 1928 For Eth port, can be any 1929 Field must not cross device capabilities as reported 1930 */ 1931/* -------------- */ 1932 pseudo_bit_t max_pkey[0x00010]; /* Maximum pkeys for the port. 1933 Must be the same for both ports. */ 1934 pseudo_bit_t reserved3[0x00010]; 1935/* -------------- */ 1936 pseudo_bit_t reserved4[0x00020]; 1937/* -------------- */ 1938 pseudo_bit_t guid0_h[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 63:32) */ 1939/* -------------- */ 1940 pseudo_bit_t guid0_l[0x00020]; /* EUI-64 GUID assigned by the manufacturer, takes effect only if the G0 bit is set (bits 31:0) */ 1941/* -------------- */ 1942 pseudo_bit_t node_guid_h[0x00020]; /* Node GUID[63:32], takes effect only if the NG bit is set 1943 Must be the same for both ports. */ 1944/* -------------- */ 1945 pseudo_bit_t node_guid_l[0x00020]; /* Node GUID[31:0], takes effect only if the NG bit is set 1946 Must be the same for both ports. */ 1947/* -------------- */ 1948 pseudo_bit_t system_image_guid_h[0x00020];/* System Image GUID[63:32], takes effect only if the SIG bit is set 1949 Must be the same for both ports. */ 1950/* -------------- */ 1951 pseudo_bit_t system_image_guid_l[0x00020];/* System Image GUID[31:0], takes effect only if the SIG bit is set 1952 Must be the same for both ports. */ 1953/* -------------- */ 1954 pseudo_bit_t reserved5[0x006c0]; 1955/* -------------- */ 1956}; 1957 1958/* Query Device Capablities #### michal - gdror fixed */ 1959 1960struct hermonprm_query_dev_cap_st { /* Little Endian */ 1961 pseudo_bit_t reserved0[0x00080]; 1962/* -------------- */ 1963 pseudo_bit_t log_max_qp[0x00005]; /* Log2 of the Maximum number of QPs supported */ 1964 pseudo_bit_t reserved1[0x00003]; 1965 pseudo_bit_t log2_rsvd_qps[0x00004];/* Log (base 2) of the number of QPs reserved for firmware use 1966 The reserved resources are numbered from 0 to 2^log2_rsvd_qps-1 */ 1967 pseudo_bit_t reserved2[0x00004]; 1968 pseudo_bit_t log_max_qp_sz[0x00008];/* The maximum number of WQEs allowed on the RQ or the SQ is 2^log_max_qp_sz-1 */ 1969 pseudo_bit_t log_max_srq_sz[0x00008];/* The maximum number of WQEs allowed on the SRQ is 2^log_max_srq_sz-1 */ 1970/* -------------- */ 1971 pseudo_bit_t log_max_scqs[0x00004]; /* log base 2 of number of supported schedule queues */ 1972 pseudo_bit_t reserved3[0x00004]; 1973 pseudo_bit_t num_rsvd_scqs[0x00006]; 1974 pseudo_bit_t reserved4[0x00002]; 1975 pseudo_bit_t log_max_srqs[0x00005]; 1976 pseudo_bit_t reserved5[0x00007]; 1977 pseudo_bit_t log2_rsvd_srqs[0x00004]; 1978/* -------------- */ 1979 pseudo_bit_t log_max_cq[0x00005]; /* Log2 of the Maximum number of CQs supported */ 1980 pseudo_bit_t reserved6[0x00003]; 1981 pseudo_bit_t log2_rsvd_cqs[0x00004];/* Log (base 2) of the number of CQs reserved for firmware use 1982 The reserved resources are numbered from 0 to 2^log2_rsrvd_cqs-1 */ 1983 pseudo_bit_t reserved7[0x00004]; 1984 pseudo_bit_t log_max_cq_sz[0x00008];/* Log2 of the Maximum CQEs allowed in a CQ */ 1985 pseudo_bit_t reserved8[0x00008]; 1986/* -------------- */ 1987 pseudo_bit_t log_max_eq[0x00004]; /* Log2 of the Maximum number of EQs */ 1988 pseudo_bit_t reserved9[0x00004]; 1989 pseudo_bit_t num_rsvd_eqs[0x00004]; /* The number of EQs reserved for firmware use 1990 The reserved resources are numbered from 0 to num_rsvd_eqs-1 1991 If 0 - no resources are reserved. */ 1992 pseudo_bit_t reserved10[0x00004]; 1993 pseudo_bit_t log_max_d_mpts[0x00006];/* Log (base 2) of the maximum number of data MPT entries (the number of Regions/Windows) */ 1994 pseudo_bit_t reserved11[0x00002]; 1995 pseudo_bit_t log_max_eq_sz[0x00008];/* Log2 of the Maximum EQEs allowed in a EQ */ 1996/* -------------- */ 1997 pseudo_bit_t log_max_mtts[0x00006]; /* Log2 of the Maximum number of MTT entries */ 1998 pseudo_bit_t reserved12[0x00002]; 1999 pseudo_bit_t log2_rsvd_mrws[0x00004];/* Log (base 2) of the number of MPTs reserved for firmware use 2000 The reserved resources are numbered from 0 to 2^log2_rsvd_mrws-1 */ 2001 pseudo_bit_t reserved13[0x00004]; 2002 pseudo_bit_t log_max_mrw_sz[0x00007];/* Log2 of the Maximum Size of Memory Region/Window. is it in PRM layout? */ 2003 pseudo_bit_t reserved14[0x00005]; 2004 pseudo_bit_t log2_rsvd_mtts[0x00004];/* Log (base 2) of the number of MTT entries reserved for firmware use 2005 The reserved resources are numbered from 0 to 2^log2_rsvd_mtts-1 2006 */ 2007/* -------------- */ 2008 pseudo_bit_t reserved15[0x00020]; 2009/* -------------- */ 2010 pseudo_bit_t log_max_ra_res_qp[0x00006];/* Log2 of the Maximum number of outstanding RDMA read/Atomic per QP as a responder */ 2011 pseudo_bit_t reserved16[0x0000a]; 2012 pseudo_bit_t log_max_ra_req_qp[0x00006];/* Log2 of the maximum number of outstanding RDMA read/Atomic per QP as a requester */ 2013 pseudo_bit_t reserved17[0x0000a]; 2014/* -------------- */ 2015 pseudo_bit_t log_max_ra_res_global[0x00006];/* Log2 of the maximum number of RDMA read/atomic operations the HCA responder can support globally. That implies the RDB table size. */ 2016 pseudo_bit_t reserved18[0x0001a]; 2017/* -------------- */ 2018 pseudo_bit_t rsz_srq[0x00001]; /* Ability to modify the maximum number of WRs per SRQ. */ 2019 pseudo_bit_t reserved19[0x0001f]; 2020/* -------------- */ 2021 pseudo_bit_t num_ports[0x00004]; /* Number of IB ports. */ 2022 pseudo_bit_t max_vl_ib[0x00004]; /* Maximum VLs supported on each port, excluding VL15 */ 2023 pseudo_bit_t ib_port_width[0x00004];/* IB Port Width 2024 1 - 1x 2025 3 - 1x, 4x 2026 11 - 1x, 4x or 12x 2027 else - Reserved */ 2028 pseudo_bit_t ib_mtu[0x00004]; /* Maximum MTU Supported 2029 0x0 - Reserved 2030 0x1 - 256 2031 0x2 - 512 2032 0x3 - 1024 2033 0x4 - 2048 2034 0x5 - 4096 2035 0x6-0xF Reserved */ 2036 pseudo_bit_t local_ca_ack_delay[0x00005];/* The Local CA ACK Delay. This is the value recommended to be returned in Query HCA verb. 2037 The delay value in microseconds is computed using 4.096us * 2^(local_ca_ack_delay). */ 2038 pseudo_bit_t port_type[0x00004]; /* Hermon New. bit per port. bit0 is first port. value '1' is ehternet. '0' is IB */ 2039 pseudo_bit_t reserved20[0x00004]; 2040 pseudo_bit_t w[0x00001]; /* Hermon New. 10GB eth support */ 2041 pseudo_bit_t j[0x00001]; /* Hermon New. Jumbo frame support */ 2042 pseudo_bit_t reserved21[0x00001]; 2043/* -------------- */ 2044 pseudo_bit_t log_max_gid[0x00004]; /* Log2 of the maximum number of GIDs per port */ 2045 pseudo_bit_t reserved22[0x00004]; 2046 pseudo_bit_t log_ethtype[0x00004]; /* Hermon New. log2 eth type table size */ 2047 pseudo_bit_t reserved23[0x00004]; 2048 pseudo_bit_t log_drain_size[0x00008];/* Log (base 2) of minimum size of the NoDropVLDrain buffer, specified in 4Kpages units */ 2049 pseudo_bit_t log_max_msg[0x00005]; /* Log (base 2) of the maximum message size supported by the device */ 2050 pseudo_bit_t reserved24[0x00003]; 2051/* -------------- */ 2052 pseudo_bit_t log_max_pkey[0x00004]; /* Log2 of the max PKey Table Size (per IB port) */ 2053 pseudo_bit_t reserved25[0x0000c]; 2054 pseudo_bit_t stat_rate_support[0x00010];/* bit mask of stat rate supported 2055 bit 0 - full bw 2056 bit 1 - 1/4 bw 2057 bit 2 - 1/8 bw 2058 bit 3 - 1/2 bw; */ 2059/* -------------- */ 2060 pseudo_bit_t reserved26[0x00020]; 2061/* -------------- */ 2062 pseudo_bit_t rc[0x00001]; /* RC Transport supported */ 2063 pseudo_bit_t uc[0x00001]; /* UC Transport Supported */ 2064 pseudo_bit_t ud[0x00001]; /* UD Transport Supported */ 2065 pseudo_bit_t src[0x00001]; /* SRC Transport Supported. Hermon New instead of RD. */ 2066 pseudo_bit_t rcm[0x00001]; /* Reliable Multicast support. Hermon New instead of IPv6 Transport Supported */ 2067 pseudo_bit_t fcoib[0x00001]; /* Hermon New */ 2068 pseudo_bit_t srq[0x00001]; /* SRQ is supported 2069 */ 2070 pseudo_bit_t checksum[0x00001]; /* IP over IB checksum is supported */ 2071 pseudo_bit_t pkv[0x00001]; /* PKey Violation Counter Supported */ 2072 pseudo_bit_t qkv[0x00001]; /* QKey Violation Coutner Supported */ 2073 pseudo_bit_t vmm[0x00001]; /* Hermon New */ 2074 pseudo_bit_t fcoe[0x00001]; 2075 pseudo_bit_t dpdp[0x00001]; /* Dual Port Different Protocols */ 2076 pseudo_bit_t raw_ethertype[0x00001]; 2077 pseudo_bit_t raw_ipv6[0x00001]; 2078 pseudo_bit_t blh[0x00001]; 2079 pseudo_bit_t mw[0x00001]; /* Memory windows supported */ 2080 pseudo_bit_t apm[0x00001]; /* Automatic Path Migration Supported */ 2081 pseudo_bit_t atm[0x00001]; /* Atomic operations supported (atomicity is guaranteed between QPs on this HCA) */ 2082 pseudo_bit_t rm[0x00001]; /* Raw Multicast Supported */ 2083 pseudo_bit_t avp[0x00001]; /* Address Vector Port checking supported */ 2084 pseudo_bit_t udm[0x00001]; /* UD Multicast Supported */ 2085 pseudo_bit_t reserved28[0x00002]; 2086 pseudo_bit_t pg[0x00001]; /* Paging on demand supported */ 2087 pseudo_bit_t r[0x00001]; /* Router mode supported */ 2088 pseudo_bit_t reserved29[0x00006]; 2089/* -------------- */ 2090 pseudo_bit_t log_pg_sz[0x00008]; /* Minimum system page size supported (log2). 2091 For proper operation it must be less than or equal the hosting platform (CPU) minimum page size. */ 2092 pseudo_bit_t reserved30[0x00008]; 2093 pseudo_bit_t uar_sz[0x00006]; /* UAR Area Size = 1MB * 2^uar_sz */ 2094 pseudo_bit_t reserved31[0x00006]; 2095 pseudo_bit_t num_rsvd_uars[0x00004];/* The number of UARs reserved for firmware use 2096 The reserved resources are numbered from 0 to num_reserved_uars-1 2097 Note that UAR number num_reserved_uars is always for the kernel. */ 2098/* -------------- */ 2099 pseudo_bit_t log_max_bf_pages[0x00006];/* Maximum number of BlueFlame pages is 2^log_max_bf_pages */ 2100 pseudo_bit_t reserved32[0x00002]; 2101 pseudo_bit_t log_max_bf_regs_per_page[0x00006];/* Maximum number of BlueFlame registers per page is 2^log_max_bf_regs_per_page. It may be that only the beginning of a page contains BlueFlame registers. */ 2102 pseudo_bit_t reserved33[0x00002]; 2103 pseudo_bit_t log_bf_reg_size[0x00005];/* BlueFlame register size in bytes is 2^log_bf_reg_size */ 2104 pseudo_bit_t reserved34[0x0000a]; 2105 pseudo_bit_t bf[0x00001]; /* If set to "1" then BlueFlame may be used. */ 2106/* -------------- */ 2107 pseudo_bit_t max_desc_sz_sq[0x00010];/* Max descriptor size in bytes for the send queue */ 2108 pseudo_bit_t max_sg_sq[0x00008]; /* The maximum S/G list elements in a SQ WQE (max_desc_sz/16 - 3) */ 2109 pseudo_bit_t reserved35[0x00008]; 2110/* -------------- */ 2111 pseudo_bit_t max_desc_sz_rq[0x00010];/* Max descriptor size in bytes for the receive queue */ 2112 pseudo_bit_t max_sg_rq[0x00008]; /* The maximum S/G list elements in a RQ WQE (max_desc_sz/16 - 3) */ 2113 pseudo_bit_t reserved36[0x00008]; 2114/* -------------- */ 2115 pseudo_bit_t reserved37[0x00001]; 2116 pseudo_bit_t fexch_base_mpt_31_25[0x00007];/* Hermon New. FC mpt base mpt number */ 2117 pseudo_bit_t fcp_ud_base_23_8[0x00010];/* Hermon New. FC ud QP base QPN */ 2118 pseudo_bit_t fexch_base_qp_23_16[0x00008];/* Hermon New. FC Exchange QP base QPN */ 2119/* -------------- */ 2120 pseudo_bit_t reserved38[0x00020]; 2121/* -------------- */ 2122 pseudo_bit_t log_max_mcg[0x00008]; /* Log2 of the maximum number of multicast groups */ 2123 pseudo_bit_t num_rsvd_mcgs[0x00004];/* The number of MGMs reserved for firmware use in the MGHT. 2124 The reserved resources are numbered from 0 to num_reserved_mcgs-1 2125 If 0 - no resources are reserved. */ 2126 pseudo_bit_t reserved39[0x00004]; 2127 pseudo_bit_t log_max_qp_mcg[0x00008];/* Log2 of the maximum number of QPs per multicast group */ 2128 pseudo_bit_t reserved40[0x00008]; 2129/* -------------- */ 2130 pseudo_bit_t log_max_srcds[0x00004];/* Log2 of the maximum number of SRC Domains */ 2131 pseudo_bit_t reserved41[0x00008]; 2132 pseudo_bit_t num_rsvd_scrds[0x00004];/* The number of SRCDs reserved for firmware use 2133 The reserved resources are numbered from 0 to num_reserved_rdds-1. 2134 If 0 - no resources are reserved. */ 2135 pseudo_bit_t log_max_pd[0x00005]; /* Log2 of the maximum number of PDs */ 2136 pseudo_bit_t reserved42[0x00007]; 2137 pseudo_bit_t num_rsvd_pds[0x00004]; /* The number of PDs reserved for firmware use 2138 The reserved resources are numbered from 0 to num_reserved_pds-1 2139 If 0 - no resources are reserved. */ 2140/* -------------- */ 2141 pseudo_bit_t reserved43[0x000c0]; 2142/* -------------- */ 2143 pseudo_bit_t qpc_entry_sz[0x00010]; /* QPC Entry Size for the device 2144 For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ 2145 pseudo_bit_t rdmardc_entry_sz[0x00010];/* RdmaRdC Entry Size for the device 2146 For the InfiniHost-III-EX MT25208 entry size is 256 bytes */ 2147/* -------------- */ 2148 pseudo_bit_t altc_entry_sz[0x00010];/* Extended QPC entry size for the device 2149 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 2150 pseudo_bit_t aux_entry_sz[0x00010]; /* Auxilary context entry size */ 2151/* -------------- */ 2152 pseudo_bit_t cqc_entry_sz[0x00010]; /* CQC entry size for the device 2153 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 2154 pseudo_bit_t eqc_entry_sz[0x00010]; /* EQ context entry size for the device 2155 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 2156/* -------------- */ 2157 pseudo_bit_t c_mpt_entry_sz[0x00010];/* cMPT entry size in Bytes for the device. 2158 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 2159 pseudo_bit_t srq_entry_sz[0x00010]; /* SRQ context entry size for the device 2160 For the InfiniHost-III-EX MT25208 entry size is 32 bytes */ 2161/* -------------- */ 2162 pseudo_bit_t d_mpt_entry_sz[0x00010];/* dMPT entry size in Bytes for the device. 2163 For the InfiniHost-III-EX MT25208 entry size is 64 bytes */ 2164 pseudo_bit_t mtt_entry_sz[0x00010]; /* MTT entry size in Bytes for the device. 2165 For the InfiniHost-III-EX MT25208 entry size is 8 bytes */ 2166/* -------------- */ 2167 pseudo_bit_t bmme[0x00001]; /* Base Memory Management Extension Support */ 2168 pseudo_bit_t win_type[0x00001]; /* Bound Type 2 Memory Window Association mechanism: 2169 0 - Type 2A - QP Number Association; or 2170 1 - Type 2B - QP Number and PD Association. */ 2171 pseudo_bit_t mps[0x00001]; /* Ability of this HCA to support multiple page sizes per Memory Region. */ 2172 pseudo_bit_t bl[0x00001]; /* Ability of this HCA to support Block List Physical Buffer Lists. */ 2173 pseudo_bit_t zb[0x00001]; /* Zero Based region/windows supported */ 2174 pseudo_bit_t lif[0x00001]; /* Ability of this HCA to support Local Invalidate Fencing. */ 2175 pseudo_bit_t reserved44[0x0001a]; 2176/* -------------- */ 2177 pseudo_bit_t resd_lkey[0x00020]; /* The value of the reserved Lkey for Base Memory Management Extension */ 2178/* -------------- */ 2179 pseudo_bit_t reserved45[0x00020]; 2180/* -------------- */ 2181 pseudo_bit_t max_icm_size_h[0x00020];/* Bits [63:32] of maximum ICM size InfiniHost III Ex support in bytes. */ 2182/* -------------- */ 2183 pseudo_bit_t max_icm_size_l[0x00020];/* Bits [31:0] of maximum ICM size InfiniHost III Ex support in bytes. */ 2184/* -------------- */ 2185 pseudo_bit_t reserved46[0x002c0]; 2186/* -------------- */ 2187}; 2188 2189/* QUERY_ADAPTER Parameters Block #### michal - gdror fixed */ 2190 2191struct hermonprm_query_adapter_st { /* Little Endian */ 2192 pseudo_bit_t reserved0[0x00080]; 2193/* -------------- */ 2194 pseudo_bit_t reserved1[0x00018]; 2195 pseudo_bit_t intapin[0x00008]; /* Driver should set this field to INTR value in the event queue in order to get Express interrupt messages. */ 2196/* -------------- */ 2197 pseudo_bit_t reserved2[0x00060]; 2198/* -------------- */ 2199 struct hermonprm_vsd_st vsd; /* ###michal- this field was replaced by 2 fields : vsd .1664; vsd(continued/psid .128; */ 2200/* -------------- */ 2201}; 2202 2203/* QUERY_FW Parameters Block #### michal - doesn't match PRM */ 2204 2205struct hermonprm_query_fw_st { /* Little Endian */ 2206 pseudo_bit_t fw_rev_major[0x00010]; /* Firmware Revision - Major */ 2207 pseudo_bit_t fw_pages[0x00010]; /* Amount of physical memory to be allocated for FW usage is in 4KByte pages. */ 2208/* -------------- */ 2209 pseudo_bit_t fw_rev_minor[0x00010]; /* Firmware Revision - Minor */ 2210 pseudo_bit_t fw_rev_subminor[0x00010];/* Firmware Sub-minor version (Patch level). */ 2211/* -------------- */ 2212 pseudo_bit_t cmd_interface_rev[0x00010];/* Command Interface Interpreter Revision ID */ 2213 pseudo_bit_t reserved0[0x00010]; 2214/* -------------- */ 2215 pseudo_bit_t log_max_outstanding_cmd[0x00008];/* Log2 of the maximum number of commands the HCR can support simultaneously */ 2216 pseudo_bit_t reserved1[0x00017]; 2217 pseudo_bit_t dt[0x00001]; /* Debug Trace Support 2218 0 - Debug trace is not supported 2219 1 - Debug trace is supported */ 2220/* -------------- */ 2221 pseudo_bit_t reserved2[0x00001]; 2222 pseudo_bit_t ccq[0x00001]; /* CCQ support */ 2223 pseudo_bit_t reserved3[0x00006]; 2224 pseudo_bit_t fw_seconds[0x00008]; /* FW timestamp - seconds. Dispalyed as Hexadecimal number */ 2225 pseudo_bit_t fw_minutes[0x00008]; /* FW timestamp - minutes. Dispalyed as Hexadecimal number */ 2226 pseudo_bit_t fw_hour[0x00008]; /* FW timestamp - hour. Dispalyed as Hexadecimal number */ 2227/* -------------- */ 2228 pseudo_bit_t fw_day[0x00008]; /* FW timestamp - day. Dispalyed as Hexadecimal number */ 2229 pseudo_bit_t fw_month[0x00008]; /* FW timestamp - month. Dispalyed as Hexadecimal number */ 2230 pseudo_bit_t fw_year[0x00010]; /* FW timestamp - year. Dispalyed as Hexadecimal number (e.g. 0x2005) */ 2231/* -------------- */ 2232 pseudo_bit_t reserved4[0x00040]; 2233/* -------------- */ 2234 pseudo_bit_t clr_int_base_offset_h[0x00020];/* Bits [63:32] of the Clear Interrupt registers offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */ 2235/* -------------- */ 2236 pseudo_bit_t clr_int_base_offset_l[0x00020];/* Bits [31:0] of the Clear Interrupt registers offset from clr_int_bar register in PCIaddress space. Points to a 64-bit register. */ 2237/* -------------- */ 2238 pseudo_bit_t reserved5[0x0001e]; 2239 pseudo_bit_t clr_int_bar[0x00002]; /* PCI base address register (BAR) where clr_int register is located. 2240 00 - BAR 0-1 2241 01 - BAR 2-3 2242 10 - BAR 4-5 2243 11 - Reserved 2244 The PCI BARs of ConnectX are 64 bit BARs. 2245 In ConnectX, clr_int register is located on BAR 0-1. */ 2246/* -------------- */ 2247 pseudo_bit_t reserved6[0x00020]; 2248/* -------------- */ 2249 pseudo_bit_t error_buf_offset_h[0x00020];/* Read Only buffer for catastrophic error reports (bits [63:32] of offset from error_buf_bar register in PCI address space.) */ 2250/* -------------- */ 2251 pseudo_bit_t error_buf_offset_l[0x00020];/* Read Only buffer for catastrophic error reports (bits [31:0] of offset from error_buf_bar register in PCI address space.) */ 2252/* -------------- */ 2253 pseudo_bit_t error_buf_size[0x00020];/* Size in words */ 2254/* -------------- */ 2255 pseudo_bit_t reserved7[0x0001e]; 2256 pseudo_bit_t error_buf_bar[0x00002];/* PCI base address register (BAR) where error_buf register is located. 2257 00 - BAR 0-1 2258 01 - BAR 2-3 2259 10 - BAR 4-5 2260 11 - Reserved 2261 The PCI BARs of ConnectX are 64 bit BARs. 2262 In ConnectX, error_buf register is located on BAR 0-1. */ 2263/* -------------- */ 2264 pseudo_bit_t reserved8[0x00600]; 2265/* -------------- */ 2266}; 2267 2268/* Memory Access Parameters for UD Address Vector Table */ 2269 2270struct hermonprm_udavtable_memory_parameters_st { /* Little Endian */ 2271 pseudo_bit_t l_key[0x00020]; /* L_Key used to access TPT */ 2272/* -------------- */ 2273 pseudo_bit_t pd[0x00018]; /* PD used by TPT for matching against PD of region entry being accessed. */ 2274 pseudo_bit_t reserved0[0x00005]; 2275 pseudo_bit_t xlation_en[0x00001]; /* When cleared, address is physical address and no translation will be done. When set, address is virtual. */ 2276 pseudo_bit_t reserved1[0x00002]; 2277/* -------------- */ 2278}; 2279 2280/* INIT_HCA & QUERY_HCA Parameters Block ####michal-doesn't match PRM (see differs below) new size in bytes:0x300 */ 2281 2282struct hermonprm_init_hca_st { /* Little Endian */ 2283 pseudo_bit_t reserved0[0x00018]; 2284 pseudo_bit_t version[0x00008]; 2285/* -------------- */ 2286 pseudo_bit_t reserved1[0x00040]; 2287/* -------------- */ 2288 pseudo_bit_t reserved2[0x00010]; 2289 pseudo_bit_t hca_core_clock[0x00010];/* Internal Clock freq in MHz */ 2290/* -------------- */ 2291 pseudo_bit_t router_qp[0x00018]; /* QP number for router mode (8 LSBits should be 0). Low order 8 bits are taken from the TClass field of the incoming packet. 2292 Valid only if RE bit is set */ 2293 pseudo_bit_t reserved3[0x00005]; 2294 pseudo_bit_t ipr2[0x00001]; /* Hermon New. IP router on port 2 */ 2295 pseudo_bit_t ipr1[0x00001]; /* Hermon New. IP router on port 1 */ 2296 pseudo_bit_t ibr[0x00001]; /* InfiniBand Router Mode */ 2297/* -------------- */ 2298 pseudo_bit_t udp[0x00001]; /* UD Port Check Enable 2299 0 - Port field in Address Vector is ignored 2300 1 - HCA will check the port field in AV entry (fetched for UD descriptor) against the Port of the UD QP executing the descriptor. */ 2301 pseudo_bit_t he[0x00001]; /* Host Endianess - Used for Atomic Operations 2302 0 - Host is Little Endian 2303 1 - Host is Big endian 2304 */ 2305 pseudo_bit_t reserved4[0x00001]; 2306 pseudo_bit_t ce[0x00001]; /* Checksum Enabled - when Set IPoverIB checksum generation & checking is enabled */ 2307 pseudo_bit_t reserved5[0x0001c]; 2308/* -------------- */ 2309 pseudo_bit_t reserved6[0x00040]; 2310/* -------------- */ 2311 struct hermonprm_qpcbaseaddr_st qpc_eec_cqc_eqc_rdb_parameters;/* ## michal - this field has chenged to - "qpc_cqc_eqc_parameters" - gdror, this is ok for now */ 2312/* -------------- */ 2313 pseudo_bit_t reserved7[0x00100]; 2314/* -------------- */ 2315 struct hermonprm_multicastparam_st multicast_parameters;/* ##michal- this field has chenged to - "IBUD/IPv6_multicast_parameters" - gdror - this is OK for now */ 2316/* -------------- */ 2317 pseudo_bit_t reserved8[0x00080]; 2318/* -------------- */ 2319 struct hermonprm_tptparams_st tpt_parameters; 2320/* -------------- */ 2321 pseudo_bit_t reserved9[0x00080]; 2322/* -------------- */ 2323 struct hermonprm_uar_params_st uar_parameters;/* UAR Parameters */ 2324/* -------------- */ 2325 pseudo_bit_t reserved10[0x00600]; 2326/* -------------- */ 2327}; 2328 2329/* Event Queue Context Table Entry #### michal - gdror fixed */ 2330 2331struct hermonprm_eqc_st { /* Little Endian */ 2332 pseudo_bit_t reserved0[0x00008]; 2333 pseudo_bit_t st[0x00004]; /* Event delivery state machine 2334 0x9 - Armed 2335 0xA - Fired 2336 0xB - Always_Armed (auto-rearm) 2337 other - reserved */ 2338 pseudo_bit_t reserved1[0x00005]; 2339 pseudo_bit_t oi[0x00001]; /* Oerrun ignore. 2340 If set, HW will not check EQ full condition when writing new EQEs. */ 2341 pseudo_bit_t ec[0x00001]; /* is set, all EQEs are written (coalesced) to first EQ entry */ 2342 pseudo_bit_t reserved2[0x00009]; 2343 pseudo_bit_t status[0x00004]; /* EQ status: 2344 0000 - OK 2345 1010 - EQ write failure 2346 Valid for the QUERY_EQ and HW2SW_EQ commands only */ 2347/* -------------- */ 2348 pseudo_bit_t reserved3[0x00020]; 2349/* -------------- */ 2350 pseudo_bit_t reserved4[0x00005]; 2351 pseudo_bit_t page_offset[0x00007]; /* offset bits[11:5] of first EQE in the EQ relative to the first page in memory region mapping this EQ */ 2352 pseudo_bit_t reserved5[0x00014]; 2353/* -------------- */ 2354 pseudo_bit_t reserved6[0x00018]; 2355 pseudo_bit_t log_eq_size[0x00005]; /* Log (base 2) of the EQ size (in entries). Maximum EQ size is 2^22 EQEs (max log_eq_size is 22) */ 2356 pseudo_bit_t reserved7[0x00003]; 2357/* -------------- */ 2358 pseudo_bit_t eq_max_count[0x00010]; /* Event Generation Moderation counter */ 2359 pseudo_bit_t eq_period[0x00010]; /* Event Generation moderation timed, microseconds */ 2360/* -------------- */ 2361 pseudo_bit_t intr[0x0000a]; /* MSI-X table entry index to be used to signal interrupts on this EQ. Reserved if MSI-X are not enabled in the PCI configuration header. */ 2362 pseudo_bit_t reserved8[0x00016]; 2363/* -------------- */ 2364 pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] relative to INIT_HCA.mtt_base_addr */ 2365 pseudo_bit_t reserved9[0x00010]; 2366 pseudo_bit_t log2_page_size[0x00006];/* Log (base 2) of MTT page size in units of 4KByte */ 2367 pseudo_bit_t reserved10[0x00002]; 2368/* -------------- */ 2369 pseudo_bit_t reserved11[0x00003]; 2370 pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] relative to INIT_HCA.mtt_base_addr */ 2371/* -------------- */ 2372 pseudo_bit_t reserved12[0x00040]; 2373/* -------------- */ 2374 pseudo_bit_t consumer_counter[0x00018];/* Consumer counter. The counter is incremented for each EQE polled from the EQ. 2375 Must be 0x0 in EQ initialization. 2376 Maintained by HW (valid for the QUERY_EQ command only). */ 2377 pseudo_bit_t reserved13[0x00008]; 2378/* -------------- */ 2379 pseudo_bit_t producer_counter[0x00018];/* Producer Coutner. The counter is incremented for each EQE that is written by the HW to the EQ. 2380 EQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a EQE needs to be added. 2381 Maintained by HW (valid for the QUERY_EQ command only) */ 2382 pseudo_bit_t reserved14[0x00008]; 2383/* -------------- */ 2384 pseudo_bit_t reserved15[0x00080]; 2385/* -------------- */ 2386}; 2387 2388/* Memory Translation Table (MTT) Entry #### michal - match to PRM */ 2389 2390struct hermonprm_mtt_st { /* Little Endian */ 2391 pseudo_bit_t ptag_h[0x00020]; /* High-order bits of physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ 2392/* -------------- */ 2393 pseudo_bit_t p[0x00001]; /* Present bit. If set, page entry is valid. If cleared, access to this page will generate non-present page access fault. */ 2394 pseudo_bit_t reserved0[0x00002]; 2395 pseudo_bit_t ptag_l[0x0001d]; /* Low-order bits of Physical tag. The size of the field depends on the page size of the region. Maximum PTAG size is 52 bits. */ 2396/* -------------- */ 2397}; 2398 2399/* Memory Protection Table (MPT) Entry ### doesn't match PRM (new fields were added). new size in bytes : 0x54 */ 2400 2401struct hermonprm_mpt_st { /* Little Endian */ 2402 pseudo_bit_t reserved0[0x00008]; 2403 pseudo_bit_t r_w[0x00001]; /* Defines whether this entry is Region (1) or Window (0) */ 2404 pseudo_bit_t pa[0x00001]; /* Physical address. If set, no virtual-to-physical address translation is performed for this region */ 2405 pseudo_bit_t lr[0x00001]; /* If set - local read access is enabled. Must be set for all MPT Entries. */ 2406 pseudo_bit_t lw[0x00001]; /* If set - local write access is enabled */ 2407 pseudo_bit_t rr[0x00001]; /* If set - remote read access is enabled. */ 2408 pseudo_bit_t rw[0x00001]; /* If set - remote write access is enabled */ 2409 pseudo_bit_t atomic[0x00001]; /* If set - remote Atomic access is allowed. */ 2410 pseudo_bit_t eb[0x00001]; /* If set - bind is enabled. Valid only for regions. */ 2411 pseudo_bit_t atc_req[0x00001]; /* If set, second hop of address translation (PA to MA) to be performed in the device prior to issuing the uplink request. */ 2412 pseudo_bit_t atc_xlated[0x00001]; /* If set, uplink cycle to be issues with ATC_translated indicator to force bypass of the chipset IOMMU. */ 2413 pseudo_bit_t reserved1[0x00001]; 2414 pseudo_bit_t no_snoop[0x00001]; /* If set, issue PCIe cycle with ûno Snoopÿ attribute - cycle not to be snooped in CPU caches */ 2415 pseudo_bit_t reserved2[0x00008]; 2416 pseudo_bit_t status[0x00004]; /* 0xF - Not Valid 0x3 - Free. else - HW ownership.Unbound Type1 windows are denoted by reg_wnd_len=0. Unbound Type II windows are denoted by Status = Free. */ 2417/* -------------- */ 2418 pseudo_bit_t reserved3[0x00007]; 2419 pseudo_bit_t bqp[0x00001]; /* 0 - not bound to qp (type 1 window, MR)1 - bound to qp (type 2 window) */ 2420 pseudo_bit_t qpn[0x00018]; /* QP number this MW is attached to. Valid for type2 memory windows and on QUERY_MPT only */ 2421/* -------------- */ 2422 pseudo_bit_t mem_key[0x00020]; /* The memory Key. The field holds the mem_key field in the following semantics: {key[7:0],key[31:8]}. */ 2423/* -------------- */ 2424 pseudo_bit_t pd[0x00018]; /* Protection Domain. If VMM support is enabled PD[17:23] specify Guest VM Identifier */ 2425 pseudo_bit_t en_rinv[0x00001]; /* Enable remote invalidation */ 2426 pseudo_bit_t ei[0x00001]; /* Enable Invalidation - When set, Local/Remote invalidation can be executed on this window/region. Must be set for type2 windows and non-shared physical memory regions. Must be clear for regions that are used to access Work Queues, Completion Queues and Event Queues */ 2427 pseudo_bit_t nce[0x00001]; /* Data can be cached in Network Cache (see ûNetwork Cacheÿ on page 81) */ 2428 pseudo_bit_t fre[0x00001]; /* When set, Fast Registration Operations can be executed on this region */ 2429 pseudo_bit_t rae[0x00001]; /* When set, remote access can be enabled on this region. Used when executing Fast Registration Work Request to validate that remote access rights can be granted to this MPT. If the bit is cleared, Fast Registration Work Request requesting remote access rights will fail */ 2430 pseudo_bit_t w_dif[0x00001]; /* Wire space contains dif */ 2431 pseudo_bit_t m_dif[0x00001]; /* Memory space contains dif */ 2432 pseudo_bit_t reserved4[0x00001]; 2433/* -------------- */ 2434 pseudo_bit_t start_addr_h[0x00020]; /* Start Address - Virtual Address where this region/window starts */ 2435/* -------------- */ 2436 pseudo_bit_t start_addr_l[0x00020]; /* Start Address - Virtual Address where this region/window starts */ 2437/* -------------- */ 2438 pseudo_bit_t len_h[0x00020]; /* Region/Window Length */ 2439/* -------------- */ 2440 pseudo_bit_t len_l[0x00020]; /* Region/Window Length */ 2441/* -------------- */ 2442 pseudo_bit_t lkey[0x00020]; /* Must be 0 for SW2HW_MPT. On QUERY_MPT and HW2SW_MPT commands for Memory Window it reflects the LKey of the Region that the Window is bound to.The field holds the lkey field in the following semantics: {key[7:0],key[31:8]}. */ 2443/* -------------- */ 2444 pseudo_bit_t win_cnt[0x00018]; /* Number of windows bound to this region. Valid for regions only.The field is valid only for the QUERY_MPT and HW2SW_MPT commands. */ 2445 pseudo_bit_t reserved5[0x00008]; 2446/* -------------- */ 2447 pseudo_bit_t mtt_rep[0x00004]; /* Log (base 2) of the number of time an MTT is replicated.E.g. for 64KB virtual blocks from 512B blocks, a replication factor of 2^7 is needed (MTT_REPLICATION_FACTOR=7).Up to 1MB of replicated block works */ 2448 pseudo_bit_t reserved6[0x00011]; 2449 pseudo_bit_t block_mode[0x00001]; /* If set, the page size is not power of two, and entity_size is in bytes. */ 2450 pseudo_bit_t len64[0x00001]; /* Region/Window Length[64]. This bit added to enable registering 2^64 bytes per region */ 2451 pseudo_bit_t fbo_en[0x00001]; /* If set, mtt_fbo field is valid, otherwise it is calculated from least significant bytes of the address. Must be set when mtt_rep is used or MPT is block-mode region */ 2452 pseudo_bit_t reserved7[0x00008]; 2453/* -------------- */ 2454 pseudo_bit_t mtt_adr_h[0x00008]; /* Offset to MTT list for this region. Must be aligned on 8 bytes. */ 2455 pseudo_bit_t reserved8[0x00018]; 2456/* -------------- */ 2457 pseudo_bit_t mtt_adr_l[0x00020]; /* Offset to MTT list for this region. Must be aligned on 8 bytes.###michal-relpaced with: RESERVED .3;mtt_adr_l .29; gdror - this is OK to leave it this way. */ 2458/* -------------- */ 2459 pseudo_bit_t mtt_size[0x00020]; /* Number of MTT entries allocated for this MR.When Fast Registration Operations cannot be executed on this region (FRE bit is zero) this field is reserved.When Fast Registration Operation is enabled (FRE bit is set) this field indicates the number of MTTs allocated for this MR. If mtt_sz value cannot be zero. */ 2460/* -------------- */ 2461 pseudo_bit_t entity_size[0x00015]; /* Page/block size. If MPT maps pages, the page size is 2entiry_size. If MPT maps blocks, the entity_size field specifies block size in bytes. The minimum amount of memory that can be mapped with single MTT is 512 bytes. */ 2462 pseudo_bit_t reserved9[0x0000b]; 2463/* -------------- */ 2464 pseudo_bit_t mtt_fbo[0x00015]; /* First byte offset in the zero-based region - the first byte within the first block/page start address refers to. When mtt_rep is being used, fbo points within the replicated block (i.e. block-size x 2^mtt_rep) */ 2465 pseudo_bit_t reserved10[0x0000b]; 2466/* -------------- */ 2467}; 2468 2469/* Completion Queue Context Table Entry #### michal - match PRM */ 2470 2471struct hermonprm_completion_queue_context_st { /* Little Endian */ 2472 pseudo_bit_t reserved0[0x00008]; 2473 pseudo_bit_t st[0x00004]; /* Event delivery state machine 2474 0x0 - reserved 2475 0x9 - ARMED (Request for Notification) 2476 0x6 - ARMED SOLICITED (Request Solicited Notification) 2477 0xA - FIRED 2478 other - reserved 2479 2480 Must be 0x0 in CQ initialization. 2481 Valid for the QUERY_CQ and HW2SW_CQ commands only. */ 2482 pseudo_bit_t reserved1[0x00005]; 2483 pseudo_bit_t oi[0x00001]; /* When set, overrun ignore is enabled. 2484 When set, Updates of CQ consumer counter (poll for completion) or Request completion notifications (Arm CQ) doorbells should not be rang on that CQ. */ 2485 pseudo_bit_t cc[0x00001]; /* is set, all CQEs are written (coalesced) to first CQ entry */ 2486 pseudo_bit_t reserved2[0x00009]; 2487 pseudo_bit_t status[0x00004]; /* CQ status 2488 0000 - OK 2489 1001 - CQ overflow 2490 1010 - CQ write failure 2491 Valid for the QUERY_CQ and HW2SW_CQ commands only */ 2492/* -------------- */ 2493 pseudo_bit_t reserved3[0x00020]; 2494/* -------------- */ 2495 pseudo_bit_t reserved4[0x00005]; 2496 pseudo_bit_t page_offset[0x00007]; /* offset of first CQE in the CQ relative to the first page in memory region mapping this CQ */ 2497 pseudo_bit_t reserved5[0x00014]; 2498/* -------------- */ 2499 pseudo_bit_t usr_page[0x00018]; /* UAR page this CQ can be accessed through (ringinig CQ doorbells) */ 2500 pseudo_bit_t log_cq_size[0x00005]; /* Log (base 2) of the CQ size (in entries). 2501 Maximum CQ size is 2^17 CQEs (max log_cq_size is 17) */ 2502 pseudo_bit_t reserved6[0x00003]; 2503/* -------------- */ 2504 pseudo_bit_t cq_max_count[0x00010]; /* Event Generation Moderation counter */ 2505 pseudo_bit_t cq_period[0x00010]; /* Event Generation moderation timed, microseconds */ 2506/* -------------- */ 2507 pseudo_bit_t c_eqn[0x00009]; /* Event Queue this CQ reports completion events to. 2508 Valid values are 0 to 63 2509 If configured to value other than 0-63, completion events will not be reported on the CQ. */ 2510 pseudo_bit_t reserved7[0x00017]; 2511/* -------------- */ 2512 pseudo_bit_t mtt_base_addr_h[0x00008];/* MTT Base Address [39:32] in ICM relative to INIT_HCA.mtt_base_addr */ 2513 pseudo_bit_t reserved8[0x00010]; 2514 pseudo_bit_t log2_page_size[0x00006]; 2515 pseudo_bit_t reserved9[0x00002]; 2516/* -------------- */ 2517 pseudo_bit_t reserved10[0x00003]; 2518 pseudo_bit_t mtt_base_addr_l[0x0001d];/* MTT Base Address [31:3] in ICM relative to INIT_HCA.mtt_base_addr */ 2519/* -------------- */ 2520 pseudo_bit_t last_notified_indx[0x00018];/* Maintained by HW. 2521 Valid for QUERY_CQ and HW2SW_CQ commands only. */ 2522 pseudo_bit_t reserved11[0x00008]; 2523/* -------------- */ 2524 pseudo_bit_t solicit_producer_indx[0x00018];/* Maintained by HW. 2525 Valid for QUERY_CQ and HW2SW_CQ commands only. 2526 */ 2527 pseudo_bit_t reserved12[0x00008]; 2528/* -------------- */ 2529 pseudo_bit_t consumer_counter[0x00018];/* Consumer counter is a 32bits counter that is incremented for each CQE pooled from the CQ. 2530 */ 2531 pseudo_bit_t reserved13[0x00008]; 2532/* -------------- */ 2533 pseudo_bit_t producer_counter[0x00018];/* Producer counter is a 32bits counter that is incremented for each CQE that is written by the HW to the CQ. 2534 CQ overrun is reported if Producer_counter + 1 equals to Consumer_counter and a CQE needs to be added.. 2535 Maintained by HW (valid for the QUERY_CQ and HW2SW_CQ commands only) */ 2536 pseudo_bit_t reserved14[0x00008]; 2537/* -------------- */ 2538 pseudo_bit_t reserved15[0x00020]; 2539/* -------------- */ 2540 pseudo_bit_t reserved16[0x00020]; 2541/* -------------- */ 2542 pseudo_bit_t db_record_addr_h[0x00020];/* CQ DB Record physical address [63:32] */ 2543/* -------------- */ 2544 pseudo_bit_t reserved17[0x00003]; 2545 pseudo_bit_t db_record_addr_l[0x0001d];/* CQ DB Record physical address [31:3] */ 2546/* -------------- */ 2547}; 2548 2549/* GPIO_event_data #### michal - gdror fixed */ 2550 2551struct hermonprm_gpio_event_data_st { /* Little Endian */ 2552 pseudo_bit_t reserved0[0x00060]; 2553/* -------------- */ 2554 pseudo_bit_t gpio_event_hi[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ 2555/* -------------- */ 2556 pseudo_bit_t gpio_event_lo[0x00020];/* If any bit is set to 1, then a rising/falling event has occurred on the corrsponding GPIO pin. */ 2557/* -------------- */ 2558 pseudo_bit_t reserved1[0x00020]; 2559/* -------------- */ 2560}; 2561 2562/* Event_data Field - QP/EE Events #### michal - doesn't match PRM */ 2563 2564struct hermonprm_qp_ee_event_st { /* Little Endian */ 2565 pseudo_bit_t qpn_een[0x00018]; /* QP/EE/SRQ number event is reported for ###michal - field changed to QP number */ 2566 pseudo_bit_t reserved0[0x00008]; 2567/* -------------- */ 2568 pseudo_bit_t reserved1[0x00020]; 2569/* -------------- */ 2570 pseudo_bit_t reserved2[0x0001c]; 2571 pseudo_bit_t e_q[0x00001]; /* If set - EEN if cleared - QP in the QPN/EEN field 2572 Not valid on SRQ events ###michal - field replaced with RESERVED */ 2573 pseudo_bit_t reserved3[0x00003]; 2574/* -------------- */ 2575 pseudo_bit_t reserved4[0x00060]; 2576/* -------------- */ 2577}; 2578 2579/* InfiniHost-III-EX Type0 Configuration Header ####michal - doesn't match PRM (new fields added, see below) */ 2580 2581struct hermonprm_mt25208_type0_st { /* Little Endian */ 2582 pseudo_bit_t vendor_id[0x00010]; /* Hardwired to 0x15B3 */ 2583 pseudo_bit_t device_id[0x00010]; /* 25208 (decimal) - InfiniHost-III compatible mode 2584 25408 (decimal) - InfiniHost-III EX mode (the mode described in this manual) 2585 25209 (decimal) - Flash burner mode - see Flash burning application note for further details on this mode 2586 */ 2587/* -------------- */ 2588 pseudo_bit_t command[0x00010]; /* PCI Command Register */ 2589 pseudo_bit_t status[0x00010]; /* PCI Status Register */ 2590/* -------------- */ 2591 pseudo_bit_t revision_id[0x00008]; 2592 pseudo_bit_t class_code_hca_class_code[0x00018]; 2593/* -------------- */ 2594 pseudo_bit_t cache_line_size[0x00008];/* Cache Line Size */ 2595 pseudo_bit_t latency_timer[0x00008]; 2596 pseudo_bit_t header_type[0x00008]; /* hardwired to zero */ 2597 pseudo_bit_t bist[0x00008]; 2598/* -------------- */ 2599 pseudo_bit_t bar0_ctrl[0x00004]; /* hard-wired to 0100 */ 2600 pseudo_bit_t reserved0[0x00010]; 2601 pseudo_bit_t bar0_l[0x0000c]; /* Lower bits of BAR0 (Device Configuration Space) */ 2602/* -------------- */ 2603 pseudo_bit_t bar0_h[0x00020]; /* Upper 32 bits of BAR0 (Device Configuration Space) */ 2604/* -------------- */ 2605 pseudo_bit_t bar1_ctrl[0x00004]; /* Hardwired to 1100 */ 2606 pseudo_bit_t reserved1[0x00010]; 2607 pseudo_bit_t bar1_l[0x0000c]; /* Lower bits of BAR1 (User Access Region - UAR - space) */ 2608/* -------------- */ 2609 pseudo_bit_t bar1_h[0x00020]; /* upper 32 bits of BAR1 (User Access Region - UAR - space) */ 2610/* -------------- */ 2611 pseudo_bit_t bar2_ctrl[0x00004]; /* Hardwired to 1100 */ 2612 pseudo_bit_t reserved2[0x00010]; 2613 pseudo_bit_t bar2_l[0x0000c]; /* Lower bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ 2614/* -------------- */ 2615 pseudo_bit_t bar2_h[0x00020]; /* Upper 32 bits of BAR2 - Local Attached Memory if present and enabled. Else zeroed. */ 2616/* -------------- */ 2617 pseudo_bit_t cardbus_cis_pointer[0x00020]; 2618/* -------------- */ 2619 pseudo_bit_t subsystem_vendor_id[0x00010];/* Specified by the device NVMEM configuration */ 2620 pseudo_bit_t subsystem_id[0x00010]; /* Specified by the device NVMEM configuration */ 2621/* -------------- */ 2622 pseudo_bit_t expansion_rom_enable[0x00001];/* Expansion ROM Enable. Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ 2623 pseudo_bit_t reserved3[0x0000a]; 2624 pseudo_bit_t expansion_rom_base_address[0x00015];/* Expansion ROM Base Address (upper 21 bit). Hardwired to 0 if expansion ROM is disabled in the device NVMEM configuration. */ 2625/* -------------- */ 2626 pseudo_bit_t capabilities_pointer[0x00008];/* Specified by the device NVMEM configuration */ 2627 pseudo_bit_t reserved4[0x00018]; 2628/* -------------- */ 2629 pseudo_bit_t reserved5[0x00020]; 2630/* -------------- */ 2631 pseudo_bit_t interrupt_line[0x00008]; 2632 pseudo_bit_t interrupt_pin[0x00008]; 2633 pseudo_bit_t min_gnt[0x00008]; 2634 pseudo_bit_t max_latency[0x00008]; 2635/* -------------- */ 2636 pseudo_bit_t reserved6[0x00100]; 2637/* -------------- */ 2638 pseudo_bit_t msi_cap_id[0x00008]; 2639 pseudo_bit_t msi_next_cap_ptr[0x00008]; 2640 pseudo_bit_t msi_en[0x00001]; 2641 pseudo_bit_t multiple_msg_cap[0x00003]; 2642 pseudo_bit_t multiple_msg_en[0x00003]; 2643 pseudo_bit_t cap_64_bit_addr[0x00001]; 2644 pseudo_bit_t reserved7[0x00008]; 2645/* -------------- */ 2646 pseudo_bit_t msg_addr_l[0x00020]; 2647/* -------------- */ 2648 pseudo_bit_t msg_addr_h[0x00020]; 2649/* -------------- */ 2650 pseudo_bit_t msg_data[0x00010]; 2651 pseudo_bit_t reserved8[0x00010]; 2652/* -------------- */ 2653 pseudo_bit_t reserved9[0x00080]; 2654/* -------------- */ 2655 pseudo_bit_t pm_cap_id[0x00008]; /* Power management capability ID - 01h */ 2656 pseudo_bit_t pm_next_cap_ptr[0x00008]; 2657 pseudo_bit_t pm_cap[0x00010]; /* [2:0] Version - 02h 2658 [3] PME clock - 0h 2659 [4] RsvP 2660 [5] Device specific initialization - 0h 2661 [8:6] AUX current - 0h 2662 [9] D1 support - 0h 2663 [10] D2 support - 0h 2664 [15:11] PME support - 0h */ 2665/* -------------- */ 2666 pseudo_bit_t pm_status_control[0x00010];/* [14:13] - Data scale - 0h */ 2667 pseudo_bit_t pm_control_status_brdg_ext[0x00008]; 2668 pseudo_bit_t data[0x00008]; 2669/* -------------- */ 2670 pseudo_bit_t reserved10[0x00040]; 2671/* -------------- */ 2672 pseudo_bit_t vpd_cap_id[0x00008]; /* 03h */ 2673 pseudo_bit_t vpd_next_cap_id[0x00008]; 2674 pseudo_bit_t vpd_address[0x0000f]; 2675 pseudo_bit_t f[0x00001]; 2676/* -------------- */ 2677 pseudo_bit_t vpd_data[0x00020]; 2678/* -------------- */ 2679 pseudo_bit_t reserved11[0x00040]; 2680/* -------------- */ 2681 pseudo_bit_t pciex_cap_id[0x00008]; /* PCI-Express capability ID - 10h */ 2682 pseudo_bit_t pciex_next_cap_ptr[0x00008]; 2683 pseudo_bit_t pciex_cap[0x00010]; /* [3:0] Capability version - 1h 2684 [7:4] Device/Port Type - 0h 2685 [8] Slot implemented - 0h 2686 [13:9] Interrupt message number 2687 */ 2688/* -------------- */ 2689 pseudo_bit_t device_cap[0x00020]; /* [2:0] Max_Payload_Size supported - 2h 2690 [4:3] Phantom Function supported - 0h 2691 [5] Extended Tag Filed supported - 0h 2692 [8:6] Endpoint L0s Acceptable Latency - TBD 2693 [11:9] Endpoint L1 Acceptable Latency - TBD 2694 [12] Attention Button Present - configured through InfiniBurn 2695 [13] Attention Indicator Present - configured through InfiniBurn 2696 [14] Power Indicator Present - configured through InfiniBurn 2697 [25:18] Captured Slot Power Limit Value 2698 [27:26] Captured Slot Power Limit Scale */ 2699/* -------------- */ 2700 pseudo_bit_t device_control[0x00010]; 2701 pseudo_bit_t device_status[0x00010]; 2702/* -------------- */ 2703 pseudo_bit_t link_cap[0x00020]; /* [3:0] Maximum Link Speed - 1h 2704 [9:4] Maximum Link Width - 8h 2705 [11:10] Active State Power Management Support - 3h 2706 [14:12] L0s Exit Latency - TBD 2707 [17:15] L1 Exit Latency - TBD 2708 [31:24] Port Number - 0h */ 2709/* -------------- */ 2710 pseudo_bit_t link_control[0x00010]; 2711 pseudo_bit_t link_status[0x00010]; /* [3:0] Link Speed - 1h 2712 [9:4] Negotiated Link Width 2713 [12] Slot clock configuration - 1h */ 2714/* -------------- */ 2715 pseudo_bit_t reserved12[0x00260]; 2716/* -------------- */ 2717 pseudo_bit_t advanced_error_reporting_cap_id[0x00010];/* 0001h. */ 2718 pseudo_bit_t capability_version[0x00004];/* 1h */ 2719 pseudo_bit_t next_capability_offset[0x0000c];/* 0h */ 2720/* -------------- */ 2721 pseudo_bit_t uncorrectable_error_status_register[0x00020];/* 0 Training Error Status 2722 4 Data Link Protocol Error Status 2723 12 Poisoned TLP Status 2724 13 Flow Control Protocol Error Status 2725 14 Completion Timeout Status 2726 15 Completer Abort Status 2727 16 Unexpected Completion Status 2728 17 Receiver Overflow Status 2729 18 Malformed TLP Status 2730 19 ECRC Error Status 2731 20 Unsupported Request Error Status */ 2732/* -------------- */ 2733 pseudo_bit_t uncorrectable_error_mask_register[0x00020];/* 0 Training Error Mask 2734 4 Data Link Protocol Error Mask 2735 12 Poisoned TLP Mask 2736 13 Flow Control Protocol Error Mask 2737 14 Completion Timeout Mask 2738 15 Completer Abort Mask 2739 16 Unexpected Completion Mask 2740 17 Receiver Overflow Mask 2741 18 Malformed TLP Mask 2742 19 ECRC Error Mask 2743 20 Unsupported Request Error Mask */ 2744/* -------------- */ 2745 pseudo_bit_t uncorrectable_severity_mask_register[0x00020];/* 0 Training Error Severity 2746 4 Data Link Protocol Error Severity 2747 12 Poisoned TLP Severity 2748 13 Flow Control Protocol Error Severity 2749 14 Completion Timeout Severity 2750 15 Completer Abort Severity 2751 16 Unexpected Completion Severity 2752 17 Receiver Overflow Severity 2753 18 Malformed TLP Severity 2754 19 ECRC Error Severity 2755 20 Unsupported Request Error Severity */ 2756/* -------------- */ 2757 pseudo_bit_t correctable_error_status_register[0x00020];/* 0 Receiver Error Status 2758 6 Bad TLP Status 2759 7 Bad DLLP Status 2760 8 REPLAY_NUM Rollover Status 2761 12 Replay Timer Timeout Status */ 2762/* -------------- */ 2763 pseudo_bit_t correctable_error_mask_register[0x00020];/* 0 Receiver Error Mask 2764 6 Bad TLP Mask 2765 7 Bad DLLP Mask 2766 8 REPLAY_NUM Rollover Mask 2767 12 Replay Timer Timeout Mask */ 2768/* -------------- */ 2769 pseudo_bit_t advance_error_capabilities_and_control_register[0x00020]; 2770/* -------------- */ 2771 struct hermonprm_header_log_register_st header_log_register; 2772/* -------------- */ 2773 pseudo_bit_t reserved13[0x006a0]; 2774/* -------------- */ 2775}; 2776 2777/* Event Data Field - Performance Monitor */ 2778 2779struct hermonprm_performance_monitor_event_st { /* Little Endian */ 2780 struct hermonprm_performance_monitors_st performance_monitor_snapshot;/* Performance monitor snapshot */ 2781/* -------------- */ 2782 pseudo_bit_t monitor_number[0x00008];/* 0x01 - SQPC 2783 0x02 - RQPC 2784 0x03 - CQC 2785 0x04 - Rkey 2786 0x05 - TLB 2787 0x06 - port0 2788 0x07 - port1 */ 2789 pseudo_bit_t reserved0[0x00018]; 2790/* -------------- */ 2791 pseudo_bit_t reserved1[0x00040]; 2792/* -------------- */ 2793}; 2794 2795/* Event_data Field - Page Faults */ 2796 2797struct hermonprm_page_fault_event_data_st { /* Little Endian */ 2798 pseudo_bit_t va_h[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ 2799/* -------------- */ 2800 pseudo_bit_t va_l[0x00020]; /* Virtual Address[63:32] this page fault is reported on */ 2801/* -------------- */ 2802 pseudo_bit_t mem_key[0x00020]; /* Memory Key this page fault is reported on */ 2803/* -------------- */ 2804 pseudo_bit_t qp[0x00018]; /* QP this page fault is reported on */ 2805 pseudo_bit_t reserved0[0x00003]; 2806 pseudo_bit_t a[0x00001]; /* If set the memory access that caused the page fault was atomic */ 2807 pseudo_bit_t lw[0x00001]; /* If set the memory access that caused the page fault was local write */ 2808 pseudo_bit_t lr[0x00001]; /* If set the memory access that caused the page fault was local read */ 2809 pseudo_bit_t rw[0x00001]; /* If set the memory access that caused the page fault was remote write */ 2810 pseudo_bit_t rr[0x00001]; /* If set the memory access that caused the page fault was remote read */ 2811/* -------------- */ 2812 pseudo_bit_t pd[0x00018]; /* PD this page fault is reported on */ 2813 pseudo_bit_t reserved1[0x00008]; 2814/* -------------- */ 2815 pseudo_bit_t prefetch_len[0x00020]; /* Indicates how many subsequent pages in the same memory region/window will be accessed by the following transaction after this page fault is resolved. measured in bytes. SW can use this information in order to page-in the subsequent pages if they are not present. */ 2816/* -------------- */ 2817}; 2818 2819/* WQE segments format */ 2820 2821struct hermonprm_wqe_segment_st { /* Little Endian */ 2822 struct hermonprm_send_wqe_segment_st send_wqe_segment;/* Send WQE segment format */ 2823/* -------------- */ 2824 pseudo_bit_t reserved0[0x00280]; 2825/* -------------- */ 2826 struct hermonprm_wqe_segment_ctrl_mlx_st mlx_wqe_segment_ctrl;/* MLX WQE segment format */ 2827/* -------------- */ 2828 pseudo_bit_t reserved1[0x00100]; 2829/* -------------- */ 2830 pseudo_bit_t recv_wqe_segment_ctrl[4][0x00020];/* Receive segment format */ 2831/* -------------- */ 2832 pseudo_bit_t reserved2[0x00080]; 2833/* -------------- */ 2834}; 2835 2836/* Event_data Field - Port State Change #### michal - match PRM */ 2837 2838struct hermonprm_port_state_change_st { /* Little Endian */ 2839 pseudo_bit_t reserved0[0x00040]; 2840/* -------------- */ 2841 pseudo_bit_t reserved1[0x0001c]; 2842 pseudo_bit_t p[0x00002]; /* Port number (1 or 2) */ 2843 pseudo_bit_t reserved2[0x00002]; 2844/* -------------- */ 2845 pseudo_bit_t reserved3[0x00060]; 2846/* -------------- */ 2847}; 2848 2849/* Event_data Field - Completion Queue Error #### michal - match PRM */ 2850 2851struct hermonprm_completion_queue_error_st { /* Little Endian */ 2852 pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ 2853 pseudo_bit_t reserved0[0x00008]; 2854/* -------------- */ 2855 pseudo_bit_t reserved1[0x00020]; 2856/* -------------- */ 2857 pseudo_bit_t syndrome[0x00008]; /* Error syndrome 2858 0x01 - CQ overrun 2859 0x02 - CQ access violation error */ 2860 pseudo_bit_t reserved2[0x00018]; 2861/* -------------- */ 2862 pseudo_bit_t reserved3[0x00060]; 2863/* -------------- */ 2864}; 2865 2866/* Event_data Field - Completion Event #### michal - match PRM */ 2867 2868struct hermonprm_completion_event_st { /* Little Endian */ 2869 pseudo_bit_t cqn[0x00018]; /* CQ number event is reported for */ 2870 pseudo_bit_t reserved0[0x00008]; 2871/* -------------- */ 2872 pseudo_bit_t reserved1[0x000a0]; 2873/* -------------- */ 2874}; 2875 2876/* Event Queue Entry #### michal - match to PRM */ 2877 2878struct hermonprm_event_queue_entry_st { /* Little Endian */ 2879 pseudo_bit_t event_sub_type[0x00008];/* Event Sub Type. 2880 Defined for events which have sub types, zero elsewhere. */ 2881 pseudo_bit_t reserved0[0x00008]; 2882 pseudo_bit_t event_type[0x00008]; /* Event Type */ 2883 pseudo_bit_t reserved1[0x00008]; 2884/* -------------- */ 2885 pseudo_bit_t event_data[6][0x00020];/* Delivers auxilary data to handle event. */ 2886/* -------------- */ 2887 pseudo_bit_t reserved2[0x00007]; 2888 pseudo_bit_t owner[0x00001]; /* Owner of the entry 2889 0 SW 2890 1 HW */ 2891 pseudo_bit_t reserved3[0x00018]; 2892/* -------------- */ 2893}; 2894 2895/* QP/EE State Transitions Command Parameters ###michal - doesn't match PRM (field name changed) */ 2896 2897struct hermonprm_qp_ee_state_transitions_st { /* Little Endian */ 2898 pseudo_bit_t opt_param_mask[0x00020];/* This field defines which optional parameters are passed. Each bit specifies whether optional parameter is passed (set) or not (cleared). The optparammask is defined for each QP/EE command. */ 2899/* -------------- */ 2900 pseudo_bit_t reserved0[0x00020]; 2901/* -------------- */ 2902 struct hermonprm_queue_pair_ee_context_entry_st qpc_eec_data;/* QPC/EEC data ###michal - field has replaced with "qpc_data" (size .1948) */ 2903/* -------------- */ 2904 pseudo_bit_t reserved1[0x00800]; 2905/* -------------- */ 2906}; 2907 2908/* Completion Queue Entry Format #### michal - fixed by gdror */ 2909 2910struct hermonprm_completion_queue_entry_st { /* Little Endian */ 2911 pseudo_bit_t qpn[0x00018]; /* Indicates the QP for which completion is being reported */ 2912 pseudo_bit_t reserved0[0x00002]; 2913 pseudo_bit_t d2s[0x00001]; /* Duplicate to Sniffer. This bit is set if both Send and Receive queues are subject for sniffer queue. The HW delivers 2914 packet only to send-associated sniffer receive queue. */ 2915 pseudo_bit_t fcrc_sd[0x00001]; /* FCRC: If set, FC CRC is correct in FC frame encapsulated in payload. Valid for Raw Frame FC receive queue only. 2916 SD: CQ associated with Sniffer receive queue. If set, packets were skipped due to lack of receive buffers on the Sniffer receive queue */ 2917 pseudo_bit_t fl[0x00001]; /* Force Loopback Valid for responder RawEth and UD only. */ 2918 pseudo_bit_t vlan[0x00002]; /* Valid for RawEth and UD over Ethernet only. Applicable for RawEth and UD over Ethernet Receive queue 2919 00 - No VLAN header was present in the packet 2920 01 - C-VLAN (802.1q) Header was present in the frame. 2921 10 - S-VLAN (802.1ad) Header was present in the frame. */ 2922 pseudo_bit_t dife[0x00001]; /* DIF Error */ 2923/* -------------- */ 2924 pseudo_bit_t immediate_rssvalue_invalidatekey[0x00020];/* For a responder CQE, if completed WQE Opcode is Send With Immediate or Write With Immediate, this field contains immediate field of the received message. 2925 For a responder CQE, if completed WQE Opcode is Send With Invalidate, this field contains the R_key that was invalidated. 2926 For a responder CQE of a GSI packet this filed contains the Pkey Index of the packet. 2927 For IPoIB (UD) and RawEth CQEs this field contains the RSS hash function value. 2928 Otherwise, this field is reserved. */ 2929/* -------------- */ 2930 pseudo_bit_t srq_rqpn[0x00018]; /* For Responder UD QPs, Remote (source) QP number. 2931 For Responder SRC QPs, SRQ number. 2932 Otherwise, this field is reserved. */ 2933 pseudo_bit_t ml_path_mac_index[0x00007];/* For responder UD over IB CQE: These are the lower LMC bits of the DLID in an incoming UD packet, higher bits of this field, that are not part of the LMC bits are zeroed by HW. Invalid if incoming message DLID is the permissive LID or incoming message is multicast. 2934 For responder UD over Ethernet and RawEth CQEs: Index of the MAC Table entry that the packet DMAC was matched against. 2935 Otherwise, this field is reserved. */ 2936 pseudo_bit_t g[0x00001]; /* For responder UD over IB CQE this bit indicates the presence of a GRH 2937 For responder UD over Ethernet CQE this bit is set if IPv6 L3 header was present in the packet, this bit is cleared if IPv4 L3 Header was present in the packet. 2938 Otherwise, this field is reserved. */ 2939/* -------------- */ 2940 pseudo_bit_t slid_smac47_32[0x00010];/* For responder UD over IB CQE it is the source LID of the packet. 2941 For responder UD over Ethernet and RawEth CQEs it is the source-MAC[47:32] of the packet. 2942 Otherwise, this field is reserved. */ 2943 pseudo_bit_t vid[0x0000c]; /* Frame VID, valid for Responder Raw Ethernet and UD over Ethernet QP. Otherwise, this field is reserved. */ 2944 pseudo_bit_t sl[0x00004]; /* For responder UD over IB - the Service Level of the packet. 2945 For responder UD over Ethernet and RawEth - it is VLAN-header[15:12] 2946 Otherwise, this field is reserved. */ 2947/* -------------- */ 2948 pseudo_bit_t smac31_0_rawether_ipoib_status[0x00020];/* For responder UD over Ethernet - source MAC[31:0] of the packet. 2949 For responder RawEth and UD over IB - RawEth-IPoIB status {3 reserved, ipok,udp,tcp,ipv4opt,ipv6,ipv4vf,ipv4,rht(6),ipv6extmask(6),reserved(2),l2am,reserved(2),bfcs,reserved(2),enc} 2950 Otherwise, this field is reserved. */ 2951/* -------------- */ 2952 pseudo_bit_t byte_cnt[0x00020]; /* Byte count of data transferred. Applicable for RDMA-read, Atomic and all receive operations. completions. 2953 For Receive Queue that is subject for headers. separation, byte_cnt[31:24] specify number of bytes scattered to the first scatter entry (headers. length). Byte_cnt[23:0] specify total byte count received (including headers). */ 2954/* -------------- */ 2955 pseudo_bit_t checksum[0x00010]; /* Valid for RawEth and IPoIB only. */ 2956 pseudo_bit_t wqe_counter[0x00010]; 2957/* -------------- */ 2958 pseudo_bit_t opcode[0x00005]; /* Send completions - same encoding as WQE. 2959 Error coding is 0x1F 2960 Receive: 2961 0x0 - RDMA-Write with Immediate 2962 0x1 - Send 2963 0x2 - Send with Immediate 2964 0x3 - Send & Invalidate 2965 */ 2966 pseudo_bit_t is[0x00001]; /* inline scatter */ 2967 pseudo_bit_t s_r[0x00001]; /* send 1 / receive 0 */ 2968 pseudo_bit_t owner[0x00001]; /* HW Flips this bit for every CQ warp around. Initialized to Zero. */ 2969 pseudo_bit_t reserved1[0x00010]; 2970 pseudo_bit_t reserved2[0x00008]; 2971/* -------------- */ 2972}; 2973 2974/* */ 2975 2976struct hermonprm_mcg_qps_st { /* Little Endian */ 2977 struct hermonprm_mcg_qp_dw_st dw[128]; 2978/* -------------- */ 2979}; 2980 2981/* */ 2982 2983struct hermonprm_mcg_hdr_st { /* Little Endian */ 2984 pseudo_bit_t reserved0[0x00006]; 2985 pseudo_bit_t next_mcg[0x0001a]; 2986/* -------------- */ 2987 pseudo_bit_t members_count[0x00018]; 2988 pseudo_bit_t reserved1[0x00008]; 2989/* -------------- */ 2990 pseudo_bit_t reserved2[0x00020]; 2991/* -------------- */ 2992 pseudo_bit_t reserved3[0x00020]; 2993/* -------------- */ 2994 pseudo_bit_t gid3[0x00020]; 2995/* -------------- */ 2996 pseudo_bit_t gid2[0x00020]; 2997/* -------------- */ 2998 pseudo_bit_t gid1[0x00020]; 2999/* -------------- */ 3000 pseudo_bit_t gid0[0x00020]; 3001/* -------------- */ 3002}; 3003 3004/* */ 3005 3006struct hermonprm_sched_queue_context_st { /* Little Endian */ 3007 pseudo_bit_t policy[0x00003]; /* Schedule Queue Policy - 0 - LLSQ, 1 - GBSQ, 2 - BESQ */ 3008 pseudo_bit_t vl15[0x00001]; 3009 pseudo_bit_t sl[0x00004]; /* SL this Schedule Queue is associated with (if vl15 bit is 0) */ 3010 pseudo_bit_t port[0x00002]; /* Port this Schedule Queue is associated with */ 3011 pseudo_bit_t reserved0[0x00006]; 3012 pseudo_bit_t weight[0x00010]; /* Weight of this SchQ */ 3013/* -------------- */ 3014}; 3015 3016/* */ 3017 3018struct hermonprm_ecc_detect_event_data_st { /* Little Endian */ 3019 pseudo_bit_t reserved0[0x00080]; 3020/* -------------- */ 3021 pseudo_bit_t cause_lsb[0x00001]; 3022 pseudo_bit_t reserved1[0x00002]; 3023 pseudo_bit_t cause_msb[0x00001]; 3024 pseudo_bit_t reserved2[0x00002]; 3025 pseudo_bit_t err_rmw[0x00001]; 3026 pseudo_bit_t err_src_id[0x00003]; 3027 pseudo_bit_t err_da[0x00002]; 3028 pseudo_bit_t err_ba[0x00002]; 3029 pseudo_bit_t reserved3[0x00011]; 3030 pseudo_bit_t overflow[0x00001]; 3031/* -------------- */ 3032 pseudo_bit_t err_ra[0x00010]; 3033 pseudo_bit_t err_ca[0x00010]; 3034/* -------------- */ 3035}; 3036 3037/* Event_data Field - ECC Detection Event */ 3038 3039struct hermonprm_scrubbing_event_st { /* Little Endian */ 3040 pseudo_bit_t reserved0[0x00080]; 3041/* -------------- */ 3042 pseudo_bit_t cause_lsb[0x00001]; /* data integrity error cause: 3043 single ECC error in the 64bit lsb data, on the rise edge of the clock */ 3044 pseudo_bit_t reserved1[0x00002]; 3045 pseudo_bit_t cause_msb[0x00001]; /* data integrity error cause: 3046 single ECC error in the 64bit msb data, on the fall edge of the clock */ 3047 pseudo_bit_t reserved2[0x00002]; 3048 pseudo_bit_t err_rmw[0x00001]; /* transaction type: 3049 0 - read 3050 1 - read/modify/write */ 3051 pseudo_bit_t err_src_id[0x00003]; /* source of the transaction: 0x4 - PCI, other - internal or IB */ 3052 pseudo_bit_t err_da[0x00002]; /* Error DIMM address */ 3053 pseudo_bit_t err_ba[0x00002]; /* Error bank address */ 3054 pseudo_bit_t reserved3[0x00011]; 3055 pseudo_bit_t overflow[0x00001]; /* Fatal: ECC error FIFO overflow - ECC errors were detected, which may or may not have been corrected by InfiniHost-III-EX */ 3056/* -------------- */ 3057 pseudo_bit_t err_ra[0x00010]; /* Error row address */ 3058 pseudo_bit_t err_ca[0x00010]; /* Error column address */ 3059/* -------------- */ 3060}; 3061 3062/* */ 3063 3064struct hermonprm_eq_cmd_doorbell_st { /* Little Endian */ 3065 pseudo_bit_t reserved0[0x00020]; 3066/* -------------- */ 3067}; 3068 3069/* 0 */ 3070 3071struct hermonprm_hermon_prm_st { /* Little Endian */ 3072 struct hermonprm_completion_queue_entry_st completion_queue_entry;/* Completion Queue Entry Format */ 3073/* -------------- */ 3074 pseudo_bit_t reserved0[0x7ff00]; 3075/* -------------- */ 3076 struct hermonprm_qp_ee_state_transitions_st qp_ee_state_transitions;/* QP/EE State Transitions Command Parameters */ 3077/* -------------- */ 3078 pseudo_bit_t reserved1[0x7f000]; 3079/* -------------- */ 3080 struct hermonprm_event_queue_entry_st event_queue_entry;/* Event Queue Entry */ 3081/* -------------- */ 3082 pseudo_bit_t reserved2[0x7ff00]; 3083/* -------------- */ 3084 struct hermonprm_completion_event_st completion_event;/* Event_data Field - Completion Event */ 3085/* -------------- */ 3086 pseudo_bit_t reserved3[0x7ff40]; 3087/* -------------- */ 3088 struct hermonprm_completion_queue_error_st completion_queue_error;/* Event_data Field - Completion Queue Error */ 3089/* -------------- */ 3090 pseudo_bit_t reserved4[0x7ff40]; 3091/* -------------- */ 3092 struct hermonprm_port_state_change_st port_state_change;/* Event_data Field - Port State Change */ 3093/* -------------- */ 3094 pseudo_bit_t reserved5[0x7ff40]; 3095/* -------------- */ 3096 struct hermonprm_wqe_segment_st wqe_segment;/* WQE segments format */ 3097/* -------------- */ 3098 pseudo_bit_t reserved6[0x7f000]; 3099/* -------------- */ 3100 struct hermonprm_page_fault_event_data_st page_fault_event_data;/* Event_data Field - Page Faults */ 3101/* -------------- */ 3102 pseudo_bit_t reserved7[0x7ff40]; 3103/* -------------- */ 3104 struct hermonprm_performance_monitor_event_st performance_monitor_event;/* Event Data Field - Performance Monitor */ 3105/* -------------- */ 3106 pseudo_bit_t reserved8[0xfff20]; 3107/* -------------- */ 3108 struct hermonprm_mt25208_type0_st mt25208_type0;/* InfiniHost-III-EX Type0 Configuration Header */ 3109/* -------------- */ 3110 pseudo_bit_t reserved9[0x7f000]; 3111/* -------------- */ 3112 struct hermonprm_qp_ee_event_st qp_ee_event;/* Event_data Field - QP/EE Events */ 3113/* -------------- */ 3114 pseudo_bit_t reserved10[0x00040]; 3115/* -------------- */ 3116 struct hermonprm_gpio_event_data_st gpio_event_data; 3117/* -------------- */ 3118 pseudo_bit_t reserved11[0x7fe40]; 3119/* -------------- */ 3120 struct hermonprm_ud_address_vector_st ud_address_vector;/* UD Address Vector */ 3121/* -------------- */ 3122 pseudo_bit_t reserved12[0x7ff00]; 3123/* -------------- */ 3124 struct hermonprm_queue_pair_ee_context_entry_st queue_pair_ee_context_entry;/* QP and EE Context Entry */ 3125/* -------------- */ 3126 pseudo_bit_t reserved13[0x7f840]; 3127/* -------------- */ 3128 struct hermonprm_address_path_st address_path;/* Address Path */ 3129/* -------------- */ 3130 pseudo_bit_t reserved14[0x7fea0]; 3131/* -------------- */ 3132 struct hermonprm_completion_queue_context_st completion_queue_context;/* Completion Queue Context Table Entry */ 3133/* -------------- */ 3134 pseudo_bit_t reserved15[0x7fe00]; 3135/* -------------- */ 3136 struct hermonprm_mpt_st mpt; /* Memory Protection Table (MPT) Entry */ 3137/* -------------- */ 3138 pseudo_bit_t reserved16[0x7fe00]; 3139/* -------------- */ 3140 struct hermonprm_mtt_st mtt; /* Memory Translation Table (MTT) Entry */ 3141/* -------------- */ 3142 pseudo_bit_t reserved17[0x7ffc0]; 3143/* -------------- */ 3144 struct hermonprm_eqc_st eqc; /* Event Queue Context Table Entry */ 3145/* -------------- */ 3146 pseudo_bit_t reserved18[0x7fe00]; 3147/* -------------- */ 3148 struct hermonprm_performance_monitors_st performance_monitors;/* Performance Monitors */ 3149/* -------------- */ 3150 pseudo_bit_t reserved19[0x7ff80]; 3151/* -------------- */ 3152 struct hermonprm_hca_command_register_st hca_command_register;/* HCA Command Register (HCR) */ 3153/* -------------- */ 3154 pseudo_bit_t reserved20[0xfff20]; 3155/* -------------- */ 3156 struct hermonprm_init_hca_st init_hca;/* INIT_HCA & QUERY_HCA Parameters Block */ 3157/* -------------- */ 3158 pseudo_bit_t reserved21[0x7f000]; 3159/* -------------- */ 3160 struct hermonprm_qpcbaseaddr_st qpcbaseaddr;/* QPC/EEC/CQC/EQC/RDB Parameters */ 3161/* -------------- */ 3162 pseudo_bit_t reserved22[0x7fc00]; 3163/* -------------- */ 3164 struct hermonprm_udavtable_memory_parameters_st udavtable_memory_parameters;/* Memory Access Parameters for UD Address Vector Table */ 3165/* -------------- */ 3166 pseudo_bit_t reserved23[0x7ffc0]; 3167/* -------------- */ 3168 struct hermonprm_multicastparam_st multicastparam;/* Multicast Support Parameters */ 3169/* -------------- */ 3170 pseudo_bit_t reserved24[0x7ff00]; 3171/* -------------- */ 3172 struct hermonprm_tptparams_st tptparams;/* Translation and Protection Tables Parameters */ 3173/* -------------- */ 3174 pseudo_bit_t reserved25[0x7ff00]; 3175/* -------------- */ 3176 pseudo_bit_t reserved26[0x00800]; 3177/* -------------- */ 3178 pseudo_bit_t reserved27[0x00100]; 3179/* -------------- */ 3180 pseudo_bit_t reserved28[0x7f700]; 3181/* -------------- */ 3182 pseudo_bit_t reserved29[0x00100]; 3183/* -------------- */ 3184 pseudo_bit_t reserved30[0x7ff00]; 3185/* -------------- */ 3186 struct hermonprm_query_fw_st query_fw;/* QUERY_FW Parameters Block */ 3187/* -------------- */ 3188 pseudo_bit_t reserved31[0x7f800]; 3189/* -------------- */ 3190 struct hermonprm_query_adapter_st query_adapter;/* QUERY_ADAPTER Parameters Block */ 3191/* -------------- */ 3192 pseudo_bit_t reserved32[0x7f800]; 3193/* -------------- */ 3194 struct hermonprm_query_dev_cap_st query_dev_cap;/* Query Device Limitations */ 3195/* -------------- */ 3196 pseudo_bit_t reserved33[0x7f800]; 3197/* -------------- */ 3198 struct hermonprm_uar_params_st uar_params;/* UAR Parameters */ 3199/* -------------- */ 3200 pseudo_bit_t reserved34[0x7ff00]; 3201/* -------------- */ 3202 struct hermonprm_init_port_st init_port;/* INIT_PORT Parameters */ 3203/* -------------- */ 3204 pseudo_bit_t reserved35[0x7f800]; 3205/* -------------- */ 3206 struct hermonprm_mgm_entry_st mgm_entry;/* Multicast Group Member */ 3207/* -------------- */ 3208 pseudo_bit_t reserved36[0x7fe00]; 3209/* -------------- */ 3210 struct hermonprm_set_ib_st set_ib; /* SET_IB Parameters */ 3211/* -------------- */ 3212 pseudo_bit_t reserved37[0x7fe00]; 3213/* -------------- */ 3214 struct hermonprm_rd_send_doorbell_st rd_send_doorbell;/* RD-send doorbell */ 3215/* -------------- */ 3216 pseudo_bit_t reserved38[0x7ff80]; 3217/* -------------- */ 3218 struct hermonprm_send_doorbell_st send_doorbell;/* Send doorbell */ 3219/* -------------- */ 3220 pseudo_bit_t reserved39[0x7ffc0]; 3221/* -------------- */ 3222 struct hermonprm_receive_doorbell_st receive_doorbell;/* Receive doorbell */ 3223/* -------------- */ 3224 pseudo_bit_t reserved40[0x7ffc0]; 3225/* -------------- */ 3226 struct hermonprm_cq_cmd_doorbell_st cq_cmd_doorbell;/* CQ Doorbell */ 3227/* -------------- */ 3228 pseudo_bit_t reserved41[0xfffc0]; 3229/* -------------- */ 3230 struct hermonprm_uar_st uar; /* User Access Region */ 3231/* -------------- */ 3232 pseudo_bit_t reserved42[0x7c000]; 3233/* -------------- */ 3234 struct hermonprm_mgmqp_st mgmqp; /* Multicast Group Member QP */ 3235/* -------------- */ 3236 pseudo_bit_t reserved43[0x7ffe0]; 3237/* -------------- */ 3238 struct hermonprm_query_debug_msg_st query_debug_msg;/* Query Debug Message */ 3239/* -------------- */ 3240 pseudo_bit_t reserved44[0x7f800]; 3241/* -------------- */ 3242 struct hermonprm_mad_ifc_st mad_ifc; /* MAD_IFC Input Mailbox */ 3243/* -------------- */ 3244 pseudo_bit_t reserved45[0x00900]; 3245/* -------------- */ 3246 struct hermonprm_mad_ifc_input_modifier_st mad_ifc_input_modifier;/* MAD_IFC Input Modifier */ 3247/* -------------- */ 3248 pseudo_bit_t reserved46[0x7e6e0]; 3249/* -------------- */ 3250 struct hermonprm_resize_cq_st resize_cq;/* Resize CQ Input Mailbox */ 3251/* -------------- */ 3252 pseudo_bit_t reserved47[0x7fe00]; 3253/* -------------- */ 3254 struct hermonprm_completion_with_error_st completion_with_error;/* Completion with Error CQE */ 3255/* -------------- */ 3256 pseudo_bit_t reserved48[0x7ff00]; 3257/* -------------- */ 3258 struct hermonprm_hcr_completion_event_st hcr_completion_event;/* Event_data Field - HCR Completion Event */ 3259/* -------------- */ 3260 pseudo_bit_t reserved49[0x7ff40]; 3261/* -------------- */ 3262 struct hermonprm_transport_and_ci_error_counters_st transport_and_ci_error_counters;/* Transport and CI Error Counters */ 3263/* -------------- */ 3264 pseudo_bit_t reserved50[0x7f000]; 3265/* -------------- */ 3266 struct hermonprm_performance_counters_st performance_counters;/* Performance Counters */ 3267/* -------------- */ 3268 pseudo_bit_t reserved51[0x9ff800]; 3269/* -------------- */ 3270 struct hermonprm_fast_registration_segment_st fast_registration_segment;/* Fast Registration Segment */ 3271/* -------------- */ 3272 pseudo_bit_t reserved52[0x7ff00]; 3273/* -------------- */ 3274 struct hermonprm_pbl_st pbl; /* Physical Buffer List */ 3275/* -------------- */ 3276 pseudo_bit_t reserved53[0x7ff00]; 3277/* -------------- */ 3278 struct hermonprm_srq_context_st srq_context;/* SRQ Context */ 3279/* -------------- */ 3280 pseudo_bit_t reserved54[0x7fe80]; 3281/* -------------- */ 3282 struct hermonprm_mod_stat_cfg_st mod_stat_cfg;/* MOD_STAT_CFG */ 3283/* -------------- */ 3284 pseudo_bit_t reserved55[0x7f800]; 3285/* -------------- */ 3286 struct hermonprm_virtual_physical_mapping_st virtual_physical_mapping;/* Virtual and Physical Mapping */ 3287/* -------------- */ 3288 pseudo_bit_t reserved56[0x7ff80]; 3289/* -------------- */ 3290 struct hermonprm_cq_ci_db_record_st cq_ci_db_record;/* CQ_CI_DB_Record */ 3291/* -------------- */ 3292 pseudo_bit_t reserved57[0x7ffc0]; 3293/* -------------- */ 3294 struct hermonprm_cq_arm_db_record_st cq_arm_db_record;/* CQ_ARM_DB_Record */ 3295/* -------------- */ 3296 pseudo_bit_t reserved58[0x7ffc0]; 3297/* -------------- */ 3298 struct hermonprm_qp_db_record_st qp_db_record;/* QP_DB_Record */ 3299/* -------------- */ 3300 pseudo_bit_t reserved59[0x00020]; 3301/* -------------- */ 3302 pseudo_bit_t reserved60[0x1fffc0]; 3303/* -------------- */ 3304 struct hermonprm_configuration_registers_st configuration_registers;/* InfiniHost III EX Configuration Registers */ 3305/* -------------- */ 3306 struct hermonprm_eq_set_ci_table_st eq_set_ci_table;/* EQ Set CI DBs Table */ 3307/* -------------- */ 3308 pseudo_bit_t reserved61[0x01000]; 3309/* -------------- */ 3310 pseudo_bit_t reserved62[0x00040]; 3311/* -------------- */ 3312 pseudo_bit_t reserved63[0x00fc0]; 3313/* -------------- */ 3314 struct hermonprm_clr_int_st clr_int; /* Clear Interrupt Register */ 3315/* -------------- */ 3316 pseudo_bit_t reserved64[0xffcfc0]; 3317/* -------------- */ 3318}; 3319#endif /* H_prefix_hermonprm_bits_fixnames_MT25408_PRM_csp_H */ 3320