logic-aarch64.cc revision 868bfc49d722d6a233390ec847fa1407820a1eab
1b78f13911bfe6eda303e91ef215c87a165aae8aeAlexandre Rames// Copyright 2015, VIXL authors 25289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// All rights reserved. 35289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// 45289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Redistribution and use in source and binary forms, with or without 55289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// modification, are permitted provided that the following conditions are met: 65289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// 75289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// * Redistributions of source code must retain the above copyright notice, 85289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// this list of conditions and the following disclaimer. 95289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// * Redistributions in binary form must reproduce the above copyright notice, 105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// this list of conditions and the following disclaimer in the documentation 115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// and/or other materials provided with the distribution. 125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// * Neither the name of ARM Limited nor the names of its contributors may be 135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// used to endorse or promote products derived from this software without 145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// specific prior written permission. 155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// 165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl#ifdef VIXL_INCLUDE_SIMULATOR 28684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl 296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl#include <cmath> 30b68bacb75c1ab265fc539afa93964c7f51f35589Alexandre Rames 31d3832965c62a8ad461b9ea9eb0994ca6b0a3da2cAlexandre Rames#include "aarch64/simulator-aarch64.h" 325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlnamespace vixl { 3488c46b84df005638546de5e4e965bdcc31352f48Pierre Langloisnamespace aarch64 { 356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltemplate <> 370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixldouble Simulator::FPDefaultNaN<double>() { 386e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return kFP64DefaultNaN; 396e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltemplate <> 430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlfloat Simulator::FPDefaultNaN<float>() { 446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return kFP32DefaultNaN; 456e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 476e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// See FPRound for a description of this function. 480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlstatic inline double FPRoundToDouble(int64_t sign, 490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t exponent, 500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t mantissa, 510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl FPRounding round_mode) { 526e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl int64_t bits = 536e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPRound<int64_t, kDoubleExponentBits, kDoubleMantissaBits>(sign, 546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent, 556e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa, 566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl round_mode); 5788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return RawbitsToDouble(bits); 586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 606e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 616e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// See FPRound for a description of this function. 620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlstatic inline float FPRoundToFloat(int64_t sign, 630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t exponent, 640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t mantissa, 650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl FPRounding round_mode) { 666e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl int32_t bits = 676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPRound<int32_t, kFloatExponentBits, kFloatMantissaBits>(sign, 686e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent, 696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa, 706e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl round_mode); 7188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return RawbitsToFloat(bits); 726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 736e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl// See FPRound for a description of this function. 766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlstatic inline float16 FPRoundToFloat16(int64_t sign, 776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl int64_t exponent, 786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t mantissa, 796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPRounding round_mode) { 800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return FPRound<float16, 810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl kFloat16ExponentBits, 820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl kFloat16MantissaBits>(sign, exponent, mantissa, round_mode); 836e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 846e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 856e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 866e2c8275d5f34a531fe1eef7a7aa877601be8558armvixldouble Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { 876e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (src >= 0) { 886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return UFixedToDouble(src, fbits, round); 896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // This works for all negative values, including INT64_MIN. 916e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return -UFixedToDouble(-src, fbits, round); 926e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 936e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 956e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixldouble Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { 976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // An input of 0 is a special case because the result is effectively 986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // subnormal: The exponent is encoded as 0 and there is no implicit 1 bit. 996e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (src == 0) { 1006e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return 0.0; 1016e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1026e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1036e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Calculate the exponent. The highest significant bit will have the value 1046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 2^exponent. 1056e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const int highest_significant_bit = 63 - CountLeadingZeros(src); 1066e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const int64_t exponent = highest_significant_bit - fbits; 1076e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1086e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPRoundToDouble(0, exponent, src, round); 1096e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 1106e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1116e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1126e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlfloat Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) { 1136e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (src >= 0) { 1146e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return UFixedToFloat(src, fbits, round); 1156e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else { 1166e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // This works for all negative values, including INT64_MIN. 1176e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return -UFixedToFloat(-src, fbits, round); 1186e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1196e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 1206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1216e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1226e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlfloat Simulator::UFixedToFloat(uint64_t src, int fbits, FPRounding round) { 1236e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // An input of 0 is a special case because the result is effectively 1246e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // subnormal: The exponent is encoded as 0 and there is no implicit 1 bit. 1256e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (src == 0) { 1266e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return 0.0f; 1276e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Calculate the exponent. The highest significant bit will have the value 1306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // 2^exponent. 1316e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const int highest_significant_bit = 63 - CountLeadingZeros(src); 1326e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl const int32_t exponent = highest_significant_bit - fbits; 1336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPRoundToFloat(0, exponent, src, round); 1356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 1366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1376e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1386e2c8275d5f34a531fe1eef7a7aa877601be8558armvixldouble Simulator::FPToDouble(float value) { 1396e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl switch (std::fpclassify(value)) { 1406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_NAN: { 1416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(value)) { 1426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPProcessException(); 1436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 14488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (ReadDN()) return kFP64DefaultNaN; 1456e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Convert NaNs as the processor would: 1476e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // - The sign is propagated. 1486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // - The payload (mantissa) is transferred entirely, except that the top 1496e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // bit is forced to '1', making the result a quiet NaN. The unused 1506e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // (low-order) payload bits are set to 0. 15188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t raw = FloatToRawbits(value); 1526e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1536e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t sign = raw >> 31; 1546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint64_t exponent = (1 << 11) - 1; 15588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t payload = ExtractUnsignedBitfield64(21, 0, raw); 1560f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl payload <<= (52 - 23); // The unused low-order bits should be 0. 1576e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl payload |= (UINT64_C(1) << 51); // Force a quiet NaN. 1586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 15988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return RawbitsToDouble((sign << 63) | (exponent << 52) | payload); 1606e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1616e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1626e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_ZERO: 1636e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_NORMAL: 1646e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_SUBNORMAL: 1656e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_INFINITE: { 1666e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // All other inputs are preserved in a standard cast, because every value 1676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // representable using an IEEE-754 float is also representable using an 1686e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // IEEE-754 double. 1696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return static_cast<double>(value); 1706e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1716e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 1726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1736e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_UNREACHABLE(); 1746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return static_cast<double>(value); 1756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 1766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlfloat Simulator::FPToFloat(float16 value) { 1796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint32_t sign = value >> 15; 1800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint32_t exponent = 18188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois ExtractUnsignedBitfield32(kFloat16MantissaBits + kFloat16ExponentBits - 1, 18288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois kFloat16MantissaBits, 18388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois value); 1840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint32_t mantissa = 18588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois ExtractUnsignedBitfield32(kFloat16MantissaBits - 1, 0, value); 1866e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 18788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois switch (Float16Classify(value)) { 1886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_ZERO: 1896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return (sign == 0) ? 0.0f : -0.0f; 1906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1916e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_INFINITE: 1926e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return (sign == 0) ? kFP32PositiveInfinity : kFP32NegativeInfinity; 1936e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_SUBNORMAL: { 1956e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Calculate shift required to put mantissa into the most-significant bits 1966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // of the destination mantissa. 1976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl int shift = CountLeadingZeros(mantissa << (32 - 10)); 1986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 1996e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Shift mantissa and discard implicit '1'. 2006e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa <<= (kFloatMantissaBits - kFloat16MantissaBits) + shift + 1; 2016e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa &= (1 << kFloatMantissaBits) - 1; 2026e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2036e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Adjust the exponent for the shift applied, and rebias. 2046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent = exponent - shift + (-15 + 127); 2056e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl break; 2066e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2076e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2086e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_NAN: 2096e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(value)) { 2106e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPProcessException(); 2116e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 21288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (ReadDN()) return kFP32DefaultNaN; 2136e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2146e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Convert NaNs as the processor would: 2156e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // - The sign is propagated. 2166e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // - The payload (mantissa) is transferred entirely, except that the top 2176e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // bit is forced to '1', making the result a quiet NaN. The unused 2186e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // (low-order) payload bits are set to 0. 2196e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent = (1 << kFloatExponentBits) - 1; 2206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2216e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Increase bits in mantissa, making low-order bits 0. 2226e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa <<= (kFloatMantissaBits - kFloat16MantissaBits); 2236e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa |= 1 << 22; // Force a quiet NaN. 2246e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl break; 2256e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2266e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_NORMAL: 2276e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Increase bits in mantissa, making low-order bits 0. 2286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa <<= (kFloatMantissaBits - kFloat16MantissaBits); 2296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Change exponent bias. 2316e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl exponent += (-15 + 127); 2326e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl break; 2336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 2350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 2366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 23788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return RawbitsToFloat((sign << 31) | (exponent << kFloatMantissaBits) | 23888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois mantissa); 2396e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 2406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlfloat16 Simulator::FPToFloat16(float value, FPRounding round_mode) { 2436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Only the FPTieEven rounding mode is implemented. 2446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(round_mode == FPTieEven); 2456e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl USE(round_mode); 2466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 24788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t raw = FloatToRawbits(value); 2486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl int32_t sign = raw >> 31; 24988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int32_t exponent = ExtractUnsignedBitfield32(30, 23, raw) - 127; 25088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint32_t mantissa = ExtractUnsignedBitfield32(22, 0, raw); 2516e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2526e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl switch (std::fpclassify(value)) { 2536e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_NAN: { 2546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(value)) { 2556e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPProcessException(); 2566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 25788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (ReadDN()) return kFP16DefaultNaN; 2586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Convert NaNs as the processor would: 2606e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // - The sign is propagated. 2616e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // - The payload (mantissa) is transferred as much as possible, except 2626e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // that the top bit is forced to '1', making the result a quiet NaN. 2630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl float16 result = 2640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (sign == 0) ? kFP16PositiveInfinity : kFP16NegativeInfinity; 2656e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl result |= mantissa >> (kFloatMantissaBits - kFloat16MantissaBits); 2666e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl result |= (1 << 9); // Force a quiet NaN; 2676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return result; 2686e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2706e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_ZERO: 2716e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return (sign == 0) ? 0 : 0x8000; 2726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2736e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_INFINITE: 2746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return (sign == 0) ? kFP16PositiveInfinity : kFP16NegativeInfinity; 2756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_NORMAL: 2776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_SUBNORMAL: { 2786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Convert float-to-half as the processor would, assuming that FPCR.FZ 2796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // (flush-to-zero) is not set. 2806e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2816e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Add the implicit '1' bit to the mantissa. 2826e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa += (1 << 23); 2836e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPRoundToFloat16(sign, exponent, mantissa, round_mode); 2846e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2856e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 2866e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2876e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_UNREACHABLE(); 2886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return 0; 2896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 2906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2916e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 2926e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlfloat16 Simulator::FPToFloat16(double value, FPRounding round_mode) { 2936e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Only the FPTieEven rounding mode is implemented. 2946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(round_mode == FPTieEven); 2956e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl USE(round_mode); 2966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 29788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t raw = DoubleToRawbits(value); 2986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl int32_t sign = raw >> 63; 29988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois int64_t exponent = ExtractUnsignedBitfield64(62, 52, raw) - 1023; 30088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t mantissa = ExtractUnsignedBitfield64(51, 0, raw); 3016e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3026e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl switch (std::fpclassify(value)) { 3036e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_NAN: { 3046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(value)) { 3056e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPProcessException(); 3066e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 30788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (ReadDN()) return kFP16DefaultNaN; 3086e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3096e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Convert NaNs as the processor would: 3106e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // - The sign is propagated. 3116e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // - The payload (mantissa) is transferred as much as possible, except 3126e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // that the top bit is forced to '1', making the result a quiet NaN. 3130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl float16 result = 3140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl (sign == 0) ? kFP16PositiveInfinity : kFP16NegativeInfinity; 3156e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl result |= mantissa >> (kDoubleMantissaBits - kFloat16MantissaBits); 3166e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl result |= (1 << 9); // Force a quiet NaN; 3176e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return result; 3186e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 3196e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_ZERO: 3216e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return (sign == 0) ? 0 : 0x8000; 3226e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3236e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_INFINITE: 3246e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return (sign == 0) ? kFP16PositiveInfinity : kFP16NegativeInfinity; 3256e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3266e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_NORMAL: 3276e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_SUBNORMAL: { 3286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Convert double-to-half as the processor would, assuming that FPCR.FZ 3296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // (flush-to-zero) is not set. 3306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3316e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Add the implicit '1' bit to the mantissa. 3326e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa += (UINT64_C(1) << 52); 3336e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPRoundToFloat16(sign, exponent, mantissa, round_mode); 3346e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 3356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 3366e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3376e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_UNREACHABLE(); 3386e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return 0; 3396e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 3406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3416e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3426e2c8275d5f34a531fe1eef7a7aa877601be8558armvixlfloat Simulator::FPToFloat(double value, FPRounding round_mode) { 3436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Only the FPTieEven rounding mode is implemented. 3446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT((round_mode == FPTieEven) || (round_mode == FPRoundOdd)); 3456e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl USE(round_mode); 3466e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3476e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl switch (std::fpclassify(value)) { 3486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_NAN: { 3496e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (IsSignallingNaN(value)) { 3506e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl FPProcessException(); 3516e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 35288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois if (ReadDN()) return kFP32DefaultNaN; 3536e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Convert NaNs as the processor would: 3556e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // - The sign is propagated. 3566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // - The payload (mantissa) is transferred as much as possible, except 3576e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // that the top bit is forced to '1', making the result a quiet NaN. 35888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t raw = DoubleToRawbits(value); 3596e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3606e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint32_t sign = raw >> 63; 3616e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint32_t exponent = (1 << 8) - 1; 362db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint32_t payload = 36388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois static_cast<uint32_t>(ExtractUnsignedBitfield64(50, 52 - 23, raw)); 3640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl payload |= (1 << 22); // Force a quiet NaN. 3656e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 36688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return RawbitsToFloat((sign << 31) | (exponent << 23) | payload); 3676e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 3686e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3696e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_ZERO: 3706e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_INFINITE: { 3716e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // In a C++ cast, any value representable in the target type will be 3726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // unchanged. This is always the case for +/-0.0 and infinities. 3736e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return static_cast<float>(value); 3746e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 3756e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_NORMAL: 3776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl case FP_SUBNORMAL: { 3786e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Convert double-to-float as the processor would, assuming that FPCR.FZ 3796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // (flush-to-zero) is not set. 38088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t raw = DoubleToRawbits(value); 3816e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Extract the IEEE-754 double components. 3826e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl uint32_t sign = raw >> 63; 3836e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Extract the exponent and remove the IEEE-754 encoding bias. 384db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl int32_t exponent = 38588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois static_cast<int32_t>(ExtractUnsignedBitfield64(62, 52, raw)) - 1023; 3866e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl // Extract the mantissa and add the implicit '1' bit. 38788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t mantissa = ExtractUnsignedBitfield64(51, 0, raw); 3886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (std::fpclassify(value) == FP_NORMAL) { 3896e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl mantissa |= (UINT64_C(1) << 52); 3906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 3916e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return FPRoundToFloat(sign, exponent, mantissa, round_mode); 3926e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 3936e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } 3946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3956e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_UNREACHABLE(); 3966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return value; 3976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl} 3986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 3996e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl 4000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { 4015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 4025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 4035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ReadUintFromMem(vform, i, addr); 4045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr += LaneSizeInBytesFromFormat(vform); 4055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 4075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::ld1(VectorFormat vform, 4105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 4115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 4125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr) { 4135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ReadUintFromMem(vform, index, addr); 4145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 4155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4170f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { 4185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 4195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 4205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ReadUintFromMem(vform, i, addr); 4215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 4235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::ld2(VectorFormat vform, 4265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 4275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 4285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr1) { 4295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ClearForWrite(vform); 4305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ClearForWrite(vform); 4315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int esize = LaneSizeInBytesFromFormat(vform); 4325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr2 = addr1 + esize; 4335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 4345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ReadUintFromMem(vform, i, addr1); 4355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ReadUintFromMem(vform, i, addr2); 4365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr1 += 2 * esize; 4375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr2 += 2 * esize; 4385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 4405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::ld2(VectorFormat vform, 4435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 4445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 4455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 4465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr1) { 4475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ClearForWrite(vform); 4485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ClearForWrite(vform); 4495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr2 = addr1 + LaneSizeInBytesFromFormat(vform); 4505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ReadUintFromMem(vform, index, addr1); 4515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ReadUintFromMem(vform, index, addr2); 4525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 4535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::ld2r(VectorFormat vform, 4565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 4575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 4585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr) { 4595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ClearForWrite(vform); 4605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ClearForWrite(vform); 4615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr2 = addr + LaneSizeInBytesFromFormat(vform); 4625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 4635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ReadUintFromMem(vform, i, addr); 4645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ReadUintFromMem(vform, i, addr2); 4655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 4675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::ld3(VectorFormat vform, 4705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 4715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 4725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 4735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr1) { 4745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ClearForWrite(vform); 4755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ClearForWrite(vform); 4765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.ClearForWrite(vform); 4775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int esize = LaneSizeInBytesFromFormat(vform); 4785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr2 = addr1 + esize; 4795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr3 = addr2 + esize; 4805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 4815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ReadUintFromMem(vform, i, addr1); 4825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ReadUintFromMem(vform, i, addr2); 4835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.ReadUintFromMem(vform, i, addr3); 4845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr1 += 3 * esize; 4855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr2 += 3 * esize; 4865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr3 += 3 * esize; 4875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 4885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 4895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 4915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::ld3(VectorFormat vform, 4925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 4935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 4945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 4955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 4965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr1) { 4975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ClearForWrite(vform); 4985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ClearForWrite(vform); 4995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.ClearForWrite(vform); 5005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr2 = addr1 + LaneSizeInBytesFromFormat(vform); 5015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform); 5025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ReadUintFromMem(vform, index, addr1); 5035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ReadUintFromMem(vform, index, addr2); 5045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.ReadUintFromMem(vform, index, addr3); 5055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 5065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::ld3r(VectorFormat vform, 5095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 5105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 5115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 5125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr) { 5135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ClearForWrite(vform); 5145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ClearForWrite(vform); 5155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.ClearForWrite(vform); 5165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr2 = addr + LaneSizeInBytesFromFormat(vform); 5175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform); 5185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 5195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ReadUintFromMem(vform, i, addr); 5205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ReadUintFromMem(vform, i, addr2); 5215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.ReadUintFromMem(vform, i, addr3); 5225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 5245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::ld4(VectorFormat vform, 5275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 5285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 5295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 5305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst4, 5315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr1) { 5325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ClearForWrite(vform); 5335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ClearForWrite(vform); 5345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.ClearForWrite(vform); 5355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst4.ClearForWrite(vform); 5365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int esize = LaneSizeInBytesFromFormat(vform); 5375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr2 = addr1 + esize; 5385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr3 = addr2 + esize; 5395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr4 = addr3 + esize; 5405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 5415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ReadUintFromMem(vform, i, addr1); 5425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ReadUintFromMem(vform, i, addr2); 5435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.ReadUintFromMem(vform, i, addr3); 5445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst4.ReadUintFromMem(vform, i, addr4); 5455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr1 += 4 * esize; 5465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr2 += 4 * esize; 5475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr3 += 4 * esize; 5485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr4 += 4 * esize; 5495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 5515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::ld4(VectorFormat vform, 5545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 5555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 5565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 5575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst4, 5585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 5595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr1) { 5605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ClearForWrite(vform); 5615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ClearForWrite(vform); 5625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.ClearForWrite(vform); 5635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst4.ClearForWrite(vform); 5645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr2 = addr1 + LaneSizeInBytesFromFormat(vform); 5655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform); 5665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr4 = addr3 + LaneSizeInBytesFromFormat(vform); 5675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ReadUintFromMem(vform, index, addr1); 5685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ReadUintFromMem(vform, index, addr2); 5695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.ReadUintFromMem(vform, index, addr3); 5705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst4.ReadUintFromMem(vform, index, addr4); 5715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 5725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::ld4r(VectorFormat vform, 5755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst1, 5765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 5775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 5785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst4, 5795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr) { 5805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ClearForWrite(vform); 5815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ClearForWrite(vform); 5825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.ClearForWrite(vform); 5835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst4.ClearForWrite(vform); 5845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr2 = addr + LaneSizeInBytesFromFormat(vform); 5855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform); 5865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr4 = addr3 + LaneSizeInBytesFromFormat(vform); 5875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 5885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst1.ReadUintFromMem(vform, i, addr); 5895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.ReadUintFromMem(vform, i, addr2); 5905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.ReadUintFromMem(vform, i, addr3); 5915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst4.ReadUintFromMem(vform, i, addr4); 5925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 5935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 5945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 5960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixlvoid Simulator::st1(VectorFormat vform, LogicVRegister src, uint64_t addr) { 5975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 5985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl src.WriteUintToMem(vform, i, addr); 5995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr += LaneSizeInBytesFromFormat(vform); 6005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::st1(VectorFormat vform, 6055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister src, 6065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 6075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr) { 6085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl src.WriteUintToMem(vform, index, addr); 6095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::st2(VectorFormat vform, 6135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 6145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 6155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr) { 6165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int esize = LaneSizeInBytesFromFormat(vform); 6175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr2 = addr + esize; 6185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 6195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.WriteUintToMem(vform, i, addr); 6205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.WriteUintToMem(vform, i, addr2); 6215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr += 2 * esize; 6225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr2 += 2 * esize; 6235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::st2(VectorFormat vform, 6285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 6295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 6305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 6315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr) { 6325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int esize = LaneSizeInBytesFromFormat(vform); 6335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.WriteUintToMem(vform, index, addr); 6345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.WriteUintToMem(vform, index, addr + 1 * esize); 6355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::st3(VectorFormat vform, 6395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 6405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 6415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 6425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr) { 6435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int esize = LaneSizeInBytesFromFormat(vform); 6445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr2 = addr + esize; 6455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr3 = addr2 + esize; 6465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 6475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.WriteUintToMem(vform, i, addr); 6485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.WriteUintToMem(vform, i, addr2); 6495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.WriteUintToMem(vform, i, addr3); 6505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr += 3 * esize; 6515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr2 += 3 * esize; 6525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr3 += 3 * esize; 6535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::st3(VectorFormat vform, 6585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 6595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 6605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 6615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 6625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr) { 6635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int esize = LaneSizeInBytesFromFormat(vform); 6645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.WriteUintToMem(vform, index, addr); 6655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.WriteUintToMem(vform, index, addr + 1 * esize); 6665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.WriteUintToMem(vform, index, addr + 2 * esize); 6675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::st4(VectorFormat vform, 6715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 6725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 6735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 6745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst4, 6755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr) { 6765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int esize = LaneSizeInBytesFromFormat(vform); 6775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr2 = addr + esize; 6785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr3 = addr2 + esize; 6795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr4 = addr3 + esize; 6805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 6815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.WriteUintToMem(vform, i, addr); 6825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.WriteUintToMem(vform, i, addr2); 6835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.WriteUintToMem(vform, i, addr3); 6845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst4.WriteUintToMem(vform, i, addr4); 6855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr += 4 * esize; 6865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr2 += 4 * esize; 6875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr3 += 4 * esize; 6885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl addr4 += 4 * esize; 6895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 6905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 6915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 6935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlvoid Simulator::st4(VectorFormat vform, 6945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 6955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst2, 6965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst3, 6975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst4, 6985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index, 6995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t addr) { 7005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int esize = LaneSizeInBytesFromFormat(vform); 7015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.WriteUintToMem(vform, index, addr); 7025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst2.WriteUintToMem(vform, index, addr + 1 * esize); 7035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst3.WriteUintToMem(vform, index, addr + 2 * esize); 7045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst4.WriteUintToMem(vform, index, addr + 3 * esize); 7055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 7065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 7075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 7085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::cmp(VectorFormat vform, 7095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 7105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 7115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 7125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond) { 7135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 7145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 7150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t sa = src1.Int(vform, i); 7160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t sb = src2.Int(vform, i); 7175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t ua = src1.Uint(vform, i); 7185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t ub = src2.Uint(vform, i); 7195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool result = false; 7205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (cond) { 7210f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case eq: 7220f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = (ua == ub); 7230f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 7240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case ge: 7250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = (sa >= sb); 7260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 7270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case gt: 7280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = (sa > sb); 7290f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 7300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case hi: 7310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = (ua > ub); 7320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 7330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case hs: 7340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = (ua >= ub); 7350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 7360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case lt: 7370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = (sa < sb); 7380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 7390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case le: 7400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = (sa <= sb); 7410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 7420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 7430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 7440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 7455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 7465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result ? MaxUintFromFormat(vform) : 0); 7475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 7485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 7495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 7505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 7515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 7525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::cmp(VectorFormat vform, 7535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 7545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 7555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int imm, 7565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond) { 7575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 7585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister imm_reg = dup_immediate(vform, temp, imm); 7595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return cmp(vform, dst, src1, imm_reg, cond); 7605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 7615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 7625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 7635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::cmptst(VectorFormat vform, 7645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 7655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 7665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 7675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 7685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 7695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t ua = src1.Uint(vform, i); 7705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t ub = src2.Uint(vform, i); 7715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, ((ua & ub) != 0) ? MaxUintFromFormat(vform) : 0); 7725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 7735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 7745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 7755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 7765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 7775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::add(VectorFormat vform, 7785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 7795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 7805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 7815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 7825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // TODO(all): consider assigning the result of LaneCountFromFormat to a local. 7835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 7845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Test for unsigned saturation. 7855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t ua = src1.UintLeftJustified(vform, i); 7865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t ub = src2.UintLeftJustified(vform, i); 7875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t ur = ua + ub; 7885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (ur < ua) { 7895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUnsignedSat(i, true); 7905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 7915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 7925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Test for signed saturation. 7935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t sa = src1.IntLeftJustified(vform, i); 7945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t sb = src2.IntLeftJustified(vform, i); 7955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t sr = sa + sb; 7965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // If the signs of the operands are the same, but different from the result, 7975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // there was an overflow. 7985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (((sa >= 0) == (sb >= 0)) && ((sa >= 0) != (sr >= 0))) { 7995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetSignedSat(i, sa >= 0); 8005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 8015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, src1.Int(vform, i) + src2.Int(vform, i)); 8035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 8045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 8055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 8065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::addp(VectorFormat vform, 8095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 8105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 8115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 8125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 8135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uzp1(vform, temp1, src1, src2); 8145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uzp2(vform, temp2, src1, src2); 8155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(vform, dst, temp1, temp2); 8165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 8175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 8185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::mla(VectorFormat vform, 8215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 8225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 8235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 8245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 8255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mul(vform, temp, src1, src2); 8265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(vform, dst, dst, temp); 8275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 8285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 8295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::mls(VectorFormat vform, 8325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 8335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 8345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 8355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 8365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mul(vform, temp, src1, src2); 8375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(vform, dst, dst, temp); 8385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 8395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 8405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::mul(VectorFormat vform, 8435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 8445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 8455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 8465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 8475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 8485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, src1.Uint(vform, i) * src2.Uint(vform, i)); 8495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 8505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 8515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 8525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::mul(VectorFormat vform, 8555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 8565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 8575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 8585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 8595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 8605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = VectorFormatFillQ(vform); 8615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return mul(vform, dst, src1, dup_element(indexform, temp, src2, index)); 8625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 8635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::mla(VectorFormat vform, 8665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 8675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 8685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 8695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 8705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 8715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = VectorFormatFillQ(vform); 8725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return mla(vform, dst, src1, dup_element(indexform, temp, src2, index)); 8735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 8745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::mls(VectorFormat vform, 8775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 8785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 8795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 8805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 8815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 8825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = VectorFormatFillQ(vform); 8835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return mls(vform, dst, src1, dup_element(indexform, temp, src2, index)); 8845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 8855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smull(VectorFormat vform, 8885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 8895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 8905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 8915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 8925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 8935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 8940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 8955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return smull(vform, dst, src1, dup_element(indexform, temp, src2, index)); 8965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 8975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 8995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smull2(VectorFormat vform, 9000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 9010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 9020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2, 9030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int index) { 9045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 9055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 9060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 9075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return smull2(vform, dst, src1, dup_element(indexform, temp, src2, index)); 9085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 9095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umull(VectorFormat vform, 9125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 9135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 9145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 9155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 9165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 9175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 9180f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 9195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return umull(vform, dst, src1, dup_element(indexform, temp, src2, index)); 9205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 9215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umull2(VectorFormat vform, 9240f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 9250f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 9260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2, 9270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int index) { 9285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 9295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 9300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 9315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return umull2(vform, dst, src1, dup_element(indexform, temp, src2, index)); 9325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 9335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smlal(VectorFormat vform, 9365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 9375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 9385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 9395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 9405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 9415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 9420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 9435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return smlal(vform, dst, src1, dup_element(indexform, temp, src2, index)); 9445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 9455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smlal2(VectorFormat vform, 9480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 9490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 9500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2, 9510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int index) { 9525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 9535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 9540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 9555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return smlal2(vform, dst, src1, dup_element(indexform, temp, src2, index)); 9565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 9575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umlal(VectorFormat vform, 9605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 9615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 9625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 9635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 9645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 9655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 9660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 9675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return umlal(vform, dst, src1, dup_element(indexform, temp, src2, index)); 9685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 9695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umlal2(VectorFormat vform, 9720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 9730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 9740f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2, 9750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int index) { 9765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 9775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 9780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 9795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return umlal2(vform, dst, src1, dup_element(indexform, temp, src2, index)); 9805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 9815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smlsl(VectorFormat vform, 9845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 9855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 9865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 9875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 9885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 9895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 9900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 9915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return smlsl(vform, dst, src1, dup_element(indexform, temp, src2, index)); 9925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 9935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 9955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smlsl2(VectorFormat vform, 9960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 9970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 9980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2, 9990f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int index) { 10005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 10015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 10020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 10035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return smlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index)); 10045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 10055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umlsl(VectorFormat vform, 10085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 10095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 10105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 10115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 10125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 10135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 10140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 10155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return umlsl(vform, dst, src1, dup_element(indexform, temp, src2, index)); 10165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 10175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umlsl2(VectorFormat vform, 10200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 10210f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 10220f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2, 10230f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int index) { 10245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 10255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 10260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 10275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return umlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index)); 10285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 10295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmull(VectorFormat vform, 10325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 10335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 10345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 10355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 10365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 10375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 10385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 10395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index)); 10405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 10415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmull2(VectorFormat vform, 10440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 10450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 10460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2, 10470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int index) { 10485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 10495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 10505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 10515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqdmull2(vform, dst, src1, dup_element(indexform, temp, src2, index)); 10525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 10535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmlal(VectorFormat vform, 10565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 10575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 10585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 10595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 10605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 10615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 10625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 10635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqdmlal(vform, dst, src1, dup_element(indexform, temp, src2, index)); 10645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 10655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmlal2(VectorFormat vform, 10680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 10690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 10700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2, 10710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int index) { 10725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 10735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 10745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 10755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqdmlal2(vform, dst, src1, dup_element(indexform, temp, src2, index)); 10765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 10775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmlsl(VectorFormat vform, 10805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 10815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 10825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 10835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 10845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 10855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 10865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 10875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqdmlsl(vform, dst, src1, dup_element(indexform, temp, src2, index)); 10885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 10895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 10915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmlsl2(VectorFormat vform, 10920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 10930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 10940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2, 10950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int index) { 10965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 10975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = 10985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormatHalfWidthDoubleLanes(VectorFormatFillQ(vform)); 10995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqdmlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index)); 11005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 11015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmulh(VectorFormat vform, 11045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 11055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 11065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 11075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 11085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 11095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = VectorFormatFillQ(vform); 11105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index)); 11115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 11125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqrdmulh(VectorFormat vform, 11150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 11160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 11170f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2, 11180f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int index) { 11195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 11205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat indexform = VectorFormatFillQ(vform); 11215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqrdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index)); 11225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 11235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 1125868bfc49d722d6a233390ec847fa1407820a1eabAlexandre Ramesuint16_t Simulator::PolynomialMult(uint8_t op1, uint8_t op2) const { 11265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint16_t result = 0; 11275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint16_t extended_op2 = op2; 11285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < 8; ++i) { 11295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((op1 >> i) & 1) { 11305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result = result ^ (extended_op2 << i); 11315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 11325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 11335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return result; 11345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 11355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::pmul(VectorFormat vform, 11385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 11395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 11405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 11415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 11425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 11430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, 11440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl i, 11455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl PolynomialMult(src1.Uint(vform, i), src2.Uint(vform, i))); 11465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 11475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 11485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 11495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::pmull(VectorFormat vform, 11520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 11530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 11540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2) { 11555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vform_src = VectorFormatHalfWidth(vform); 11565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 11575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 11580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, 11590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl i, 11600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PolynomialMult(src1.Uint(vform_src, i), 11610f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl src2.Uint(vform_src, i))); 11625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 11635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 11645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 11655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::pmull2(VectorFormat vform, 11680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 11690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 11700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2) { 11715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vform_src = VectorFormatHalfWidthDoubleLanes(vform); 11725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 11735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int lane_count = LaneCountFromFormat(vform); 11745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < lane_count; i++) { 11750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, 11760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl i, 11770f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl PolynomialMult(src1.Uint(vform_src, lane_count + i), 11780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl src2.Uint(vform_src, lane_count + i))); 11795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 11805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 11815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 11825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sub(VectorFormat vform, 11855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 11865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 11875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 11885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 11895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 11905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Test for unsigned saturation. 11915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (src2.Uint(vform, i) > src1.Uint(vform, i)) { 11925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUnsignedSat(i, false); 11935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 11945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 11955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Test for signed saturation. 11965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t sa = src1.IntLeftJustified(vform, i); 11975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t sb = src2.IntLeftJustified(vform, i); 11985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t sr = sa - sb; 11995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // If the signs of the operands are different, and the sign of the first 12005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // operand doesn't match the result, there was an overflow. 12015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (((sa >= 0) != (sb >= 0)) && ((sa >= 0) != (sr >= 0))) { 12025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetSignedSat(i, sr < 0); 12035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, src1.Int(vform, i) - src2.Int(vform, i)); 12065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 12085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 12095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::and_(VectorFormat vform, 12125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 12135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 12145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 12155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 12165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 12175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, src1.Uint(vform, i) & src2.Uint(vform, i)); 12185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 12205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 12215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::orr(VectorFormat vform, 12245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 12255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 12265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 12275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 12285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 12295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, src1.Uint(vform, i) | src2.Uint(vform, i)); 12305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 12325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 12335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::orn(VectorFormat vform, 12365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 12375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 12385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 12395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 12405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 12415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, src1.Uint(vform, i) | ~src2.Uint(vform, i)); 12425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 12445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 12455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::eor(VectorFormat vform, 12485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 12495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 12505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 12515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 12525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 12535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, src1.Uint(vform, i) ^ src2.Uint(vform, i)); 12545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 12565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 12575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::bic(VectorFormat vform, 12605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 12615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 12625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 12635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 12645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 12655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, src1.Uint(vform, i) & ~src2.Uint(vform, i)); 12665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 12685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 12695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::bic(VectorFormat vform, 12725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 12735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 12745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm) { 12755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[16]; 12765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 12775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 12785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[i] = src.Uint(vform, i) & ~imm; 12795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 12815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 12825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[i]); 12835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 12845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 12855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 12865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 12885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::bif(VectorFormat vform, 12895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 12905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 12915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 12925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 12935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 12945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t operand1 = dst.Uint(vform, i); 12955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t operand2 = ~src2.Uint(vform, i); 12965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t operand3 = src1.Uint(vform, i); 12975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result = operand1 ^ ((operand1 ^ operand3) & operand2); 12985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result); 12995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 13005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 13015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 13025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::bit(VectorFormat vform, 13055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 13065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 13075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 13085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 13095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 13105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t operand1 = dst.Uint(vform, i); 13115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t operand2 = src2.Uint(vform, i); 13125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t operand3 = src1.Uint(vform, i); 13135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result = operand1 ^ ((operand1 ^ operand3) & operand2); 13145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result); 13155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 13165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 13175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 13185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::bsl(VectorFormat vform, 13215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 13225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 13235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 13245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 13255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 13265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t operand1 = src2.Uint(vform, i); 13275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t operand2 = dst.Uint(vform, i); 13285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t operand3 = src1.Uint(vform, i); 13295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result = operand1 ^ ((operand1 ^ operand3) & operand2); 13305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result); 13315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 13325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 13335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 13345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sminmax(VectorFormat vform, 13375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 13385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 13395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 13405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max) { 13415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 13425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 13435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t src1_val = src1.Int(vform, i); 13445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t src2_val = src2.Int(vform, i); 13455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t dst_val; 13465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (max == true) { 13475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val = (src1_val > src2_val) ? src1_val : src2_val; 13485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 13495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val = (src1_val < src2_val) ? src1_val : src2_val; 13505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 13515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, dst_val); 13525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 13535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 13545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 13555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smax(VectorFormat vform, 13585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 13595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 13605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 13615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sminmax(vform, dst, src1, src2, true); 13625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 13635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smin(VectorFormat vform, 13665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 13675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 13685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 13695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sminmax(vform, dst, src1, src2, false); 13705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 13715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sminmaxp(VectorFormat vform, 13745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 13755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int dst_index, 13765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 13775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max) { 13785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i += 2) { 13795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t src1_val = src.Int(vform, i); 13805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t src2_val = src.Int(vform, i + 1); 13815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t dst_val; 13825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (max == true) { 13835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val = (src1_val > src2_val) ? src1_val : src2_val; 13845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 13855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val = (src1_val < src2_val) ? src1_val : src2_val; 13865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 13875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, dst_index + (i >> 1), dst_val); 13885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 13895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 13905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 13915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 13935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smaxp(VectorFormat vform, 13945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 13955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 13965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 13975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 13985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sminmaxp(vform, dst, 0, src1, true); 13995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sminmaxp(vform, dst, LaneCountFromFormat(vform) >> 1, src2, true); 14005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 14015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 14025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sminp(VectorFormat vform, 14055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 14065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 14075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 14085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 14095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sminmaxp(vform, dst, 0, src1, false); 14105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sminmaxp(vform, dst, LaneCountFromFormat(vform) >> 1, src2, false); 14115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 14125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 14135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::addp(VectorFormat vform, 14165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 14175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 14185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(vform == kFormatD); 14195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t dst_val = src.Int(kFormat2D, 0) + src.Int(kFormat2D, 1); 14215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 14225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, 0, dst_val); 14235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 14245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 14255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::addv(VectorFormat vform, 14285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 14295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 14300f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormat vform_dst = 14310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform)); 14325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t dst_val = 0; 14355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 14365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val += src.Int(vform, i); 14375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform_dst); 14405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform_dst, 0, dst_val); 14415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 14425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 14435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::saddlv(VectorFormat vform, 14465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 14475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 14480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormat vform_dst = 14490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform) * 2); 14505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t dst_val = 0; 14525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 14535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val += src.Int(vform, i); 14545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform_dst); 14575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform_dst, 0, dst_val); 14585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 14595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 14605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uaddlv(VectorFormat vform, 14635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 14645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 14650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VectorFormat vform_dst = 14660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform) * 2); 14675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t dst_val = 0; 14695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 14705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val += src.Uint(vform, i); 14715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform_dst); 14745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform_dst, 0, dst_val); 14755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 14765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 14775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sminmaxv(VectorFormat vform, 14805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 14815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 14825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max) { 14835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 14845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t dst_val = max ? INT64_MIN : INT64_MAX; 14855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 14865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, 0); 14875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t src_val = src.Int(vform, i); 14885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (max == true) { 14895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val = (src_val > dst_val) ? src_val : dst_val; 14905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 14915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val = (src_val < dst_val) ? src_val : dst_val; 14925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 14945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, 0, dst_val); 14955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 14965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 14975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 14995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smaxv(VectorFormat vform, 15005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 15015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 15025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sminmaxv(vform, dst, src, true); 15035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 15045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 15055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sminv(VectorFormat vform, 15085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 15095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 15105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sminmaxv(vform, dst, src, false); 15115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 15125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 15135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uminmax(VectorFormat vform, 15165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 15175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 15185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 15195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max) { 15205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 15215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 15225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t src1_val = src1.Uint(vform, i); 15235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t src2_val = src2.Uint(vform, i); 15245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t dst_val; 15255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (max == true) { 15265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val = (src1_val > src2_val) ? src1_val : src2_val; 15275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 15285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val = (src1_val < src2_val) ? src1_val : src2_val; 15295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, dst_val); 15315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 15335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 15345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umax(VectorFormat vform, 15375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 15385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 15395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 15405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return uminmax(vform, dst, src1, src2, true); 15415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 15425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umin(VectorFormat vform, 15455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 15465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 15475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 15485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return uminmax(vform, dst, src1, src2, false); 15495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 15505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uminmaxp(VectorFormat vform, 15535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 15545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int dst_index, 15555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 15565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max) { 15575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i += 2) { 15585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t src1_val = src.Uint(vform, i); 15595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t src2_val = src.Uint(vform, i + 1); 15605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t dst_val; 15615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (max == true) { 15625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val = (src1_val > src2_val) ? src1_val : src2_val; 15635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 15645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val = (src1_val < src2_val) ? src1_val : src2_val; 15655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, dst_index + (i >> 1), dst_val); 15675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 15685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 15695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 15705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umaxp(VectorFormat vform, 15735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 15745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 15755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 15765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 15775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uminmaxp(vform, dst, 0, src1, true); 15785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uminmaxp(vform, dst, LaneCountFromFormat(vform) >> 1, src2, true); 15795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 15805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 15815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uminp(VectorFormat vform, 15845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 15855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 15865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 15875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 15885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uminmaxp(vform, dst, 0, src1, false); 15895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uminmaxp(vform, dst, LaneCountFromFormat(vform) >> 1, src2, false); 15905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 15915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 15925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 15945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uminmaxv(VectorFormat vform, 15955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 15965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 15975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool max) { 15985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 15995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t dst_val = max ? 0 : UINT64_MAX; 16005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 16015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, 0); 16025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t src_val = src.Uint(vform, i); 16035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (max == true) { 16045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val = (src_val > dst_val) ? src_val : dst_val; 16055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 16065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst_val = (src_val < dst_val) ? src_val : dst_val; 16075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 16085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 16095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, 0, dst_val); 16105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 16115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 16125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umaxv(VectorFormat vform, 16155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 16165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 16175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uminmaxv(vform, dst, src, true); 16185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 16195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 16205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uminv(VectorFormat vform, 16235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 16245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 16255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uminmaxv(vform, dst, src, false); 16265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 16275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 16285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::shl(VectorFormat vform, 16315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 16325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 16335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 16345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(shift >= 0); 16355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 16365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shiftreg = dup_immediate(vform, temp, shift); 16375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return ushl(vform, dst, src, shiftreg); 16385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 16395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sshll(VectorFormat vform, 16425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 16435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 16445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 16455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(shift >= 0); 16465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 16475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shiftreg = dup_immediate(vform, temp1, shift); 16485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister extendedreg = sxtl(vform, temp2, src); 16495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sshl(vform, dst, extendedreg, shiftreg); 16505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 16515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sshll2(VectorFormat vform, 16545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 16555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 16565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 16575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(shift >= 0); 16585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 16595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shiftreg = dup_immediate(vform, temp1, shift); 16605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister extendedreg = sxtl2(vform, temp2, src); 16615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sshl(vform, dst, extendedreg, shiftreg); 16625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 16635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::shll(VectorFormat vform, 16665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 16675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 16685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift = LaneSizeInBitsFromFormat(vform) / 2; 16695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sshll(vform, dst, src, shift); 16705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 16715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::shll2(VectorFormat vform, 16745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 16755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 16765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift = LaneSizeInBitsFromFormat(vform) / 2; 16775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sshll2(vform, dst, src, shift); 16785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 16795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ushll(VectorFormat vform, 16825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 16835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 16845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 16855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(shift >= 0); 16865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 16875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shiftreg = dup_immediate(vform, temp1, shift); 16885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister extendedreg = uxtl(vform, temp2, src); 16895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return ushl(vform, dst, extendedreg, shiftreg); 16905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 16915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 16935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ushll2(VectorFormat vform, 16945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 16955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 16965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 16975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(shift >= 0); 16985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 16995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shiftreg = dup_immediate(vform, temp1, shift); 17005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister extendedreg = uxtl2(vform, temp2, src); 17015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return ushl(vform, dst, extendedreg, shiftreg); 17025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 17035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sli(VectorFormat vform, 17065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 17075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 17085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 17095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 17105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 17115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; i++) { 17125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t src_lane = src.Uint(vform, i); 17135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t dst_lane = dst.Uint(vform, i); 17145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t shifted = src_lane << shift; 17155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t mask = MaxUintFromFormat(vform) << shift; 17165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, (dst_lane & ~mask) | shifted); 17175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 17185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 17195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 17205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqshl(VectorFormat vform, 17235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 17245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 17255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 17265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(shift >= 0); 17275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 17285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shiftreg = dup_immediate(vform, temp, shift); 17295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sshl(vform, dst, src, shiftreg).SignedSaturate(vform); 17305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 17315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uqshl(VectorFormat vform, 17345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 17355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 17365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 17375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(shift >= 0); 17385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 17395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shiftreg = dup_immediate(vform, temp, shift); 17405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return ushl(vform, dst, src, shiftreg).UnsignedSaturate(vform); 17415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 17425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqshlu(VectorFormat vform, 17455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 17465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 17475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 17485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(shift >= 0); 17495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 17505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shiftreg = dup_immediate(vform, temp, shift); 17515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sshl(vform, dst, src, shiftreg).UnsignedSaturate(vform); 17525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 17535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sri(VectorFormat vform, 17565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 17575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 17585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 17595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 17605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 17615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT((shift > 0) && 17625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (shift <= static_cast<int>(LaneSizeInBitsFromFormat(vform)))); 17635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; i++) { 17645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t src_lane = src.Uint(vform, i); 17655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t dst_lane = dst.Uint(vform, i); 17665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t shifted; 17675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t mask; 17685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (shift == 64) { 17695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl shifted = 0; 17705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mask = 0; 17715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 17725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl shifted = src_lane >> shift; 17735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mask = MaxUintFromFormat(vform) >> shift; 17745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 17755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, (dst_lane & ~mask) | shifted); 17765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 17775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 17785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 17795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ushr(VectorFormat vform, 17825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 17835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 17845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 17855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(shift >= 0); 17865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 17875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shiftreg = dup_immediate(vform, temp, -shift); 17885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return ushl(vform, dst, src, shiftreg); 17895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 17905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 17925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sshr(VectorFormat vform, 17935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 17945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 17955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 17965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(shift >= 0); 17975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 17985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shiftreg = dup_immediate(vform, temp, -shift); 17995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sshl(vform, dst, src, shiftreg); 18005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 18015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ssra(VectorFormat vform, 18045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 18055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 18065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 18075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 18085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_reg = sshr(vform, temp, src, shift); 18095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return add(vform, dst, dst, shifted_reg); 18105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 18115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::usra(VectorFormat vform, 18145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 18155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 18165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 18175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 18185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_reg = ushr(vform, temp, src, shift); 18195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return add(vform, dst, dst, shifted_reg); 18205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 18215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::srsra(VectorFormat vform, 18245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 18255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 18265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 18275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 18285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_reg = sshr(vform, temp, src, shift).Round(vform); 18295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return add(vform, dst, dst, shifted_reg); 18305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 18315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ursra(VectorFormat vform, 18345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 18355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 18365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 18375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 18385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_reg = ushr(vform, temp, src, shift).Round(vform); 18395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return add(vform, dst, dst, shifted_reg); 18405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 18415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::cls(VectorFormat vform, 18445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 18455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 18465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[16]; 18470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int laneSizeInBits = LaneSizeInBitsFromFormat(vform); 18485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 18495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; i++) { 18505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[i] = CountLeadingSignBits(src.Int(vform, i), laneSizeInBits); 18515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 18525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 18545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 18555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[i]); 18565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 18575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 18585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 18595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::clz(VectorFormat vform, 18625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 18635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 18645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[16]; 18650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int laneSizeInBits = LaneSizeInBitsFromFormat(vform); 18665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 18675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; i++) { 18685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[i] = CountLeadingZeros(src.Uint(vform, i), laneSizeInBits); 18695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 18705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 18725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 18735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[i]); 18745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 18755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 18765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 18775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::cnt(VectorFormat vform, 18805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 18815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 18825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[16]; 18830f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int laneSizeInBits = LaneSizeInBitsFromFormat(vform); 18845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 18855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; i++) { 18865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t value = src.Uint(vform, i); 18875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[i] = 0; 18885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int j = 0; j < laneSizeInBits; j++) { 18895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[i] += (value & 1); 18905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl value >>= 1; 18915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 18925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 18935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 18945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 18955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 18965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[i]); 18975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 18985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 18995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 19005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sshl(VectorFormat vform, 19035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 19065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 19075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 19085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int8_t shift_val = src2.Int(vform, i); 19095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t lj_src_val = src1.IntLeftJustified(vform, i); 19105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Set signed saturation state. 19120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if ((shift_val > CountLeadingSignBits(lj_src_val)) && (lj_src_val != 0)) { 19135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetSignedSat(i, lj_src_val >= 0); 19145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Set unsigned saturation state. 19175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (lj_src_val < 0) { 19185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUnsignedSat(i, false); 19196e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if ((shift_val > CountLeadingZeros(lj_src_val)) && 19205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (lj_src_val != 0)) { 19215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUnsignedSat(i, true); 19225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t src_val = src1.Int(vform, i); 19255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (shift_val > 63) { 19265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, 0); 19275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (shift_val < -63) { 19285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetRounding(i, src_val < 0); 19295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, (src_val < 0) ? -1 : 0); 19305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 19315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (shift_val < 0) { 19325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Set rounding state. Rounding only needed on right shifts. 19335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (((src_val >> (-shift_val - 1)) & 1) == 1) { 19345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetRounding(i, true); 19355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl src_val >>= -shift_val; 19375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 19385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl src_val <<= shift_val; 19395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, src_val); 19415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 19445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 19455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ushl(VectorFormat vform, 19485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 19505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 19515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 19525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 19535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int8_t shift_val = src2.Int(vform, i); 19545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t lj_src_val = src1.UintLeftJustified(vform, i); 19555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Set saturation state. 19576e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if ((shift_val > CountLeadingZeros(lj_src_val)) && (lj_src_val != 0)) { 19585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUnsignedSat(i, true); 19595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t src_val = src1.Uint(vform, i); 19625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((shift_val > 63) || (shift_val < -64)) { 19635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, 0); 19645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 19655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (shift_val < 0) { 19665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Set rounding state. Rounding only needed on right shifts. 19675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (((src_val >> (-shift_val - 1)) & 1) == 1) { 19685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetRounding(i, true); 19695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (shift_val == -64) { 19725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl src_val = 0; 19735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 19745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl src_val >>= -shift_val; 19755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 19775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl src_val <<= shift_val; 19785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, src_val); 19805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 19835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 19845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 19865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::neg(VectorFormat vform, 19875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 19885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 19895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 19905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 19915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Test for signed saturation. 19925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t sa = src.Int(vform, i); 19935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sa == MinIntFromFormat(vform)) { 19945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetSignedSat(i, true); 19955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, -sa); 19975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 19985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 19995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 20005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 20015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 20025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::suqadd(VectorFormat vform, 20035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 20055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 20065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 20070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t sa = dst.IntLeftJustified(vform, i); 20085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t ub = src.UintLeftJustified(vform, i); 20090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t sr = sa + ub; 20105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 20115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sr < sa) { // Test for signed positive saturation. 20125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, MaxIntFromFormat(vform)); 20135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 20145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, dst.Int(vform, i) + src.Int(vform, i)); 20155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 20165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 20175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 20185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 20195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 20205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 20215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::usqadd(VectorFormat vform, 20225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 20245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 20255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 20260f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t ua = dst.UintLeftJustified(vform, i); 20270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t sb = src.IntLeftJustified(vform, i); 20280f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uint64_t ur = ua + sb; 20295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 20305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((sb > 0) && (ur <= ua)) { 20315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, MaxUintFromFormat(vform)); // Positive saturation. 20325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if ((sb < 0) && (ur >= ua)) { 20330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, i, 0); // Negative saturation. 20345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 20355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, dst.Uint(vform, i) + src.Int(vform, i)); 20365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 20375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 20385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 20395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 20405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 20415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 20425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::abs(VectorFormat vform, 20435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 20455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 20465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 20475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Test for signed saturation. 20485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t sa = src.Int(vform, i); 20495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sa == MinIntFromFormat(vform)) { 20505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetSignedSat(i, true); 20515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 20525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sa < 0) { 20535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, -sa); 20545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 20555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, sa); 20565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 20575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 20585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 20595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 20605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 20615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 20625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::extractnarrow(VectorFormat dstform, 20635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 20645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool dstIsSigned, 20655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 20665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool srcIsSigned) { 20675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool upperhalf = false; 20685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat srcform = kFormatUndefined; 20690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t ssrc[8]; 20705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t usrc[8]; 20715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 20725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (dstform) { 20730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kFormat8B: 20740f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl upperhalf = false; 20750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl srcform = kFormat8H; 20760f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 20770f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kFormat16B: 20780f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl upperhalf = true; 20790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl srcform = kFormat8H; 20800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 20810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kFormat4H: 20820f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl upperhalf = false; 20830f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl srcform = kFormat4S; 20840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 20850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kFormat8H: 20860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl upperhalf = true; 20870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl srcform = kFormat4S; 20880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 20890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kFormat2S: 20900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl upperhalf = false; 20910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl srcform = kFormat2D; 20920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 20930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kFormat4S: 20940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl upperhalf = true; 20950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl srcform = kFormat2D; 20960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 20970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kFormatB: 20980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl upperhalf = false; 20990f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl srcform = kFormatH; 21000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 21010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kFormatH: 21020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl upperhalf = false; 21030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl srcform = kFormatS; 21040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 21050f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case kFormatS: 21060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl upperhalf = false; 21070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl srcform = kFormatD; 21080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 21090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 21100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNIMPLEMENTED(); 21115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 21125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(srcform); i++) { 21145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl ssrc[i] = src.Int(srcform, i); 21155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl usrc[i] = src.Uint(srcform, i); 21165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 21175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int offset; 21195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (upperhalf) { 21205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl offset = LaneCountFromFormat(dstform) / 2; 21215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 21225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl offset = 0; 21235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(dstform); 21245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 21255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(srcform); i++) { 21275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Test for signed saturation 21285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (ssrc[i] > MaxIntFromFormat(dstform)) { 21295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetSignedSat(offset + i, true); 21305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (ssrc[i] < MinIntFromFormat(dstform)) { 21315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetSignedSat(offset + i, false); 21325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 21335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Test for unsigned saturation 21355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (srcIsSigned) { 21365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (ssrc[i] > static_cast<int64_t>(MaxUintFromFormat(dstform))) { 21375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUnsignedSat(offset + i, true); 21385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (ssrc[i] < 0) { 21395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUnsignedSat(offset + i, false); 21405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 21415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 21425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (usrc[i] > MaxUintFromFormat(dstform)) { 21435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUnsignedSat(offset + i, true); 21445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 21455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 21465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t result; 21485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (srcIsSigned) { 21495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result = ssrc[i] & MaxUintFromFormat(dstform); 21505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 21515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result = usrc[i] & MaxUintFromFormat(dstform); 21525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 21535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (dstIsSigned) { 21555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(dstform, offset + i, result); 21565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 21575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(dstform, offset + i, result); 21585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 21595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 21605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 21615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 21625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::xtn(VectorFormat vform, 21655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 21675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return extractnarrow(vform, dst, true, src, true); 21685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 21695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqxtn(VectorFormat vform, 21725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 21745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return extractnarrow(vform, dst, true, src, true).SignedSaturate(vform); 21755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 21765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqxtun(VectorFormat vform, 21795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 21815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return extractnarrow(vform, dst, false, src, true).UnsignedSaturate(vform); 21825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 21835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uqxtn(VectorFormat vform, 21865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 21885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return extractnarrow(vform, dst, false, src, false).UnsignedSaturate(vform); 21895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 21905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 21925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::absdiff(VectorFormat vform, 21935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 21945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 21955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 21965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool issigned) { 21975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 21985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 21995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (issigned) { 22005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t sr = src1.Int(vform, i) - src2.Int(vform, i); 22015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sr = sr > 0 ? sr : -sr; 22025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, sr); 22035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 22045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t sr = src1.Uint(vform, i) - src2.Uint(vform, i); 22055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sr = sr > 0 ? sr : -sr; 22065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, sr); 22075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 22085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 22095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 22105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 22115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::saba(VectorFormat vform, 22145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 22175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 22185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 22195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl absdiff(vform, temp, src1, src2, true); 22205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(vform, dst, dst, temp); 22215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 22225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 22235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uaba(VectorFormat vform, 22265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 22285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 22295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 22305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 22315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl absdiff(vform, temp, src1, src2, false); 22325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(vform, dst, dst, temp); 22335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 22345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 22355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::not_(VectorFormat vform, 22385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 22405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 22415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 22425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, ~src.Uint(vform, i)); 22435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 22445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 22455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 22465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::rbit(VectorFormat vform, 22495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 22515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[16]; 22525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 22530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int laneSizeInBits = LaneSizeInBitsFromFormat(vform); 22545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t reversed_value; 22555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t value; 22565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; i++) { 22575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl value = src.Uint(vform, i); 22585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl reversed_value = 0; 22595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int j = 0; j < laneSizeInBits; j++) { 22605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl reversed_value = (reversed_value << 1) | (value & 1); 22615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl value >>= 1; 22625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 22635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[i] = reversed_value; 22645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 22655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 22675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 22685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[i]); 22695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 22705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 22715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 22725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::rev(VectorFormat vform, 22755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 22775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int revSize) { 22785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[16]; 22795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 22805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneSize = LaneSizeInBytesFromFormat(vform); 22810f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int lanesPerLoop = revSize / laneSize; 22825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; i += lanesPerLoop) { 22835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int j = 0; j < lanesPerLoop; j++) { 22845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[i + lanesPerLoop - 1 - j] = src.Uint(vform, i + j); 22855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 22865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 22875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 22885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 22895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[i]); 22905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 22915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 22925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 22935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 22955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::rev16(VectorFormat vform, 22965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 22975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 22985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return rev(vform, dst, src, 2); 22995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 23005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::rev32(VectorFormat vform, 23035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 23055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return rev(vform, dst, src, 4); 23065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 23075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::rev64(VectorFormat vform, 23105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 23125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return rev(vform, dst, src, 8); 23135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 23145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::addlp(VectorFormat vform, 23170f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 23180f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src, 23190f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool is_signed, 23200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl bool do_accumulate) { 23215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformsrc = VectorFormatHalfWidthDoubleLanes(vform); 23225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23230f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int64_t sr[16]; 23245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t ur[16]; 23255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 23275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 23285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (is_signed) { 23295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sr[i] = src.Int(vformsrc, 2 * i) + src.Int(vformsrc, 2 * i + 1); 23305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 23315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl ur[i] = src.Uint(vformsrc, 2 * i) + src.Uint(vformsrc, 2 * i + 1); 23325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 23335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 23345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 23365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 23375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (do_accumulate) { 23385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (is_signed) { 23395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, dst.Int(vform, i) + sr[i]); 23405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 23415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, dst.Uint(vform, i) + ur[i]); 23425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 23435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 23445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (is_signed) { 23455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, sr[i]); 23465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 23475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, ur[i]); 23485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 23495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 23505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 23515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 23535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 23545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::saddlp(VectorFormat vform, 23575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 23595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return addlp(vform, dst, src, true, false); 23605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 23615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uaddlp(VectorFormat vform, 23645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 23665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return addlp(vform, dst, src, false, false); 23675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 23685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sadalp(VectorFormat vform, 23715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 23735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return addlp(vform, dst, src, true, true); 23745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 23755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uadalp(VectorFormat vform, 23785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 23805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return addlp(vform, dst, src, false, true); 23815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 23825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 23845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ext(VectorFormat vform, 23855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 23865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 23875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 23885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 23895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint8_t result[16]; 23905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 23915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount - index; ++i) { 23925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[i] = src1.Uint(vform, i + index); 23935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 23945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < index; ++i) { 23955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[laneCount - index + i] = src2.Uint(vform, i); 23965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 23975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 23985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 23995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[i]); 24005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 24015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 24025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 24035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::dup_element(VectorFormat vform, 24065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int src_index) { 24095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 24105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t value = src.Uint(vform, src_index); 24115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 24125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 24135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, value); 24145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 24155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 24165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 24175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::dup_immediate(VectorFormat vform, 24205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm) { 24225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 24235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t value = imm & MaxUintFromFormat(vform); 24245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 24255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 24265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, value); 24275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 24285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 24295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 24305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ins_element(VectorFormat vform, 24335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int dst_index, 24355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int src_index) { 24375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, dst_index, src.Uint(vform, src_index)); 24385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 24395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 24405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ins_immediate(VectorFormat vform, 24435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int dst_index, 24455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm) { 24465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t value = imm & MaxUintFromFormat(vform); 24475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, dst_index, value); 24485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 24495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 24505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::movi(VectorFormat vform, 24535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm) { 24555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 24565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 24575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 24585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, imm); 24595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 24605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 24615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 24625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::mvni(VectorFormat vform, 24655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm) { 24675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 24685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 24695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 24705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, ~imm); 24715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 24725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 24735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 24745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::orr(VectorFormat vform, 24775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 24795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t imm) { 24805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[16]; 24815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 24825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 24835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[i] = src.Uint(vform, i) | imm; 24845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 24855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 24865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 24875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[i]); 24885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 24895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 24905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 24915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uxtl(VectorFormat vform, 24945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 24955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 24965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vform_half = VectorFormatHalfWidth(vform); 24975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 24985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 24995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 25005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, src.Uint(vform_half, i)); 25015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 25025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 25035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 25045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sxtl(VectorFormat vform, 25075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 25095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vform_half = VectorFormatHalfWidth(vform); 25105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 25125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 25135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, src.Int(vform_half, i)); 25145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 25155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 25165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 25175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uxtl2(VectorFormat vform, 25205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 25225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vform_half = VectorFormatHalfWidth(vform); 25235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int lane_count = LaneCountFromFormat(vform); 25245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 25265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < lane_count; i++) { 25275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, src.Uint(vform_half, lane_count + i)); 25285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 25295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 25305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 25315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sxtl2(VectorFormat vform, 25345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 25365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vform_half = VectorFormatHalfWidth(vform); 25375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int lane_count = LaneCountFromFormat(vform); 25385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 25405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < lane_count; i++) { 25415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, src.Int(vform_half, lane_count + i)); 25425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 25435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 25445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 25455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::shrn(VectorFormat vform, 25485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 25515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 25525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vform_src = VectorFormatDoubleWidth(vform); 25535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vform_dst = vform; 25545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_src = ushr(vform_src, temp, src, shift); 25555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return extractnarrow(vform_dst, dst, false, shifted_src, false); 25565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 25575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::shrn2(VectorFormat vform, 25605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 25635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 25645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformsrc = VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)); 25655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformdst = vform; 25665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_src = ushr(vformsrc, temp, src, shift); 25675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return extractnarrow(vformdst, dst, false, shifted_src, false); 25685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 25695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::rshrn(VectorFormat vform, 25725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 25755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 25765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformsrc = VectorFormatDoubleWidth(vform); 25775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformdst = vform; 25785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_src = ushr(vformsrc, temp, src, shift).Round(vformsrc); 25795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return extractnarrow(vformdst, dst, false, shifted_src, false); 25805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 25815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::rshrn2(VectorFormat vform, 25845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 25865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 25875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 25885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformsrc = VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)); 25895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformdst = vform; 25905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_src = ushr(vformsrc, temp, src, shift).Round(vformsrc); 25915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return extractnarrow(vformdst, dst, false, shifted_src, false); 25925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 25935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 25955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::tbl(VectorFormat vform, 25965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 25975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 25985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind) { 25990f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl movi(vform, dst, 0); 26000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return tbx(vform, dst, tab, ind); 26015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 26025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::tbl(VectorFormat vform, 26055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 26075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 26085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind) { 26090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl movi(vform, dst, 0); 26100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return tbx(vform, dst, tab, tab2, ind); 26115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 26125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::tbl(VectorFormat vform, 26155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 26175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 26185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 26195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind) { 26200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl movi(vform, dst, 0); 26210f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return tbx(vform, dst, tab, tab2, tab3, ind); 26225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 26235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::tbl(VectorFormat vform, 26265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 26285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 26295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 26305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab4, 26315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind) { 26320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl movi(vform, dst, 0); 26330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return tbx(vform, dst, tab, tab2, tab3, tab4, ind); 26345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 26355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::tbx(VectorFormat vform, 26385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 26405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind) { 26415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 26425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 2643db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint64_t j = ind.Uint(vform, i); 26445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (j >> 4) { 26450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 0: 26460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, i, tab.Uint(kFormat16B, j & 15)); 26470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 26485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 26495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 26505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 26515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 26525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::tbx(VectorFormat vform, 26555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 26575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 26585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind) { 26595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 26605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 2661db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint64_t j = ind.Uint(vform, i); 26625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (j >> 4) { 26630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 0: 26640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, i, tab.Uint(kFormat16B, j & 15)); 26650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 26660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 1: 26670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, i, tab2.Uint(kFormat16B, j & 15)); 26680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 26695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 26705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 26715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 26725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 26735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::tbx(VectorFormat vform, 26765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 26775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 26785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 26795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 26805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind) { 26815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 26825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 2683db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint64_t j = ind.Uint(vform, i); 26845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (j >> 4) { 26850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 0: 26860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, i, tab.Uint(kFormat16B, j & 15)); 26870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 26880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 1: 26890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, i, tab2.Uint(kFormat16B, j & 15)); 26900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 26910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 2: 26920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, i, tab3.Uint(kFormat16B, j & 15)); 26930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 26945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 26955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 26965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 26975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 26985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 26995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::tbx(VectorFormat vform, 27015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab, 27035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab2, 27045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab3, 27055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& tab4, 27065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& ind) { 27075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 27085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 2709db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint64_t j = ind.Uint(vform, i); 27105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (j >> 4) { 27110f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 0: 27120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, i, tab.Uint(kFormat16B, j & 15)); 27130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 27140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 1: 27150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, i, tab2.Uint(kFormat16B, j & 15)); 27160f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 27170f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 2: 27180f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, i, tab3.Uint(kFormat16B, j & 15)); 27190f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 27200f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case 3: 27210f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, i, tab4.Uint(kFormat16B, j & 15)); 27220f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 27235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 27245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 27255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 27265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 27275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uqshrn(VectorFormat vform, 27305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 27325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 27335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return shrn(vform, dst, src, shift).UnsignedSaturate(vform); 27345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 27355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uqshrn2(VectorFormat vform, 27385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 27405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 27415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return shrn2(vform, dst, src, shift).UnsignedSaturate(vform); 27425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 27435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uqrshrn(VectorFormat vform, 27465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 27485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 27495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return rshrn(vform, dst, src, shift).UnsignedSaturate(vform); 27505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 27515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uqrshrn2(VectorFormat vform, 27545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 27565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 27575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return rshrn2(vform, dst, src, shift).UnsignedSaturate(vform); 27585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 27595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqshrn(VectorFormat vform, 27625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 27645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 27655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 27665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformsrc = VectorFormatDoubleWidth(vform); 27675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformdst = vform; 27685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift); 27695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqxtn(vformdst, dst, shifted_src); 27705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 27715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqshrn2(VectorFormat vform, 27745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 27765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 27775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 27785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformsrc = VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)); 27795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformdst = vform; 27805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift); 27815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqxtn(vformdst, dst, shifted_src); 27825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 27835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqrshrn(VectorFormat vform, 27865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 27885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 27895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 27905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformsrc = VectorFormatDoubleWidth(vform); 27915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformdst = vform; 27925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc); 27935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqxtn(vformdst, dst, shifted_src); 27945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 27955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 27975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqrshrn2(VectorFormat vform, 27985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 27995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 28015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 28025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformsrc = VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)); 28035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformdst = vform; 28045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc); 28055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqxtn(vformdst, dst, shifted_src); 28065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 28075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqshrun(VectorFormat vform, 28105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 28135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 28145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformsrc = VectorFormatDoubleWidth(vform); 28155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformdst = vform; 28165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift); 28175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqxtun(vformdst, dst, shifted_src); 28185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 28195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqshrun2(VectorFormat vform, 28225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 28255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 28265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformsrc = VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)); 28275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformdst = vform; 28285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift); 28295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqxtun(vformdst, dst, shifted_src); 28305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 28315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqrshrun(VectorFormat vform, 28345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 28375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 28385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformsrc = VectorFormatDoubleWidth(vform); 28395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformdst = vform; 28405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc); 28415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqxtun(vformdst, dst, shifted_src); 28425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 28435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqrshrun2(VectorFormat vform, 28465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 28485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int shift) { 28495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 28505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformsrc = VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)); 28515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VectorFormat vformdst = vform; 28525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister shifted_src = sshr(vformsrc, temp, src, shift).Round(vformsrc); 28535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqxtun(vformdst, dst, shifted_src); 28545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 28555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uaddl(VectorFormat vform, 28585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 28615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 28625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp1, src1); 28635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp2, src2); 28645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(vform, dst, temp1, temp2); 28655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 28665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 28675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uaddl2(VectorFormat vform, 28705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 28735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 28745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp1, src1); 28755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp2, src2); 28765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(vform, dst, temp1, temp2); 28775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 28785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 28795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uaddw(VectorFormat vform, 28825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 28855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 28865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp, src2); 28875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(vform, dst, src1, temp); 28885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 28895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 28905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 28925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uaddw2(VectorFormat vform, 28935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 28945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 28955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 28965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 28975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp, src2); 28985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(vform, dst, src1, temp); 28995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 29005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 29015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::saddl(VectorFormat vform, 29045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 29065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 29075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 29085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp1, src1); 29095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp2, src2); 29105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(vform, dst, temp1, temp2); 29115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 29125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 29135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::saddl2(VectorFormat vform, 29165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 29185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 29195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 29205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp1, src1); 29215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp2, src2); 29225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(vform, dst, temp1, temp2); 29235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 29245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 29255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::saddw(VectorFormat vform, 29285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 29305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 29315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 29325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp, src2); 29335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(vform, dst, src1, temp); 29345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 29355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 29365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::saddw2(VectorFormat vform, 29395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 29415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 29425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 29435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp, src2); 29445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(vform, dst, src1, temp); 29455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 29465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 29475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::usubl(VectorFormat vform, 29505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 29525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 29535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 29545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp1, src1); 29555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp2, src2); 29565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(vform, dst, temp1, temp2); 29575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 29585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 29595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::usubl2(VectorFormat vform, 29625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 29645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 29655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 29665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp1, src1); 29675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp2, src2); 29685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(vform, dst, temp1, temp2); 29695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 29705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 29715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::usubw(VectorFormat vform, 29745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 29765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 29775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 29785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp, src2); 29795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(vform, dst, src1, temp); 29805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 29815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 29825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::usubw2(VectorFormat vform, 29855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 29875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 29885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 29895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp, src2); 29905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(vform, dst, src1, temp); 29915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 29925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 29935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 29955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ssubl(VectorFormat vform, 29965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 29975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 29985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 29995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 30005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp1, src1); 30015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp2, src2); 30025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(vform, dst, temp1, temp2); 30035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 30045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 30055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ssubl2(VectorFormat vform, 30085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 30095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 30105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 30115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 30125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp1, src1); 30135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp2, src2); 30145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(vform, dst, temp1, temp2); 30155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 30165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 30175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ssubw(VectorFormat vform, 30205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 30215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 30225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 30235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 30245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp, src2); 30255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(vform, dst, src1, temp); 30265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 30275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 30285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ssubw2(VectorFormat vform, 30315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 30325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 30335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 30345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 30355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp, src2); 30365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(vform, dst, src1, temp); 30375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 30385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 30395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uabal(VectorFormat vform, 30425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 30435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 30445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 30455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 30465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp1, src1); 30475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp2, src2); 30485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uaba(vform, dst, temp1, temp2); 30495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 30505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 30515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uabal2(VectorFormat vform, 30545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 30555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 30565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 30575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 30585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp1, src1); 30595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp2, src2); 30605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uaba(vform, dst, temp1, temp2); 30615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 30625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 30635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sabal(VectorFormat vform, 30665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 30675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 30685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 30695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 30705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp1, src1); 30715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp2, src2); 30725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl saba(vform, dst, temp1, temp2); 30735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 30745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 30755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sabal2(VectorFormat vform, 30785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 30795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 30805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 30815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 30825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp1, src1); 30835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp2, src2); 30845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl saba(vform, dst, temp1, temp2); 30855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 30865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 30875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 30895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uabdl(VectorFormat vform, 30905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 30915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 30925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 30935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 30945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp1, src1); 30955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp2, src2); 30965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl absdiff(vform, dst, temp1, temp2, false); 30975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 30985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 30995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uabdl2(VectorFormat vform, 31025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 31035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 31045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 31055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 31065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp1, src1); 31075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp2, src2); 31085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl absdiff(vform, dst, temp1, temp2, false); 31095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 31105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 31115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sabdl(VectorFormat vform, 31145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 31155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 31165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 31175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 31185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp1, src1); 31195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp2, src2); 31205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl absdiff(vform, dst, temp1, temp2, true); 31215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 31225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 31235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sabdl2(VectorFormat vform, 31265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 31275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 31285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 31295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 31305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp1, src1); 31315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp2, src2); 31325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl absdiff(vform, dst, temp1, temp2, true); 31335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 31345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 31355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umull(VectorFormat vform, 31385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 31395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 31405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 31415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 31425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp1, src1); 31435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp2, src2); 31445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mul(vform, dst, temp1, temp2); 31455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 31465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 31475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umull2(VectorFormat vform, 31505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 31515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 31525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 31535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 31545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp1, src1); 31555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp2, src2); 31565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mul(vform, dst, temp1, temp2); 31575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 31585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 31595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smull(VectorFormat vform, 31625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 31635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 31645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 31655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 31665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp1, src1); 31675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp2, src2); 31685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mul(vform, dst, temp1, temp2); 31695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 31705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 31715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smull2(VectorFormat vform, 31745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 31755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 31765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 31775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 31785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp1, src1); 31795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp2, src2); 31805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mul(vform, dst, temp1, temp2); 31815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 31825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 31835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umlsl(VectorFormat vform, 31865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 31875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 31885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 31895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 31905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp1, src1); 31915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp2, src2); 31925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mls(vform, dst, temp1, temp2); 31935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 31945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 31955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 31975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umlsl2(VectorFormat vform, 31985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 31995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 32005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 32015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 32025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp1, src1); 32035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp2, src2); 32045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mls(vform, dst, temp1, temp2); 32055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 32065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 32075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smlsl(VectorFormat vform, 32105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 32115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 32125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 32135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 32145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp1, src1); 32155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp2, src2); 32165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mls(vform, dst, temp1, temp2); 32175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 32185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 32195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smlsl2(VectorFormat vform, 32225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 32235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 32245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 32255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 32265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp1, src1); 32275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp2, src2); 32285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mls(vform, dst, temp1, temp2); 32295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 32305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 32315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umlal(VectorFormat vform, 32345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 32355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 32365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 32375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 32385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp1, src1); 32395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl(vform, temp2, src2); 32405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mla(vform, dst, temp1, temp2); 32415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 32425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 32435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::umlal2(VectorFormat vform, 32465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 32475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 32485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 32495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 32505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp1, src1); 32515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uxtl2(vform, temp2, src2); 32525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mla(vform, dst, temp1, temp2); 32535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 32545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 32555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smlal(VectorFormat vform, 32585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 32595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 32605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 32615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 32625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp1, src1); 32635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl(vform, temp2, src2); 32645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mla(vform, dst, temp1, temp2); 32655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 32665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 32675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::smlal2(VectorFormat vform, 32705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 32715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 32725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 32735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 32745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp1, src1); 32755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sxtl2(vform, temp2, src2); 32765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl mla(vform, dst, temp1, temp2); 32775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 32785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 32795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmlal(VectorFormat vform, 32825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 32835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 32845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 32855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 32865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister product = sqdmull(vform, temp, src1, src2); 32875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return add(vform, dst, dst, product).SignedSaturate(vform); 32885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 32895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 32915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmlal2(VectorFormat vform, 32920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 32930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 32940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2) { 32955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 32965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister product = sqdmull2(vform, temp, src1, src2); 32975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return add(vform, dst, dst, product).SignedSaturate(vform); 32985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 32995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmlsl(VectorFormat vform, 33025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 33035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 33045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 33055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 33065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister product = sqdmull(vform, temp, src1, src2); 33075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sub(vform, dst, dst, product).SignedSaturate(vform); 33085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 33095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmlsl2(VectorFormat vform, 33120f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 33130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 33140f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2) { 33155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 33165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister product = sqdmull2(vform, temp, src1, src2); 33175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sub(vform, dst, dst, product).SignedSaturate(vform); 33185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 33195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmull(VectorFormat vform, 33225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 33235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 33245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 33255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 33265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister product = smull(vform, temp, src1, src2); 33275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return add(vform, dst, product, product).SignedSaturate(vform); 33285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 33295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmull2(VectorFormat vform, 33320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 33330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, 33340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2) { 33355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 33365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister product = smull2(vform, temp, src1, src2); 33375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return add(vform, dst, product, product).SignedSaturate(vform); 33385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 33395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqrdmulh(VectorFormat vform, 33425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 33435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 33445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 33455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool round) { 33465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // 2 * INT_32_MIN * INT_32_MIN causes int64_t to overflow. 33475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // To avoid this, we use (src1 * src2 + 1 << (esize - 2)) >> (esize - 1) 33485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // which is same as (2 * src1 * src2 + 1 << (esize - 1)) >> esize. 33495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int esize = LaneSizeInBitsFromFormat(vform); 33515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int round_const = round ? (1 << (esize - 2)) : 0; 33525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int64_t product; 33535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 33555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 33565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl product = src1.Int(vform, i) * src2.Int(vform, i); 33575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl product += round_const; 33585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl product = product >> (esize - 1); 33595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (product > MaxIntFromFormat(vform)) { 33615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl product = MaxIntFromFormat(vform); 33625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (product < MinIntFromFormat(vform)) { 33635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl product = MinIntFromFormat(vform); 33645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 33655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, product); 33665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 33675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 33685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 33695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::sqdmulh(VectorFormat vform, 33725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 33735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 33745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 33755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqrdmulh(vform, dst, src1, src2, false); 33765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 33775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::addhn(VectorFormat vform, 33805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 33815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 33825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 33835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 33845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(VectorFormatDoubleWidth(vform), temp, src1, src2); 33855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); 33865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 33875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 33885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 33905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::addhn2(VectorFormat vform, 33915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 33925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 33935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 33945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 33955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2); 33965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); 33975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 33985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 33995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::raddhn(VectorFormat vform, 34025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 34035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 34045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 34055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 34065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(VectorFormatDoubleWidth(vform), temp, src1, src2); 34075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl rshrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); 34085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 34095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 34105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::raddhn2(VectorFormat vform, 34135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 34145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 34155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 34165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 34175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2); 34185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); 34195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 34205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 34215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::subhn(VectorFormat vform, 34245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 34255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 34265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 34275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 34285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(VectorFormatDoubleWidth(vform), temp, src1, src2); 34295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl shrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); 34305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 34315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 34325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::subhn2(VectorFormat vform, 34355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 34365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 34375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 34385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 34395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2); 34405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl shrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); 34415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 34425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 34435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::rsubhn(VectorFormat vform, 34465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 34475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 34485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 34495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 34505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(VectorFormatDoubleWidth(vform), temp, src1, src2); 34515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl rshrn(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); 34525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 34535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 34545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::rsubhn2(VectorFormat vform, 34575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 34585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 34595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 34605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 34615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2); 34625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); 34635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 34645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 34655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::trn1(VectorFormat vform, 34685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 34695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 34705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 34715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[16]; 34725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 34735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int pairs = laneCount / 2; 34745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < pairs; ++i) { 34750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result[2 * i] = src1.Uint(vform, 2 * i); 34765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[(2 * i) + 1] = src2.Uint(vform, 2 * i); 34775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 34785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 34805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 34815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[i]); 34825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 34835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 34845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 34855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::trn2(VectorFormat vform, 34885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 34895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 34905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 34915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[16]; 34925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 34935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int pairs = laneCount / 2; 34945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < pairs; ++i) { 34950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result[2 * i] = src1.Uint(vform, (2 * i) + 1); 34965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[(2 * i) + 1] = src2.Uint(vform, (2 * i) + 1); 34975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 34985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 34995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 35005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 35015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[i]); 35025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 35035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 35045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 35055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::zip1(VectorFormat vform, 35085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 35095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 35105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 35115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[16]; 35125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 35135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int pairs = laneCount / 2; 35145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < pairs; ++i) { 35150f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result[2 * i] = src1.Uint(vform, i); 35165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[(2 * i) + 1] = src2.Uint(vform, i); 35175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 35185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 35205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 35215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[i]); 35225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 35235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 35245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 35255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::zip2(VectorFormat vform, 35285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 35295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 35305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 35315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[16]; 35325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 35335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int pairs = laneCount / 2; 35345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < pairs; ++i) { 35350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result[2 * i] = src1.Uint(vform, pairs + i); 35365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[(2 * i) + 1] = src2.Uint(vform, pairs + i); 35375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 35385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 35405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 35415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[i]); 35425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 35435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 35445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 35455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uzp1(VectorFormat vform, 35485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 35495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 35505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 35515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[32]; 35525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 35535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 35540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result[i] = src1.Uint(vform, i); 35555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[laneCount + i] = src2.Uint(vform, i); 35565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 35575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 35595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 35605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result[2 * i]); 35615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 35625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 35635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 35645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::uzp2(VectorFormat vform, 35675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 35685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 35695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 35705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t result[32]; 35715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int laneCount = LaneCountFromFormat(vform); 35725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 35730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result[i] = src1.Uint(vform, i); 35745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result[laneCount + i] = src2.Uint(vform, i); 35755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 35765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 35785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < laneCount; ++i) { 35790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetUint(vform, i, result[(2 * i) + 1]); 35805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 35815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 35825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 35835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 35865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPAdd(T op1, T op2) { 35875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result = FPProcessNaNs(op1, op2); 35886e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (std::isnan(result)) return result; 35895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 35906e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (std::isinf(op1) && std::isinf(op2) && (op1 != op2)) { 35915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // inf + -inf returns the default NaN. 35925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPProcessException(); 35935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPDefaultNaN<T>(); 35945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 35955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Other cases should be handled by standard arithmetic. 35965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return op1 + op2; 35975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 35985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 35995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 36025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPSub(T op1, T op2) { 36035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // NaNs should be handled elsewhere. 36046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(!std::isnan(op1) && !std::isnan(op2)); 36055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36066e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (std::isinf(op1) && std::isinf(op2) && (op1 == op2)) { 36075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // inf - inf returns the default NaN. 36085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPProcessException(); 36095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPDefaultNaN<T>(); 36105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 36115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Other cases should be handled by standard arithmetic. 36125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return op1 - op2; 36135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 36145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 36155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 36185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPMul(T op1, T op2) { 36195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // NaNs should be handled elsewhere. 36206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(!std::isnan(op1) && !std::isnan(op2)); 36215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36226e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if ((std::isinf(op1) && (op2 == 0.0)) || (std::isinf(op2) && (op1 == 0.0))) { 36235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // inf * 0.0 returns the default NaN. 36245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPProcessException(); 36255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPDefaultNaN<T>(); 36265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 36275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Other cases should be handled by standard arithmetic. 36285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return op1 * op2; 36295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 36305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 36315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltemplate <typename T> 36345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPMulx(T op1, T op2) { 36356e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if ((std::isinf(op1) && (op2 == 0.0)) || (std::isinf(op2) && (op1 == 0.0))) { 36365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // inf * 0.0 returns +/-2.0. 36375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T two = 2.0; 36385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return copysign(1.0, op1) * copysign(1.0, op2) * two; 36395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 36405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPMul(op1, op2); 36415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 36425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixltemplate <typename T> 36455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPMulAdd(T a, T op1, T op2) { 36465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result = FPProcessNaNs3(a, op1, op2); 36475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T sign_a = copysign(1.0, a); 36495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T sign_prod = copysign(1.0, op1) * copysign(1.0, op2); 36506e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl bool isinf_prod = std::isinf(op1) || std::isinf(op2); 36515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool operation_generates_nan = 36526e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl (std::isinf(op1) && (op2 == 0.0)) || // inf * 0.0 36536e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl (std::isinf(op2) && (op1 == 0.0)) || // 0.0 * inf 36546e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl (std::isinf(a) && isinf_prod && (sign_a != sign_prod)); // inf - inf 36555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (std::isnan(result)) { 36575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Generated NaNs override quiet NaNs propagated from a. 36585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (operation_generates_nan && IsQuietNaN(a)) { 36595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPProcessException(); 36605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPDefaultNaN<T>(); 36615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 36625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return result; 36635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 36645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 36655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // If the operation would produce a NaN, return the default NaN. 36675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (operation_generates_nan) { 36685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPProcessException(); 36695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPDefaultNaN<T>(); 36705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 36715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Work around broken fma implementations for exact zero results: The sign of 36735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // exact 0.0 results is positive unless both a and op1 * op2 are negative. 36745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (((op1 == 0.0) || (op2 == 0.0)) && (a == 0.0)) { 36755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return ((sign_a < 0) && (sign_prod < 0)) ? -0.0 : 0.0; 36765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 36775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result = FusedMultiplyAdd(op1, op2, a); 36796e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(!std::isnan(result)); 36805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Work around broken fma implementations for rounded zero results: If a is 36825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // 0.0, the sign of the result is the sign of op1 * op2 before rounding. 36835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((a == 0.0) && (result == 0.0)) { 36845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return copysign(0.0, sign_prod); 36855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 36865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return result; 36885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 36895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 36925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPDiv(T op1, T op2) { 36935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // NaNs should be handled elsewhere. 36946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl VIXL_ASSERT(!std::isnan(op1) && !std::isnan(op2)); 36955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 36966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if ((std::isinf(op1) && std::isinf(op2)) || ((op1 == 0.0) && (op2 == 0.0))) { 36975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // inf / inf and 0.0 / 0.0 return the default NaN. 36985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPProcessException(); 36995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPDefaultNaN<T>(); 37005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 37015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (op2 == 0.0) FPProcessException(); 37025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Other cases should be handled by standard arithmetic. 37045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return op1 / op2; 37055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 37065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 37075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 37105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPSqrt(T op) { 37116e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (std::isnan(op)) { 37125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPProcessNaN(op); 37135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (op < 0.0) { 37145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPProcessException(); 37155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPDefaultNaN<T>(); 37165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 37175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return sqrt(op); 37185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 37195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 37205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 37235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPMax(T a, T b) { 37245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result = FPProcessNaNs(a, b); 37256e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (std::isnan(result)) return result; 37265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37270f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if ((a == 0.0) && (b == 0.0) && (copysign(1.0, a) != copysign(1.0, b))) { 37285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // a and b are zero, and the sign differs: return +0.0. 37295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 0.0; 37305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 37315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return (a > b) ? a : b; 37325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 37335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 37345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 37375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPMaxNM(T a, T b) { 37385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (IsQuietNaN(a) && !IsQuietNaN(b)) { 37395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl a = kFP64NegativeInfinity; 37405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (!IsQuietNaN(a) && IsQuietNaN(b)) { 37415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl b = kFP64NegativeInfinity; 37425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 37435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result = FPProcessNaNs(a, b); 37456e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return std::isnan(result) ? result : FPMax(a, b); 37465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 37475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 37505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPMin(T a, T b) { 37515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result = FPProcessNaNs(a, b); 37526e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (std::isnan(result)) return result; 37535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if ((a == 0.0) && (b == 0.0) && (copysign(1.0, a) != copysign(1.0, b))) { 37555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // a and b are zero, and the sign differs: return -0.0. 37565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return -0.0; 37575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 37585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return (a < b) ? a : b; 37595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 37605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 37615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 37645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPMinNM(T a, T b) { 37655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (IsQuietNaN(a) && !IsQuietNaN(b)) { 37665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl a = kFP64PositiveInfinity; 37675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (!IsQuietNaN(a) && IsQuietNaN(b)) { 37685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl b = kFP64PositiveInfinity; 37695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 37705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result = FPProcessNaNs(a, b); 37726e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return std::isnan(result) ? result : FPMin(a, b); 37735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 37745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 37775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPRecipStepFused(T op1, T op2) { 37785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const T two = 2.0; 37790f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if ((std::isinf(op1) && (op2 == 0.0)) || 37800f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl ((op1 == 0.0) && (std::isinf(op2)))) { 37815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return two; 37826e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isinf(op1) || std::isinf(op2)) { 37835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Return +inf if signs match, otherwise -inf. 37845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return ((op1 >= 0.0) == (op2 >= 0.0)) ? kFP64PositiveInfinity 37855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl : kFP64NegativeInfinity; 37865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 37875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FusedMultiplyAdd(op1, op2, two); 37885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 37895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 37905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 37935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPRSqrtStepFused(T op1, T op2) { 37945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const T one_point_five = 1.5; 37955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const T two = 2.0; 37965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 37970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if ((std::isinf(op1) && (op2 == 0.0)) || 37980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl ((op1 == 0.0) && (std::isinf(op2)))) { 37995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return one_point_five; 38006e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isinf(op1) || std::isinf(op2)) { 38015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Return +inf if signs match, otherwise -inf. 38025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return ((op1 >= 0.0) == (op2 >= 0.0)) ? kFP64PositiveInfinity 38035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl : kFP64NegativeInfinity; 38045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 38055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // The multiply-add-halve operation must be fully fused, so avoid interim 38065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // rounding by checking which operand can be losslessly divided by two 38075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // before doing the multiply-add. 38086e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (std::isnormal(op1 / two)) { 38095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FusedMultiplyAdd(op1 / two, op2, one_point_five); 38106e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnormal(op2 / two)) { 38115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FusedMultiplyAdd(op1, op2 / two, one_point_five); 38125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 38135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Neither operand is normal after halving: the result is dominated by 38145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // the addition term, so just return that. 38155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return one_point_five; 38165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 38195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 38205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 38215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixldouble Simulator::FPRoundInt(double value, FPRounding round_mode) { 38225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((value == 0.0) || (value == kFP64PositiveInfinity) || 38235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl (value == kFP64NegativeInfinity)) { 38245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return value; 38256e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isnan(value)) { 38265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPProcessNaN(value); 38275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 38296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl double int_result = std::floor(value); 38305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double error = value - int_result; 38315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (round_mode) { 38325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl case FPTieAway: { 38335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Take care of correctly handling the range ]-0.5, -0.0], which must 38345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // yield -0.0. 38355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((-0.5 < value) && (value < 0.0)) { 38365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int_result = -0.0; 38375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 38385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if ((error > 0.5) || ((error == 0.5) && (int_result >= 0.0))) { 38395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // If the error is greater than 0.5, or is equal to 0.5 and the integer 38405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // result is positive, round up. 38415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int_result++; 38425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl break; 38445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl case FPTieEven: { 38465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Take care of correctly handling the range [-0.5, -0.0], which must 38475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // yield -0.0. 38485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((-0.5 <= value) && (value < 0.0)) { 38495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int_result = -0.0; 38505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 38510f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // If the error is greater than 0.5, or is equal to 0.5 and the integer 38520f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // result is odd, round up. 38535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if ((error > 0.5) || 38540f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl ((error == 0.5) && (std::fmod(int_result, 2) != 0))) { 38555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int_result++; 38565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl break; 38585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl case FPZero: { 38605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // If value>0 then we take floor(value) 38615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // otherwise, ceil(value). 38625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (value < 0) { 38630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl int_result = ceil(value); 38645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl break; 38665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl case FPNegativeInfinity: { 38685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // We always use floor(value). 38695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl break; 38705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl case FPPositiveInfinity: { 38725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Take care of correctly handling the range ]-1.0, -0.0], which must 38735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // yield -0.0. 38745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if ((-1.0 < value) && (value < 0.0)) { 38755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int_result = -0.0; 38765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 38770f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl // If the error is non-zero, round up. 38785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (error > 0.0) { 38795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int_result++; 38805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl break; 38825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38830f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 38840f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNIMPLEMENTED(); 38855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return int_result; 38875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 38885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 38895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 38905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlint32_t Simulator::FPToInt32(double value, FPRounding rmode) { 38915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl value = FPRoundInt(value, rmode); 38925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (value >= kWMaxInt) { 38935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return kWMaxInt; 38945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (value < kWMinInt) { 38955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return kWMinInt; 38965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 38976e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return std::isnan(value) ? 0 : static_cast<int32_t>(value); 38985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 38995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlint64_t Simulator::FPToInt64(double value, FPRounding rmode) { 39025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl value = FPRoundInt(value, rmode); 39035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (value >= kXMaxInt) { 39045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return kXMaxInt; 39055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (value < kXMinInt) { 39065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return kXMinInt; 39075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 39086e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return std::isnan(value) ? 0 : static_cast<int64_t>(value); 39095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 39105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixluint32_t Simulator::FPToUInt32(double value, FPRounding rmode) { 39135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl value = FPRoundInt(value, rmode); 39145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (value >= kWMaxUInt) { 39155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return kWMaxUInt; 39165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (value < 0.0) { 39175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 0; 39185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 39196e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return std::isnan(value) ? 0 : static_cast<uint32_t>(value); 39205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 39215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixluint64_t Simulator::FPToUInt64(double value, FPRounding rmode) { 39245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl value = FPRoundInt(value, rmode); 39255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (value >= kXMaxUInt) { 39265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return kXMaxUInt; 39275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (value < 0.0) { 39285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 0; 39295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 39306e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl return std::isnan(value) ? 0 : static_cast<uint64_t>(value); 39315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 39325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl#define DEFINE_NEON_FP_VECTOR_OP(FN, OP, PROCNAN) \ 39350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl template <typename T> \ 39360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister Simulator::FN(VectorFormat vform, \ 39370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 39380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 39390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2) { \ 39400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.ClearForWrite(vform); \ 39410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { \ 39420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl T op1 = src1.Float<T>(i); \ 39430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl T op2 = src2.Float<T>(i); \ 39440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl T result; \ 39450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (PROCNAN) { \ 39460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = FPProcessNaNs(op1, op2); \ 39470f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (!std::isnan(result)) { \ 39480f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = OP(op1, op2); \ 39490f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } \ 39500f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } else { \ 39515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result = OP(op1, op2); \ 39525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } \ 39530f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetFloat(i, result); \ 39545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } \ 39550f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return dst; \ 39565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } \ 39575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl \ 39580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister Simulator::FN(VectorFormat vform, \ 39590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 39600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 39610f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2) { \ 39620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { \ 39630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl FN<float>(vform, dst, src1, src2); \ 39640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } else { \ 39650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); \ 39660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl FN<double>(vform, dst, src1, src2); \ 39670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } \ 39680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return dst; \ 39690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 39705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlNEON_FP3SAME_LIST(DEFINE_NEON_FP_VECTOR_OP) 39715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl#undef DEFINE_NEON_FP_VECTOR_OP 39725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fnmul(VectorFormat vform, 39755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 39765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 39775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 39785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 39795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister product = fmul(vform, temp, src1, src2); 39805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return fneg(vform, dst, product); 39815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 39825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 39855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::frecps(VectorFormat vform, 39865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 39875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 39885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 39895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 39905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 39915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op1 = -src1.Float<T>(i); 39925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op2 = src2.Float<T>(i); 39935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result = FPProcessNaNs(op1, op2); 39946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl dst.SetFloat(i, std::isnan(result) ? result : FPRecipStepFused(op1, op2)); 39955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 39965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 39975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 39985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 39995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 40005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::frecps(VectorFormat vform, 40015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 40025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 40035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 40045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 40055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl frecps<float>(vform, dst, src1, src2); 40065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 40075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 40085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl frecps<double>(vform, dst, src1, src2); 40095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 40105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 40115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 40125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 40135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 40145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 40155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::frsqrts(VectorFormat vform, 40165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 40175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 40185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 40195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 40205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 40215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op1 = -src1.Float<T>(i); 40225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op2 = src2.Float<T>(i); 40235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result = FPProcessNaNs(op1, op2); 40246e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl dst.SetFloat(i, std::isnan(result) ? result : FPRSqrtStepFused(op1, op2)); 40255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 40265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 40275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 40285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 40295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 40305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::frsqrts(VectorFormat vform, 40315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 40325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 40335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 40345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 40355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl frsqrts<float>(vform, dst, src1, src2); 40365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 40375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 40385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl frsqrts<double>(vform, dst, src1, src2); 40395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 40405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 40415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 40425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 40435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 40445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 40455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fcmp(VectorFormat vform, 40465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 40475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 40485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 40495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond) { 40505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 40515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 40525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool result = false; 40535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op1 = src1.Float<T>(i); 40545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op2 = src2.Float<T>(i); 40555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T nan_result = FPProcessNaNs(op1, op2); 40566e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (!std::isnan(nan_result)) { 40575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (cond) { 40580f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case eq: 40590f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = (op1 == op2); 40600f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 40610f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case ge: 40620f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = (op1 >= op2); 40630f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 40640f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case gt: 40650f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = (op1 > op2); 40660f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 40670f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case le: 40680f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = (op1 <= op2); 40690f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 40700f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case lt: 40710f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = (op1 < op2); 40720f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 40730f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 40740f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_UNREACHABLE(); 40750f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 40765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 40775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 40785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result ? MaxUintFromFormat(vform) : 0); 40795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 40805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 40815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 40825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 40835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 40845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fcmp(VectorFormat vform, 40855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 40865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 40875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 40885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond) { 40895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 40905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fcmp<float>(vform, dst, src1, src2, cond); 40915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 40925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 40935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fcmp<double>(vform, dst, src1, src2, cond); 40945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 40955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 40965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 40975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 40985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 40995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fcmp_zero(VectorFormat vform, 41005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 41015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 41025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond) { 41035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 41045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 410588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois LogicVRegister zero_reg = dup_immediate(vform, temp, FloatToRawbits(0.0)); 41065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fcmp<float>(vform, dst, src, zero_reg, cond); 41075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 41085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 410988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois LogicVRegister zero_reg = dup_immediate(vform, temp, DoubleToRawbits(0.0)); 41105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fcmp<double>(vform, dst, src, zero_reg, cond); 41115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 41125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 41135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 41145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 41155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 41165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fabscmp(VectorFormat vform, 41175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 41185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 41195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 41205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl Condition cond) { 41215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp1, temp2; 41225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 41235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister abs_src1 = fabs_<float>(vform, temp1, src1); 41245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister abs_src2 = fabs_<float>(vform, temp2, src2); 41255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fcmp<float>(vform, dst, abs_src1, abs_src2, cond); 41265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 41275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 41285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister abs_src1 = fabs_<double>(vform, temp1, src1); 41295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister abs_src2 = fabs_<double>(vform, temp2, src2); 41305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fcmp<double>(vform, dst, abs_src1, abs_src2, cond); 41315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 41325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 41335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 41345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 41355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 41365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 41375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fmla(VectorFormat vform, 41385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 41395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 41405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 41415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 41425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 41435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op1 = src1.Float<T>(i); 41445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op2 = src2.Float<T>(i); 41455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T acc = dst.Float<T>(i); 41465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result = FPMulAdd(acc, op1, op2); 41475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, result); 41485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 41495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 41505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 41515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 41525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 41535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fmla(VectorFormat vform, 41545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 41555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 41565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 41575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 41585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmla<float>(vform, dst, src1, src2); 41595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 41605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 41615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmla<double>(vform, dst, src1, src2); 41625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 41635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 41645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 41655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 41665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 41675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 41685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fmls(VectorFormat vform, 41695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 41705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 41715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 41725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 41735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 41745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op1 = -src1.Float<T>(i); 41755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op2 = src2.Float<T>(i); 41765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T acc = dst.Float<T>(i); 41775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result = FPMulAdd(acc, op1, op2); 41785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, result); 41795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 41805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 41815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 41825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 41835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 41845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fmls(VectorFormat vform, 41855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 41865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 41875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 41885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 41895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmls<float>(vform, dst, src1, src2); 41905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 41915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 41925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmls<double>(vform, dst, src1, src2); 41935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 41945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 41955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 41965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 41975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 41985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 41995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fneg(VectorFormat vform, 42005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 42015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 42025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 42035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 42045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op = src.Float<T>(i); 42055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl op = -op; 42065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, op); 42075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 42085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 42095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 42105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 42115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 42125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fneg(VectorFormat vform, 42135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 42145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 42155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 42165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fneg<float>(vform, dst, src); 42175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 42185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 42195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fneg<double>(vform, dst, src); 42205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 42215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 42225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 42235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 42245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 42255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 42265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fabs_(VectorFormat vform, 42275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 42285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 42295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 42305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 42315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op = src.Float<T>(i); 42325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (copysign(1.0, op) < 0.0) { 42335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl op = -op; 42345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 42355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, op); 42365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 42375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 42385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 42395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 42405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 42415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fabs_(VectorFormat vform, 42425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 42435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 42445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 42455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fabs_<float>(vform, dst, src); 42465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 42475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 42485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fabs_<double>(vform, dst, src); 42495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 42505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 42515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 42525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 42535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 42545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fabd(VectorFormat vform, 42555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 42565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 42575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2) { 42585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 42595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fsub(vform, temp, src1, src2); 42605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fabs_(vform, dst, temp); 42615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 42625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 42635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 42645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 42655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fsqrt(VectorFormat vform, 42665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 42675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 42685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 42695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 42705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 42715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float result = FPSqrt(src.Float<float>(i)); 42725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, result); 42735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 42745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 42755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 42765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 42775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double result = FPSqrt(src.Float<double>(i)); 42785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, result); 42795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 42805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 42815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 42825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 42835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 42845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 42850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl#define DEFINE_NEON_FP_PAIR_OP(FNP, FN, OP) \ 42860f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister Simulator::FNP(VectorFormat vform, \ 42870f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 42880f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src1, \ 42890f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src2) { \ 42900f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl SimVRegister temp1, temp2; \ 42910f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uzp1(vform, temp1, src1, src2); \ 42920f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl uzp2(vform, temp2, src1, src2); \ 42930f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl FN(vform, dst, temp1, temp2); \ 42940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return dst; \ 42950f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } \ 42960f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl \ 42970f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister Simulator::FNP(VectorFormat vform, \ 42980f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, \ 42990f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src) { \ 43000f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl if (vform == kFormatS) { \ 43010f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl float result = OP(src.Float<float>(0), src.Float<float>(1)); \ 43020f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetFloat(0, result); \ 43030f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } else { \ 43040f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl VIXL_ASSERT(vform == kFormatD); \ 43050f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl double result = OP(src.Float<double>(0), src.Float<double>(1)); \ 43060f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.SetFloat(0, result); \ 43070f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } \ 43080f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl dst.ClearForWrite(vform); \ 43090f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl return dst; \ 43100f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } 43115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlNEON_FPPAIRWISE_LIST(DEFINE_NEON_FP_PAIR_OP) 43125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl#undef DEFINE_NEON_FP_PAIR_OP 43135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fminmaxv(VectorFormat vform, 43165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 43175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 43185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPMinMaxOp Op) { 43195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(vform == kFormat4S); 43205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl USE(vform); 43215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float result1 = (this->*Op)(src.Float<float>(0), src.Float<float>(1)); 43225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float result2 = (this->*Op)(src.Float<float>(2), src.Float<float>(3)); 43235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float result = (this->*Op)(result1, result2); 43245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(kFormatS); 43255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat<float>(0, result); 43265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 43275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 43285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fmaxv(VectorFormat vform, 43315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 43325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 43335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return fminmaxv(vform, dst, src, &Simulator::FPMax); 43345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 43355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fminv(VectorFormat vform, 43385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 43395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 43405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return fminmaxv(vform, dst, src, &Simulator::FPMin); 43415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 43425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fmaxnmv(VectorFormat vform, 43450f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl LogicVRegister dst, 43460f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl const LogicVRegister& src) { 43475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return fminmaxv(vform, dst, src, &Simulator::FPMaxNM); 43485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 43495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fminnmv(VectorFormat vform, 43525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 43535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 43545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return fminmaxv(vform, dst, src, &Simulator::FPMinNM); 43555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 43565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fmul(VectorFormat vform, 43595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 43605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 43615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 43625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 43635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 43645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 43655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 43665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); 43675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmul<float>(vform, dst, src1, index_reg); 43685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 43705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 43715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); 43725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmul<double>(vform, dst, src1, index_reg); 43735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 43745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 43755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 43765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fmla(VectorFormat vform, 43795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 43805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 43815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 43825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 43835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 43845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 43855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 43865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); 43875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmla<float>(vform, dst, src1, index_reg); 43885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 43905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 43915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); 43925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmla<double>(vform, dst, src1, index_reg); 43935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 43945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 43955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 43965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 43985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fmls(VectorFormat vform, 43995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 44005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 44015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 44025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 44035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 44045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 44055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 44065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); 44075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmls<float>(vform, dst, src1, index_reg); 44085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 44095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 44105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 44115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); 44125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmls<double>(vform, dst, src1, index_reg); 44135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 44145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 44155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 44165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 44175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 44185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fmulx(VectorFormat vform, 44195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 44205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src1, 44215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src2, 44225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int index) { 44235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 44245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl SimVRegister temp; 44255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 44265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index); 44275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmulx<float>(vform, dst, src1, index_reg); 44285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 44295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 44305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 44315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index); 44325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fmulx<double>(vform, dst, src1, index_reg); 44335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 44345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 44355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 44365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 44375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 44385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::frint(VectorFormat vform, 44395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 44405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 44415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode, 44425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool inexact_exception) { 44435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 44445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 44455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 44465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float input = src.Float<float>(i); 44475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float rounded = FPRoundInt(input, rounding_mode); 44486e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (inexact_exception && !std::isnan(input) && (input != rounded)) { 44495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPProcessException(); 44505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 44515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat<float>(i, rounded); 44525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 44535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 44545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 44555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 44565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double input = src.Float<double>(i); 44575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double rounded = FPRoundInt(input, rounding_mode); 44586e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (inexact_exception && !std::isnan(input) && (input != rounded)) { 44595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPProcessException(); 44605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 44615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat<double>(i, rounded); 44625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 44635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 44645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 44655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 44665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 44675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 44685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fcvts(VectorFormat vform, 44695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 44705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 44715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode, 44725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits) { 44735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 44745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 44755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 44766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl float op = src.Float<float>(i) * std::pow(2.0f, fbits); 44775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, FPToInt32(op, rounding_mode)); 44785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 44795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 44805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 44815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 44826e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl double op = src.Float<double>(i) * std::pow(2.0, fbits); 44835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetInt(vform, i, FPToInt64(op, rounding_mode)); 44845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 44855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 44865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 44875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 44885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 44895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 44905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fcvtu(VectorFormat vform, 44915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 44925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 44935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding rounding_mode, 44945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits) { 44955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 44965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 44975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 44986e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl float op = src.Float<float>(i) * std::pow(2.0f, fbits); 44995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, FPToUInt32(op, rounding_mode)); 45005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 45025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 45035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 45046e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl double op = src.Float<double>(i) * std::pow(2.0, fbits); 45055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, FPToUInt64(op, rounding_mode)); 45065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 45095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 45105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 45115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 45125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fcvtl(VectorFormat vform, 45135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 45145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 45155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 45165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = LaneCountFromFormat(vform) - 1; i >= 0; i--) { 45175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, FPToFloat(src.Float<float16>(i))); 45185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 45205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 45215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = LaneCountFromFormat(vform) - 1; i >= 0; i--) { 45225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, FPToDouble(src.Float<float>(i))); 45235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 45265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 45275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 45285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 45295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fcvtl2(VectorFormat vform, 45305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 45315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 45325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int lane_count = LaneCountFromFormat(vform); 45335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 45345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < lane_count; i++) { 45355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, FPToFloat(src.Float<float16>(i + lane_count))); 45365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 45385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 45395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < lane_count; i++) { 45405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, FPToDouble(src.Float<float>(i + lane_count))); 45415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 45445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 45455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 45465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 45475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fcvtn(VectorFormat vform, 45485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 45495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 45505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { 45515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 45525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, FPToFloat16(src.Float<float>(i), FPTieEven)); 45535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 45555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kSRegSize); 45565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 45575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, FPToFloat(src.Float<double>(i), FPTieEven)); 45585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 45615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 45625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 45635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 45645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fcvtn2(VectorFormat vform, 45655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 45665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 45675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int lane_count = LaneCountFromFormat(vform) / 2; 45685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kHRegSize) { 45695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = lane_count - 1; i >= 0; i--) { 45705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i + lane_count, FPToFloat16(src.Float<float>(i), FPTieEven)); 45715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 45735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kSRegSize); 45745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = lane_count - 1; i >= 0; i--) { 45755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i + lane_count, FPToFloat(src.Float<double>(i), FPTieEven)); 45765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 45795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 45805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 45815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 45825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fcvtxn(VectorFormat vform, 45835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 45845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 45855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 45865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kSRegSize); 45875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 45885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, FPToFloat(src.Float<double>(i), FPRoundOdd)); 45895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 45905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 45915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 45925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 45935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 45945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::fcvtxn2(VectorFormat vform, 45955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 45965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 45975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kSRegSize); 45985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int lane_count = LaneCountFromFormat(vform) / 2; 45995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = lane_count - 1; i >= 0; i--) { 46005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i + lane_count, FPToFloat(src.Float<double>(i), FPRoundOdd)); 46015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 46025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 46035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 46045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Based on reference C function recip_sqrt_estimate from ARM ARM. 46075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixldouble Simulator::recip_sqrt_estimate(double a) { 46085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int q0, q1, s; 46095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double r; 46105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (a < 0.5) { 46115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl q0 = static_cast<int>(a * 512.0); 46125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl r = 1.0 / sqrt((static_cast<double>(q0) + 0.5) / 512.0); 46130f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl } else { 46145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl q1 = static_cast<int>(a * 256.0); 46155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl r = 1.0 / sqrt((static_cast<double>(q1) + 0.5) / 256.0); 46165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 46175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl s = static_cast<int>(256.0 * r + 0.5); 46185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return static_cast<double>(s) / 256.0; 46195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 46205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlstatic inline uint64_t Bits(uint64_t val, int start_bit, int end_bit) { 462388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return ExtractUnsignedBitfield64(start_bit, end_bit, val); 46245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 46255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 46285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPRecipSqrtEstimate(T op) { 46296e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (std::isnan(op)) { 46305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPProcessNaN(op); 46315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (op == 0.0) { 46325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (copysign(1.0, op) < 0.0) { 46335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return kFP64NegativeInfinity; 46345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 46355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return kFP64PositiveInfinity; 46365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 46375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (copysign(1.0, op) < 0.0) { 46385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPProcessException(); 46395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPDefaultNaN<T>(); 46406e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isinf(op)) { 46415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return 0.0; 46425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 46435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t fraction; 46445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int exp, result_exp; 46455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sizeof(T) == sizeof(float)) { // NOLINT(runtime/sizeof) 464788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois exp = FloatExp(op); 464888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois fraction = FloatMantissa(op); 46495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fraction <<= 29; 46505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 465188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois exp = DoubleExp(op); 465288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois fraction = DoubleMantissa(op); 46535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 46545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (exp == 0) { 46565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl while (Bits(fraction, 51, 51) == 0) { 46575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fraction = Bits(fraction, 50, 0) << 1; 46585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl exp -= 1; 46595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 46605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fraction = Bits(fraction, 50, 0) << 1; 46615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 46625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double scaled; 46645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (Bits(exp, 0, 0) == 0) { 466588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois scaled = DoublePack(0, 1022, Bits(fraction, 51, 44) << 44); 46665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 466788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois scaled = DoublePack(0, 1021, Bits(fraction, 51, 44) << 44); 46685289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 46695289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sizeof(T) == sizeof(float)) { // NOLINT(runtime/sizeof) 46715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result_exp = (380 - exp) / 2; 46725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 46735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result_exp = (3068 - exp) / 2; 46745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 46755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 467688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois uint64_t estimate = DoubleToRawbits(recip_sqrt_estimate(scaled)); 46775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sizeof(T) == sizeof(float)) { // NOLINT(runtime/sizeof) 4679db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint32_t exp_bits = static_cast<uint32_t>(Bits(result_exp, 7, 0)); 4680db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint32_t est_bits = static_cast<uint32_t>(Bits(estimate, 51, 29)); 468188c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return FloatPack(0, exp_bits, est_bits); 46825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 468388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return DoublePack(0, Bits(result_exp, 10, 0), Bits(estimate, 51, 0)); 46845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 46855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 46865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 46875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 46895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::frsqrte(VectorFormat vform, 46905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 46915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 46925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 46935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 46945289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 46955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float input = src.Float<float>(i); 46965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, FPRecipSqrtEstimate<float>(input)); 46975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 46985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 46995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 47005289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 47015289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double input = src.Float<double>(i); 47025289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, FPRecipSqrtEstimate<double>(input)); 47035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 47045289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 47055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 47065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 47075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 47085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 47095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlT Simulator::FPRecipEstimate(T op, FPRounding rounding) { 47105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t sign; 47115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 47125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sizeof(T) == sizeof(float)) { // NOLINT(runtime/sizeof) 471388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois sign = FloatSign(op); 47145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 471588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois sign = DoubleSign(op); 47165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 47175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 47186e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (std::isnan(op)) { 47195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return FPProcessNaN(op); 47206e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl } else if (std::isinf(op)) { 47215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return (sign == 1) ? -0.0 : 0.0; 47225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (op == 0.0) { 47235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPProcessException(); // FPExc_DivideByZero exception. 47245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return (sign == 1) ? kFP64NegativeInfinity : kFP64PositiveInfinity; 47255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (((sizeof(T) == sizeof(float)) && // NOLINT(runtime/sizeof) 47266e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl (std::fabs(op) < std::pow(2.0, -128.0))) || 47275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl ((sizeof(T) == sizeof(double)) && // NOLINT(runtime/sizeof) 47286e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl (std::fabs(op) < std::pow(2.0, -1024.0)))) { 47295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl bool overflow_to_inf = false; 47305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl switch (rounding) { 47310f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case FPTieEven: 47320f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl overflow_to_inf = true; 47330f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 47340f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case FPPositiveInfinity: 47350f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl overflow_to_inf = (sign == 0); 47360f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 47370f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case FPNegativeInfinity: 47380f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl overflow_to_inf = (sign == 1); 47390f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 47400f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl case FPZero: 47410f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl overflow_to_inf = false; 47420f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 47430f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl default: 47440f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl break; 47455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 47465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPProcessException(); // FPExc_Overflow and FPExc_Inexact. 47475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (overflow_to_inf) { 47485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return (sign == 1) ? kFP64NegativeInfinity : kFP64PositiveInfinity; 47495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 47505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl // Return FPMaxNormal(sign). 47515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sizeof(T) == sizeof(float)) { // NOLINT(runtime/sizeof) 475288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return FloatPack(sign, 0xfe, 0x07fffff); 47535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 475488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return DoublePack(sign, 0x7fe, 0x0fffffffffffffl); 47555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 47565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 47575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 47585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint64_t fraction; 47595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int exp, result_exp; 47605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t sign; 47615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 47625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sizeof(T) == sizeof(float)) { // NOLINT(runtime/sizeof) 476388c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois sign = FloatSign(op); 476488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois exp = FloatExp(op); 476588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois fraction = FloatMantissa(op); 47665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fraction <<= 29; 47675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 476888c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois sign = DoubleSign(op); 476988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois exp = DoubleExp(op); 477088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois fraction = DoubleMantissa(op); 47715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 47725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 47735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (exp == 0) { 47745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (Bits(fraction, 51, 51) == 0) { 47755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl exp -= 1; 47765289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fraction = Bits(fraction, 49, 0) << 2; 47775289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 47785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl fraction = Bits(fraction, 50, 0) << 1; 47795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 47805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 47815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 478288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois double scaled = DoublePack(0, 1022, Bits(fraction, 51, 44) << 44); 47835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 47845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sizeof(T) == sizeof(float)) { // NOLINT(runtime/sizeof) 47850f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result_exp = (253 - exp); // In range 253-254 = -1 to 253+1 = 254. 47865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 47875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result_exp = (2045 - exp); // In range 2045-2046 = -1 to 2045+1 = 2046. 47885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 47895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 47905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double estimate = recip_estimate(scaled); 47915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 479288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois fraction = DoubleMantissa(estimate); 47935289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (result_exp == 0) { 47946e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl fraction = (UINT64_C(1) << 51) | Bits(fraction, 51, 1); 47955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else if (result_exp == -1) { 47966e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl fraction = (UINT64_C(1) << 50) | Bits(fraction, 51, 2); 47975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result_exp = 0; 47985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 47995289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sizeof(T) == sizeof(float)) { // NOLINT(runtime/sizeof) 4800db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint32_t exp_bits = static_cast<uint32_t>(Bits(result_exp, 7, 0)); 4801db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint32_t frac_bits = static_cast<uint32_t>(Bits(fraction, 51, 29)); 480288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return FloatPack(sign, exp_bits, frac_bits); 48035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 480488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois return DoublePack(sign, Bits(result_exp, 10, 0), Bits(fraction, 51, 0)); 48055289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 48065289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 48075289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 48085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 48095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 48105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::frecpe(VectorFormat vform, 48115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 48125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 48135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding round) { 48145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 48155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 48165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 48175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float input = src.Float<float>(i); 48185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, FPRecipEstimate<float>(input, round)); 48195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 48205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 48215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 48225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 48235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double input = src.Float<double>(i); 48245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, FPRecipEstimate<double>(input, round)); 48255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 48265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 48275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 48285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 48295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 48305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 48315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ursqrte(VectorFormat vform, 48325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 48335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 48345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 4835db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint64_t operand; 4836db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint32_t result; 48375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double dp_operand, dp_result; 48385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 48395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl operand = src.Uint(vform, i); 48405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (operand <= 0x3FFFFFFF) { 48415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result = 0xFFFFFFFF; 48425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 48436e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl dp_operand = operand * std::pow(2.0, -32); 48446e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl dp_result = recip_sqrt_estimate(dp_operand) * std::pow(2.0, 31); 48455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result = static_cast<uint32_t>(dp_result); 48465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 48475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result); 48485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 48495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 48505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 48515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 48525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 48535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl// Based on reference C function recip_estimate from ARM ARM. 48545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixldouble Simulator::recip_estimate(double a) { 48555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int q, s; 48565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double r; 48575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl q = static_cast<int>(a * 512.0); 48585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl r = 1.0 / ((static_cast<double>(q) + 0.5) / 512.0); 48595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl s = static_cast<int>(256.0 * r + 0.5); 48605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return static_cast<double>(s) / 256.0; 48615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 48625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 48635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 48645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::urecpe(VectorFormat vform, 48655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 48665289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 48675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 4868db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint64_t operand; 4869db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl uint32_t result; 48705289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double dp_operand, dp_result; 48715289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 48725289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl operand = src.Uint(vform, i); 48735289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (operand <= 0x7FFFFFFF) { 48745289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result = 0xFFFFFFFF; 48755289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 48766e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl dp_operand = operand * std::pow(2.0, -32); 48776e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl dp_result = recip_estimate(dp_operand) * std::pow(2.0, 31); 48785289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl result = static_cast<uint32_t>(dp_result); 48795289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 48805289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetUint(vform, i, result); 48815289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 48825289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 48835289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 48845289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 48855289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixltemplate <typename T> 48865289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::frecpx(VectorFormat vform, 48875289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 48885289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 48895289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.ClearForWrite(vform); 48905289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 48915289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T op = src.Float<T>(i); 48925289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl T result; 48936e2c8275d5f34a531fe1eef7a7aa877601be8558armvixl if (std::isnan(op)) { 48940f35e36b7f5d1d2f4d95989b418447e1a4bcc8cdarmvixl result = FPProcessNaN(op); 48955289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 48965289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int exp; 48975289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl uint32_t sign; 48985289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (sizeof(T) == sizeof(float)) { // NOLINT(runtime/sizeof) 489988c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois sign = FloatSign(op); 490088c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois exp = FloatExp(op); 4901db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl exp = (exp == 0) ? (0xFF - 1) : static_cast<int>(Bits(~exp, 7, 0)); 490288c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois result = FloatPack(sign, exp, 0); 49035289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 490488c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois sign = DoubleSign(op); 490588c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois exp = DoubleExp(op); 4906db6443499376478f5281607a3923e6ffc4c8d8ecarmvixl exp = (exp == 0) ? (0x7FF - 1) : static_cast<int>(Bits(~exp, 10, 0)); 490788c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois result = DoublePack(sign, exp, 0); 49085289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 49095289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 49105289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat(i, result); 49115289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 49125289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 49135289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 49145289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 49155289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 49165289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::frecpx(VectorFormat vform, 49175289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 49185289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src) { 49195289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 49205289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl frecpx<float>(vform, dst, src); 49215289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 49225289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 49235289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl frecpx<double>(vform, dst, src); 49245289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 49255289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 49265289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 49275289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 49285289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::scvtf(VectorFormat vform, 49295289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 49305289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 49315289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits, 49325289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding round) { 49335289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 49345289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 49355289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float result = FixedToFloat(src.Int(kFormatS, i), fbits, round); 49365289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat<float>(i, result); 49375289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 49385289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 49395289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double result = FixedToDouble(src.Int(kFormatD, i), fbits, round); 49405289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat<double>(i, result); 49415289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 49425289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 49435289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 49445289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 49455289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 49465289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 49475289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixlLogicVRegister Simulator::ucvtf(VectorFormat vform, 49485289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl LogicVRegister dst, 49495289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl const LogicVRegister& src, 49505289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl int fbits, 49515289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl FPRounding round) { 49525289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl for (int i = 0; i < LaneCountFromFormat(vform); i++) { 49535289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl if (LaneSizeInBitsFromFormat(vform) == kSRegSize) { 49545289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl float result = UFixedToFloat(src.Uint(kFormatS, i), fbits, round); 49555289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat<float>(i, result); 49565289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } else { 49575289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize); 49585289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl double result = UFixedToDouble(src.Uint(kFormatD, i), fbits, round); 49595289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl dst.SetFloat<double>(i, result); 49605289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 49615289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl } 49625289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl return dst; 49635289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} 49645289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 49655289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl 496688c46b84df005638546de5e4e965bdcc31352f48Pierre Langlois} // namespace aarch64 49675289c5900fb214f2f6aa61e2a9263730dcf4cc17armvixl} // namespace vixl 4968684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl 4969684cd2a7f5845539b58d0da7e012e39df49ceff0armvixl#endif // VIXL_INCLUDE_SIMULATOR 4970