1#ifndef __UAPI_MSMB_ISP__
2#define __UAPI_MSMB_ISP__
3
4#include <linux/videodev2.h>
5#include <media/msmb_camera.h>
6
7#define MAX_PLANES_PER_STREAM 3
8#define MAX_NUM_STREAM 7
9
10#define ISP_VERSION_48        48
11#define ISP_VERSION_47        47
12#define ISP_VERSION_46        46
13#define ISP_VERSION_44        44
14#define ISP_VERSION_40        40
15#define ISP_VERSION_32        32
16#define ISP_NATIVE_BUF_BIT    (0x10000 << 0)
17#define ISP0_BIT              (0x10000 << 1)
18#define ISP1_BIT              (0x10000 << 2)
19#define ISP_META_CHANNEL_BIT  (0x10000 << 3)
20#define ISP_SCRATCH_BUF_BIT   (0x10000 << 4)
21#define ISP_OFFLINE_STATS_BIT (0x10000 << 5)
22#define ISP_SVHDR_IN_BIT      (0x10000 << 6) /* RDI hw stream for SVHDR */
23#define ISP_SVHDR_OUT_BIT     (0x10000 << 7) /* SVHDR output bufq stream*/
24
25#define ISP_STATS_STREAM_BIT  0x80000000
26
27#define VFE_HW_LIMIT 1
28
29struct msm_vfe_cfg_cmd_list;
30
31enum ISP_START_PIXEL_PATTERN {
32	ISP_BAYER_RGRGRG,
33	ISP_BAYER_GRGRGR,
34	ISP_BAYER_BGBGBG,
35	ISP_BAYER_GBGBGB,
36	ISP_YUV_YCbYCr,
37	ISP_YUV_YCrYCb,
38	ISP_YUV_CbYCrY,
39	ISP_YUV_CrYCbY,
40	ISP_PIX_PATTERN_MAX
41};
42
43enum msm_vfe_plane_fmt {
44	Y_PLANE,
45	CB_PLANE,
46	CR_PLANE,
47	CRCB_PLANE,
48	CBCR_PLANE,
49	VFE_PLANE_FMT_MAX
50};
51
52enum msm_vfe_input_src {
53	VFE_PIX_0,
54	VFE_RAW_0,
55	VFE_RAW_1,
56	VFE_RAW_2,
57	VFE_SRC_MAX,
58};
59
60enum msm_vfe_axi_stream_src {
61	PIX_ENCODER,
62	PIX_VIEWFINDER,
63	PIX_VIDEO,
64	CAMIF_RAW,
65	IDEAL_RAW,
66	RDI_INTF_0,
67	RDI_INTF_1,
68	RDI_INTF_2,
69	VFE_AXI_SRC_MAX
70};
71
72enum msm_vfe_frame_skip_pattern {
73	NO_SKIP,
74	EVERY_2FRAME,
75	EVERY_3FRAME,
76	EVERY_4FRAME,
77	EVERY_5FRAME,
78	EVERY_6FRAME,
79	EVERY_7FRAME,
80	EVERY_8FRAME,
81	EVERY_16FRAME,
82	EVERY_32FRAME,
83	SKIP_ALL,
84	SKIP_RANGE,
85	MAX_SKIP,
86};
87
88/*
89 * Define an unused period. When this period is set it means that the stream is
90 * stopped(i.e the pattern is 0). We don't track the current pattern, just the
91 * period defines what the pattern is, if period is this then pattern is 0 else
92 * pattern is 1
93 */
94#define MSM_VFE_STREAM_STOP_PERIOD 15
95
96enum msm_isp_stats_type {
97	MSM_ISP_STATS_AEC,   /* legacy based AEC */
98	MSM_ISP_STATS_AF,    /* legacy based AF */
99	MSM_ISP_STATS_AWB,   /* legacy based AWB */
100	MSM_ISP_STATS_RS,    /* legacy based RS */
101	MSM_ISP_STATS_CS,    /* legacy based CS */
102	MSM_ISP_STATS_IHIST, /* legacy based HIST */
103	MSM_ISP_STATS_SKIN,  /* legacy based SKIN */
104	MSM_ISP_STATS_BG,    /* Bayer Grids */
105	MSM_ISP_STATS_BF,    /* Bayer Focus */
106	MSM_ISP_STATS_BE,    /* Bayer Exposure*/
107	MSM_ISP_STATS_BHIST, /* Bayer Hist */
108	MSM_ISP_STATS_BF_SCALE,  /* Bayer Focus scale */
109	MSM_ISP_STATS_HDR_BE,    /* HDR Bayer Exposure */
110	MSM_ISP_STATS_HDR_BHIST, /* HDR Bayer Hist */
111	MSM_ISP_STATS_AEC_BG,   /* AEC BG */
112	MSM_ISP_STATS_MAX    /* MAX */
113};
114
115/*
116 * @stats_type_mask: Stats type mask (enum msm_isp_stats_type).
117 * @stream_src_mask: Stream src mask (enum msm_vfe_axi_stream_src)
118 * @skip_mode: skip pattern, if skip mode is range only then min/max is used
119 * @min_frame_id: minimum frame id (valid only if skip_mode = RANGE)
120 * @max_frame_id: maximum frame id (valid only if skip_mode = RANGE)
121*/
122struct msm_isp_sw_framskip {
123	uint32_t stats_type_mask;
124	uint32_t stream_src_mask;
125	enum msm_vfe_frame_skip_pattern skip_mode;
126	uint32_t min_frame_id;
127	uint32_t max_frame_id;
128};
129
130enum msm_vfe_testgen_color_pattern {
131	COLOR_BAR_8_COLOR,
132	UNICOLOR_WHITE,
133	UNICOLOR_YELLOW,
134	UNICOLOR_CYAN,
135	UNICOLOR_GREEN,
136	UNICOLOR_MAGENTA,
137	UNICOLOR_RED,
138	UNICOLOR_BLUE,
139	UNICOLOR_BLACK,
140	MAX_COLOR,
141};
142
143enum msm_vfe_camif_input {
144	CAMIF_DISABLED,
145	CAMIF_PAD_REG_INPUT,
146	CAMIF_MIDDI_INPUT,
147	CAMIF_MIPI_INPUT,
148};
149
150struct msm_vfe_fetch_engine_cfg {
151	uint32_t input_format;
152	uint32_t buf_width;
153	uint32_t buf_height;
154	uint32_t fetch_width;
155	uint32_t fetch_height;
156	uint32_t x_offset;
157	uint32_t y_offset;
158	uint32_t buf_stride;
159};
160
161enum msm_vfe_camif_output_format {
162	CAMIF_QCOM_RAW,
163	CAMIF_MIPI_RAW,
164	CAMIF_PLAIN_8,
165	CAMIF_PLAIN_16,
166	CAMIF_MAX_FORMAT,
167};
168
169/*
170 * Camif output general configuration
171 */
172struct msm_vfe_camif_subsample_cfg {
173	uint32_t irq_subsample_period;
174	uint32_t irq_subsample_pattern;
175	uint32_t sof_counter_step;
176	uint32_t pixel_skip;
177	uint32_t line_skip;
178	uint32_t first_line;
179	uint32_t last_line;
180	uint32_t first_pixel;
181	uint32_t last_pixel;
182	enum msm_vfe_camif_output_format output_format;
183};
184
185/*
186 * Camif frame and window configuration
187 */
188struct msm_vfe_camif_cfg {
189	uint32_t lines_per_frame;
190	uint32_t pixels_per_line;
191	uint32_t first_pixel;
192	uint32_t last_pixel;
193	uint32_t first_line;
194	uint32_t last_line;
195	uint32_t epoch_line0;
196	uint32_t epoch_line1;
197	uint32_t is_split;
198	enum msm_vfe_camif_input camif_input;
199	struct msm_vfe_camif_subsample_cfg subsample_cfg;
200};
201
202struct msm_vfe_testgen_cfg {
203	uint32_t lines_per_frame;
204	uint32_t pixels_per_line;
205	uint32_t v_blank;
206	uint32_t h_blank;
207	enum ISP_START_PIXEL_PATTERN pixel_bayer_pattern;
208	uint32_t rotate_period;
209	enum msm_vfe_testgen_color_pattern color_bar_pattern;
210	uint32_t burst_num_frame;
211};
212
213enum msm_vfe_inputmux {
214	CAMIF,
215	TESTGEN,
216	EXTERNAL_READ,
217};
218
219enum msm_vfe_stats_composite_group {
220	STATS_COMPOSITE_GRP_NONE,
221	STATS_COMPOSITE_GRP_1,
222	STATS_COMPOSITE_GRP_2,
223	STATS_COMPOSITE_GRP_MAX,
224};
225
226enum msm_vfe_hvx_streaming_cmd {
227	HVX_DISABLE,
228	HVX_ONE_WAY,
229	HVX_ROUND_TRIP
230};
231
232struct msm_vfe_pix_cfg {
233	struct msm_vfe_camif_cfg camif_cfg;
234	struct msm_vfe_testgen_cfg testgen_cfg;
235	struct msm_vfe_fetch_engine_cfg fetch_engine_cfg;
236	enum msm_vfe_inputmux input_mux;
237	enum ISP_START_PIXEL_PATTERN pixel_pattern;
238	uint32_t input_format;
239	enum msm_vfe_hvx_streaming_cmd hvx_cmd;
240	uint32_t is_split;
241};
242
243struct msm_vfe_rdi_cfg {
244	uint8_t cid;
245	uint8_t frame_based;
246};
247
248struct msm_vfe_input_cfg {
249	union {
250		struct msm_vfe_pix_cfg pix_cfg;
251		struct msm_vfe_rdi_cfg rdi_cfg;
252	} d;
253	enum msm_vfe_input_src input_src;
254	uint32_t input_pix_clk;
255};
256
257struct msm_vfe_fetch_eng_start {
258	uint32_t session_id;
259	uint32_t stream_id;
260	uint32_t buf_idx;
261	uint8_t  offline_mode;
262	uint32_t fd;
263	uint32_t buf_addr;
264	uint32_t frame_id;
265};
266
267enum msm_vfe_fetch_eng_pass {
268	OFFLINE_FIRST_PASS,
269	OFFLINE_SECOND_PASS,
270	OFFLINE_MAX_PASS,
271};
272
273struct msm_vfe_fetch_eng_multi_pass_start {
274	uint32_t session_id;
275	uint32_t stream_id;
276	uint32_t buf_idx;
277	uint8_t  offline_mode;
278	uint32_t fd;
279	uint32_t buf_addr;
280	uint32_t frame_id;
281	uint32_t output_buf_idx;
282	uint32_t input_buf_offset;
283	enum msm_vfe_fetch_eng_pass  offline_pass;
284	uint32_t output_stream_id;
285};
286
287struct msm_vfe_axi_plane_cfg {
288	uint32_t output_width; /*Include padding*/
289	uint32_t output_height;
290	uint32_t output_stride;
291	uint32_t output_scan_lines;
292	uint32_t output_plane_format; /*Y/Cb/Cr/CbCr*/
293	uint32_t plane_addr_offset;
294	uint8_t csid_src; /*RDI 0-2*/
295	uint8_t rdi_cid;/*CID 1-16*/
296};
297
298enum msm_stream_rdi_input_type {
299	MSM_CAMERA_RDI_MIN,
300	MSM_CAMERA_RDI_PDAF,
301	MSM_CAMERA_RDI_MAX,
302};
303
304struct msm_vfe_axi_stream_request_cmd {
305	uint32_t session_id;
306	uint32_t stream_id;
307	uint32_t vt_enable;
308	uint32_t output_format;/*Planar/RAW/Misc*/
309	enum msm_vfe_axi_stream_src stream_src; /*CAMIF/IDEAL/RDIs*/
310	struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
311
312	uint32_t burst_count;
313	uint32_t hfr_mode;
314	uint8_t frame_base;
315
316	uint32_t init_frame_drop; /*MAX 31 Frames*/
317	enum msm_vfe_frame_skip_pattern frame_skip_pattern;
318	uint8_t buf_divert; /* if TRUE no vb2 buf done. */
319	/*Return values*/
320	uint32_t axi_stream_handle;
321	uint32_t controllable_output;
322	uint32_t burst_len;
323	/* Flag indicating memory input stream */
324	enum msm_stream_rdi_input_type rdi_input_type;
325};
326
327struct msm_vfe_axi_stream_release_cmd {
328	uint32_t stream_handle;
329};
330
331enum msm_vfe_axi_stream_cmd {
332	STOP_STREAM,
333	START_STREAM,
334	STOP_IMMEDIATELY,
335};
336
337struct msm_vfe_axi_stream_cfg_cmd {
338	uint8_t num_streams;
339	uint32_t stream_handle[VFE_AXI_SRC_MAX];
340	enum msm_vfe_axi_stream_cmd cmd;
341	uint8_t sync_frame_id_src;
342};
343
344enum msm_vfe_axi_stream_update_type {
345	ENABLE_STREAM_BUF_DIVERT,
346	DISABLE_STREAM_BUF_DIVERT,
347	UPDATE_STREAM_FRAMEDROP_PATTERN,
348	UPDATE_STREAM_STATS_FRAMEDROP_PATTERN,
349	UPDATE_STREAM_AXI_CONFIG,
350	UPDATE_STREAM_REQUEST_FRAMES,
351	UPDATE_STREAM_ADD_BUFQ,
352	UPDATE_STREAM_REMOVE_BUFQ,
353	UPDATE_STREAM_SW_FRAME_DROP,
354	UPDATE_STREAM_REQUEST_FRAMES_VER2,
355	UPDATE_STREAM_OFFLINE_AXI_CONFIG,
356};
357#define UPDATE_STREAM_REQUEST_FRAMES_VER2 UPDATE_STREAM_REQUEST_FRAMES_VER2
358
359enum msm_vfe_iommu_type {
360	IOMMU_ATTACH,
361	IOMMU_DETACH,
362};
363
364enum msm_vfe_buff_queue_id {
365	VFE_BUF_QUEUE_DEFAULT,
366	VFE_BUF_QUEUE_SHARED,
367	VFE_BUF_QUEUE_MAX,
368};
369
370struct msm_vfe_axi_stream_cfg_update_info {
371	uint32_t stream_handle;
372	uint32_t output_format;
373	uint32_t user_stream_id;
374	uint32_t frame_id;
375	enum msm_vfe_frame_skip_pattern skip_pattern;
376	struct msm_vfe_axi_plane_cfg plane_cfg[MAX_PLANES_PER_STREAM];
377	struct msm_isp_sw_framskip sw_skip_info;
378};
379
380struct msm_vfe_axi_stream_cfg_update_info_req_frm {
381	uint32_t stream_handle;
382	uint32_t user_stream_id;
383	uint32_t frame_id;
384	uint32_t buf_index;
385};
386
387struct msm_vfe_axi_halt_cmd {
388	uint32_t stop_camif;
389	uint32_t overflow_detected;
390	uint32_t blocking_halt;
391};
392
393struct msm_vfe_axi_reset_cmd {
394	uint32_t blocking;
395	uint32_t frame_id;
396};
397
398struct msm_vfe_axi_restart_cmd {
399	uint32_t enable_camif;
400};
401
402struct msm_vfe_axi_stream_update_cmd {
403	uint32_t num_streams;
404	enum msm_vfe_axi_stream_update_type update_type;
405	/*
406	 * For backward compatibility, ensure 1st member of any struct
407	 * in union below is uint32_t stream_handle.
408	 */
409	union {
410		struct msm_vfe_axi_stream_cfg_update_info
411					update_info[MSM_ISP_STATS_MAX];
412		struct msm_vfe_axi_stream_cfg_update_info_req_frm req_frm_ver2;
413	};
414};
415
416struct msm_vfe_smmu_attach_cmd {
417	uint32_t security_mode;
418	uint32_t iommu_attach_mode;
419};
420
421struct msm_vfe_stats_stream_request_cmd {
422	uint32_t session_id;
423	uint32_t stream_id;
424	enum msm_isp_stats_type stats_type;
425	uint32_t composite_flag;
426	uint32_t framedrop_pattern;
427	uint32_t init_frame_drop; /*MAX 31 Frames*/
428	uint32_t irq_subsample_pattern;
429	uint32_t buffer_offset;
430	uint32_t stream_handle;
431};
432
433struct msm_vfe_stats_stream_release_cmd {
434	uint32_t stream_handle;
435};
436struct msm_vfe_stats_stream_cfg_cmd {
437	uint8_t num_streams;
438	uint32_t stream_handle[MSM_ISP_STATS_MAX];
439	uint8_t enable;
440	uint32_t stats_burst_len;
441};
442
443enum msm_vfe_reg_cfg_type {
444	VFE_WRITE,
445	VFE_WRITE_MB,
446	VFE_READ,
447	VFE_CFG_MASK,
448	VFE_WRITE_DMI_16BIT,
449	VFE_WRITE_DMI_32BIT,
450	VFE_WRITE_DMI_64BIT,
451	VFE_READ_DMI_16BIT,
452	VFE_READ_DMI_32BIT,
453	VFE_READ_DMI_64BIT,
454	GET_MAX_CLK_RATE,
455	GET_CLK_RATES,
456	GET_ISP_ID,
457	VFE_HW_UPDATE_LOCK,
458	VFE_HW_UPDATE_UNLOCK,
459	SET_WM_UB_SIZE,
460	SET_UB_POLICY,
461	GET_VFE_HW_LIMIT,
462};
463
464struct msm_vfe_cfg_cmd2 {
465	uint16_t num_cfg;
466	uint16_t cmd_len;
467	void *cfg_data;
468	void *cfg_cmd;
469};
470
471struct msm_vfe_cfg_cmd_list {
472	struct msm_vfe_cfg_cmd2      cfg_cmd;
473	struct msm_vfe_cfg_cmd_list *next;
474	uint32_t                     next_size;
475};
476
477struct msm_vfe_reg_rw_info {
478	uint32_t reg_offset;
479	uint32_t cmd_data_offset;
480	uint32_t len;
481};
482
483struct msm_vfe_reg_mask_info {
484	uint32_t reg_offset;
485	uint32_t mask;
486	uint32_t val;
487};
488
489struct msm_vfe_reg_dmi_info {
490	uint32_t hi_tbl_offset; /*Optional*/
491	uint32_t lo_tbl_offset; /*Required*/
492	uint32_t len;
493};
494
495struct msm_vfe_reg_cfg_cmd {
496	union {
497		struct msm_vfe_reg_rw_info rw_info;
498		struct msm_vfe_reg_mask_info mask_info;
499		struct msm_vfe_reg_dmi_info dmi_info;
500	} u;
501
502	enum msm_vfe_reg_cfg_type cmd_type;
503};
504
505enum vfe_sd_type {
506	VFE_SD_0 = 0,
507	VFE_SD_1,
508	VFE_SD_COMMON,
509	VFE_SD_MAX,
510};
511
512/* When you change the value below, check for the sof event_data size.
513 * V4l2 limits payload to 64 bytes */
514#define MS_NUM_SLAVE_MAX 1
515
516/* Usecases when 2 HW need to be related or synced */
517enum msm_vfe_dual_hw_type {
518	DUAL_NONE = 0,
519	DUAL_HW_VFE_SPLIT = 1,
520	DUAL_HW_MASTER_SLAVE = 2,
521};
522
523/* Type for 2 INTF when used in Master-Slave mode */
524enum msm_vfe_dual_hw_ms_type {
525	MS_TYPE_NONE,
526	MS_TYPE_MASTER,
527	MS_TYPE_SLAVE,
528};
529
530struct msm_isp_set_dual_hw_ms_cmd {
531	uint8_t num_src;
532	/* Each session can be only one type but multiple intf if YUV cam */
533	enum msm_vfe_dual_hw_ms_type dual_hw_ms_type;
534	/* Primary intf is mostly associated with preview.
535	 * This primary intf SOF frame_id and timestamp is tracked
536	 * and used to calculate delta */
537	enum msm_vfe_input_src primary_intf;
538	/* input_src array indicates other input INTF that may be Master/Slave.
539	 * For these additional intf, frame_id and timestamp are not saved.
540	 * However, if these are slaves then they will still get their
541	 * frame_id from Master */
542	enum msm_vfe_input_src input_src[VFE_SRC_MAX];
543	uint32_t sof_delta_threshold; /* In milliseconds. Sent for Master */
544};
545
546enum msm_isp_buf_type {
547	ISP_PRIVATE_BUF,
548	ISP_SHARE_BUF,
549	MAX_ISP_BUF_TYPE,
550};
551
552struct msm_isp_unmap_buf_req {
553	uint32_t fd;
554};
555
556struct msm_isp_buf_request {
557	uint32_t session_id;
558	uint32_t stream_id;
559	uint8_t num_buf;
560	uint32_t handle;
561	enum msm_isp_buf_type buf_type;
562};
563
564struct msm_isp_buf_request_ver2 {
565	uint32_t session_id;
566	uint32_t stream_id;
567	uint8_t num_buf;
568	uint32_t handle;
569	enum msm_isp_buf_type buf_type;
570	enum smmu_attach_mode security_mode;
571	uint32_t reserved[4];
572};
573
574struct msm_isp_qbuf_plane {
575	uint32_t addr;
576	uint32_t offset;
577	uint32_t length;
578};
579
580struct msm_isp_qbuf_buffer {
581	struct msm_isp_qbuf_plane planes[MAX_PLANES_PER_STREAM];
582	uint32_t num_planes;
583};
584
585struct msm_isp_qbuf_info {
586	uint32_t handle;
587	int32_t buf_idx;
588	/*Only used for prepare buffer*/
589	struct msm_isp_qbuf_buffer buffer;
590	/*Only used for diverted buffer*/
591	uint32_t dirty_buf;
592};
593
594struct msm_isp_clk_rates {
595	uint32_t svs_rate;
596	uint32_t nominal_rate;
597	uint32_t high_rate;
598};
599
600struct msm_vfe_axi_src_state {
601	enum msm_vfe_input_src input_src;
602	uint32_t src_active;
603	uint32_t src_frame_id;
604};
605
606enum msm_isp_event_mask_index {
607	ISP_EVENT_MASK_INDEX_STATS_NOTIFY		= 0,
608	ISP_EVENT_MASK_INDEX_ERROR			= 1,
609	ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT		= 2,
610	ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE		= 3,
611	ISP_EVENT_MASK_INDEX_REG_UPDATE			= 4,
612	ISP_EVENT_MASK_INDEX_SOF			= 5,
613	ISP_EVENT_MASK_INDEX_BUF_DIVERT			= 6,
614	ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY		= 7,
615	ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE		= 8,
616	ISP_EVENT_MASK_INDEX_BUF_DONE			= 9,
617	ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING		= 10,
618	ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH		= 11,
619	ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR		= 12,
620};
621
622
623#define ISP_EVENT_SUBS_MASK_NONE			0
624
625#define ISP_EVENT_SUBS_MASK_STATS_NOTIFY \
626			(1 << ISP_EVENT_MASK_INDEX_STATS_NOTIFY)
627
628#define ISP_EVENT_SUBS_MASK_ERROR \
629			(1 << ISP_EVENT_MASK_INDEX_ERROR)
630
631#define ISP_EVENT_SUBS_MASK_IOMMU_P_FAULT \
632			(1 << ISP_EVENT_MASK_INDEX_IOMMU_P_FAULT)
633
634#define ISP_EVENT_SUBS_MASK_STREAM_UPDATE_DONE \
635			(1 << ISP_EVENT_MASK_INDEX_STREAM_UPDATE_DONE)
636
637#define ISP_EVENT_SUBS_MASK_REG_UPDATE \
638			(1 << ISP_EVENT_MASK_INDEX_REG_UPDATE)
639
640#define ISP_EVENT_SUBS_MASK_SOF \
641			(1 << ISP_EVENT_MASK_INDEX_SOF)
642
643#define ISP_EVENT_SUBS_MASK_BUF_DIVERT \
644			(1 << ISP_EVENT_MASK_INDEX_BUF_DIVERT)
645
646#define ISP_EVENT_SUBS_MASK_COMP_STATS_NOTIFY \
647			(1 << ISP_EVENT_MASK_INDEX_COMP_STATS_NOTIFY)
648
649#define ISP_EVENT_SUBS_MASK_FE_READ_DONE \
650			(1 << ISP_EVENT_MASK_INDEX_MASK_FE_READ_DONE)
651
652#define ISP_EVENT_SUBS_MASK_BUF_DONE \
653			(1 << ISP_EVENT_MASK_INDEX_BUF_DONE)
654
655#define ISP_EVENT_SUBS_MASK_REG_UPDATE_MISSING \
656			(1 << ISP_EVENT_MASK_INDEX_REG_UPDATE_MISSING)
657
658#define ISP_EVENT_SUBS_MASK_PING_PONG_MISMATCH \
659			(1 << ISP_EVENT_MASK_INDEX_PING_PONG_MISMATCH)
660
661#define ISP_EVENT_SUBS_MASK_BUF_FATAL_ERROR \
662			(1 << ISP_EVENT_MASK_INDEX_BUF_FATAL_ERROR)
663
664enum msm_isp_event_idx {
665	ISP_REG_UPDATE        = 0,
666	ISP_EPOCH_0           = 1,
667	ISP_EPOCH_1           = 2,
668	ISP_START_ACK         = 3,
669	ISP_STOP_ACK          = 4,
670	ISP_IRQ_VIOLATION     = 5,
671	ISP_STATS_OVERFLOW    = 6,
672	ISP_BUF_DONE          = 7,
673	ISP_FE_RD_DONE        = 8,
674	ISP_IOMMU_P_FAULT     = 9,
675	ISP_ERROR             = 10,
676	ISP_HW_FATAL_ERROR      = 11,
677	ISP_PING_PONG_MISMATCH = 12,
678	ISP_REG_UPDATE_MISSING = 13,
679	ISP_BUF_FATAL_ERROR = 14,
680	ISP_EVENT_MAX         = 15
681};
682
683#define ISP_EVENT_OFFSET          8
684#define ISP_EVENT_BASE            (V4L2_EVENT_PRIVATE_START)
685#define ISP_BUF_EVENT_BASE        (ISP_EVENT_BASE + (1 << ISP_EVENT_OFFSET))
686#define ISP_STATS_EVENT_BASE      (ISP_EVENT_BASE + (2 << ISP_EVENT_OFFSET))
687#define ISP_CAMIF_EVENT_BASE      (ISP_EVENT_BASE + (3 << ISP_EVENT_OFFSET))
688#define ISP_STREAM_EVENT_BASE     (ISP_EVENT_BASE + (4 << ISP_EVENT_OFFSET))
689#define ISP_EVENT_REG_UPDATE      (ISP_EVENT_BASE + ISP_REG_UPDATE)
690#define ISP_EVENT_EPOCH_0         (ISP_EVENT_BASE + ISP_EPOCH_0)
691#define ISP_EVENT_EPOCH_1         (ISP_EVENT_BASE + ISP_EPOCH_1)
692#define ISP_EVENT_START_ACK       (ISP_EVENT_BASE + ISP_START_ACK)
693#define ISP_EVENT_STOP_ACK        (ISP_EVENT_BASE + ISP_STOP_ACK)
694#define ISP_EVENT_IRQ_VIOLATION   (ISP_EVENT_BASE + ISP_IRQ_VIOLATION)
695#define ISP_EVENT_STATS_OVERFLOW  (ISP_EVENT_BASE + ISP_STATS_OVERFLOW)
696#define ISP_EVENT_ERROR           (ISP_EVENT_BASE + ISP_ERROR)
697#define ISP_EVENT_SOF             (ISP_CAMIF_EVENT_BASE)
698#define ISP_EVENT_EOF             (ISP_CAMIF_EVENT_BASE + 1)
699#define ISP_EVENT_BUF_DONE        (ISP_EVENT_BASE + ISP_BUF_DONE)
700#define ISP_EVENT_BUF_DIVERT      (ISP_BUF_EVENT_BASE)
701#define ISP_EVENT_STATS_NOTIFY    (ISP_STATS_EVENT_BASE)
702#define ISP_EVENT_COMP_STATS_NOTIFY (ISP_EVENT_STATS_NOTIFY + MSM_ISP_STATS_MAX)
703#define ISP_EVENT_FE_READ_DONE    (ISP_EVENT_BASE + ISP_FE_RD_DONE)
704#define ISP_EVENT_IOMMU_P_FAULT   (ISP_EVENT_BASE + ISP_IOMMU_P_FAULT)
705#define ISP_EVENT_HW_FATAL_ERROR  (ISP_EVENT_BASE + ISP_HW_FATAL_ERROR)
706#define ISP_EVENT_PING_PONG_MISMATCH (ISP_EVENT_BASE + ISP_PING_PONG_MISMATCH)
707#define ISP_EVENT_REG_UPDATE_MISSING (ISP_EVENT_BASE + ISP_REG_UPDATE_MISSING)
708#define ISP_EVENT_BUF_FATAL_ERROR (ISP_EVENT_BASE + ISP_BUF_FATAL_ERROR)
709#define ISP_EVENT_STREAM_UPDATE_DONE   (ISP_STREAM_EVENT_BASE)
710
711/* The msm_v4l2_event_data structure should match the
712 * v4l2_event.u.data field.
713 * should not exceed 64 bytes */
714
715struct msm_isp_buf_event {
716	uint32_t session_id;
717	uint32_t stream_id;
718	uint32_t handle;
719	uint32_t output_format;
720	int8_t buf_idx;
721};
722struct msm_isp_fetch_eng_event {
723	uint32_t session_id;
724	uint32_t stream_id;
725	uint32_t handle;
726	uint32_t fd;
727	int8_t buf_idx;
728	int8_t offline_mode;
729};
730struct msm_isp_stats_event {
731	uint32_t stats_mask;                        /* 4 bytes */
732	uint8_t stats_buf_idxs[MSM_ISP_STATS_MAX];  /* 11 bytes */
733	uint8_t pd_stats_idx;
734};
735
736struct msm_isp_stream_ack {
737	uint32_t session_id;
738	uint32_t stream_id;
739	uint32_t handle;
740};
741
742enum msm_vfe_error_type {
743	ISP_ERROR_NONE,
744	ISP_ERROR_CAMIF,
745	ISP_ERROR_BUS_OVERFLOW,
746	ISP_ERROR_RETURN_EMPTY_BUFFER,
747	ISP_ERROR_FRAME_ID_MISMATCH,
748	ISP_ERROR_MAX,
749};
750
751struct msm_isp_error_info {
752	enum msm_vfe_error_type err_type;
753	uint32_t session_id;
754	uint32_t stream_id;
755	uint32_t stream_id_mask;
756};
757
758/* This structure reports delta between master and slave */
759struct msm_isp_ms_delta_info {
760	uint8_t num_delta_info;
761	uint32_t delta[MS_NUM_SLAVE_MAX];
762};
763
764/* This is sent in EPOCH irq */
765struct msm_isp_output_info {
766	uint8_t regs_not_updated;
767	/* mask with bufq_handle for regs not updated or return empty */
768	uint16_t output_err_mask;
769	/* mask with stream_idx for get_buf failed */
770	uint8_t stream_framedrop_mask;
771	/* mask with stats stream_idx for get_buf failed */
772	uint16_t stats_framedrop_mask;
773	/* delta between master and slave */
774};
775
776/* This structure is piggybacked with SOF event */
777struct msm_isp_sof_info {
778	uint8_t regs_not_updated;
779	/* mask with bufq_handle for regs not updated */
780	uint16_t reg_update_fail_mask;
781	/* mask with bufq_handle for get_buf failed */
782	uint32_t stream_get_buf_fail_mask;
783	/* mask with stats stream_idx for get_buf failed */
784	uint16_t stats_get_buf_fail_mask;
785	/* delta between master and slave */
786	struct msm_isp_ms_delta_info ms_delta_info;
787	/*
788	 * mask with AXI_SRC in paused state. In PAUSED
789	 * state there is no Buffer output. So this mask is used
790	 * to report drop.
791	 */
792	uint16_t axi_updating_mask;
793	/* extended mask with bufq_handle for regs not updated */
794	uint32_t reg_update_fail_mask_ext;
795};
796#define AXI_UPDATING_MASK 1
797#define REG_UPDATE_FAIL_MASK_EXT 1
798
799struct msm_isp_event_data {
800	/*Wall clock except for buffer divert events
801	 *which use monotonic clock
802	 */
803	struct timeval timestamp;
804	/* Monotonic timestamp since bootup */
805	struct timeval mono_timestamp;
806	uint32_t frame_id;
807	union {
808		/* Sent for Stats_Done event */
809		struct msm_isp_stats_event stats;
810		/* Sent for Buf_Divert event */
811		struct msm_isp_buf_event buf_done;
812		/* Sent for offline fetch done event */
813		struct msm_isp_fetch_eng_event fetch_done;
814		/* Sent for Error_Event */
815		struct msm_isp_error_info error_info;
816		/*
817		 * This struct needs to be removed once
818		 * userspace switches to sof_info
819		 */
820		struct msm_isp_output_info output_info;
821		/* Sent for SOF event */
822		struct msm_isp_sof_info sof_info;
823	} u; /* union can have max 52 bytes */
824};
825
826enum msm_vfe_ahb_clk_vote {
827	MSM_ISP_CAMERA_AHB_SVS_VOTE = 1,
828	MSM_ISP_CAMERA_AHB_TURBO_VOTE = 2,
829	MSM_ISP_CAMERA_AHB_NOMINAL_VOTE = 3,
830	MSM_ISP_CAMERA_AHB_SUSPEND_VOTE = 4,
831};
832
833struct msm_isp_ahb_clk_cfg {
834	uint32_t vote;
835	uint32_t reserved[2];
836};
837
838enum msm_vfe_dual_cam_sync_mode {
839	MSM_ISP_DUAL_CAM_ASYNC,
840	MSM_ISP_DUAL_CAM_SYNC,
841};
842
843struct msm_isp_dual_hw_master_slave_sync {
844	uint32_t sync_mode;
845	uint32_t reserved[2];
846};
847
848struct msm_vfe_dual_lpm_mode {
849	enum msm_vfe_axi_stream_src stream_src[VFE_AXI_SRC_MAX];
850	uint32_t num_src;
851	uint32_t lpm_mode;
852};
853#define V4L2_PIX_FMT_QBGGR8  v4l2_fourcc('Q', 'B', 'G', '8')
854#define V4L2_PIX_FMT_QGBRG8  v4l2_fourcc('Q', 'G', 'B', '8')
855#define V4L2_PIX_FMT_QGRBG8  v4l2_fourcc('Q', 'G', 'R', '8')
856#define V4L2_PIX_FMT_QRGGB8  v4l2_fourcc('Q', 'R', 'G', '8')
857#define V4L2_PIX_FMT_QBGGR10 v4l2_fourcc('Q', 'B', 'G', '0')
858#define V4L2_PIX_FMT_QGBRG10 v4l2_fourcc('Q', 'G', 'B', '0')
859#define V4L2_PIX_FMT_QGRBG10 v4l2_fourcc('Q', 'G', 'R', '0')
860#define V4L2_PIX_FMT_QRGGB10 v4l2_fourcc('Q', 'R', 'G', '0')
861#define V4L2_PIX_FMT_QBGGR12 v4l2_fourcc('Q', 'B', 'G', '2')
862#define V4L2_PIX_FMT_QGBRG12 v4l2_fourcc('Q', 'G', 'B', '2')
863#define V4L2_PIX_FMT_QGRBG12 v4l2_fourcc('Q', 'G', 'R', '2')
864#define V4L2_PIX_FMT_QRGGB12 v4l2_fourcc('Q', 'R', 'G', '2')
865#define V4L2_PIX_FMT_QBGGR14 v4l2_fourcc('Q', 'B', 'G', '4')
866#define V4L2_PIX_FMT_QGBRG14 v4l2_fourcc('Q', 'G', 'B', '4')
867#define V4L2_PIX_FMT_QGRBG14 v4l2_fourcc('Q', 'G', 'R', '4')
868#define V4L2_PIX_FMT_QRGGB14 v4l2_fourcc('Q', 'R', 'G', '4')
869#define V4L2_PIX_FMT_P16BGGR10 v4l2_fourcc('P', 'B', 'G', '0')
870#define V4L2_PIX_FMT_P16GBRG10 v4l2_fourcc('P', 'G', 'B', '0')
871#define V4L2_PIX_FMT_P16GRBG10 v4l2_fourcc('P', 'G', 'R', '0')
872#define V4L2_PIX_FMT_P16RGGB10 v4l2_fourcc('P', 'R', 'G', '0')
873#define V4L2_PIX_FMT_NV14 v4l2_fourcc('N', 'V', '1', '4')
874#define V4L2_PIX_FMT_NV41 v4l2_fourcc('N', 'V', '4', '1')
875#define V4L2_PIX_FMT_META v4l2_fourcc('Q', 'M', 'E', 'T')
876#define V4L2_PIX_FMT_META10 v4l2_fourcc('Q', 'M', '1', '0')
877#define V4L2_PIX_FMT_SBGGR14 v4l2_fourcc('B', 'G', '1', '4') /* 14 BGBG.GRGR.*/
878#define V4L2_PIX_FMT_SGBRG14 v4l2_fourcc('G', 'B', '1', '4') /* 14 GBGB.RGRG.*/
879#define V4L2_PIX_FMT_SGRBG14 v4l2_fourcc('B', 'A', '1', '4') /* 14 GRGR.BGBG.*/
880#define V4L2_PIX_FMT_SRGGB14 v4l2_fourcc('R', 'G', '1', '4') /* 14 RGRG.GBGB.*/
881
882enum msm_isp_ioctl_cmd_code {
883	MSM_VFE_REG_CFG = BASE_VIDIOC_PRIVATE,
884	MSM_ISP_REQUEST_BUF,
885	MSM_ISP_ENQUEUE_BUF,
886	MSM_ISP_RELEASE_BUF,
887	MSM_ISP_REQUEST_STREAM,
888	MSM_ISP_CFG_STREAM,
889	MSM_ISP_RELEASE_STREAM,
890	MSM_ISP_INPUT_CFG,
891	MSM_ISP_SET_SRC_STATE,
892	MSM_ISP_REQUEST_STATS_STREAM,
893	MSM_ISP_CFG_STATS_STREAM,
894	MSM_ISP_RELEASE_STATS_STREAM,
895	MSM_ISP_REG_UPDATE_CMD,
896	MSM_ISP_UPDATE_STREAM,
897	MSM_VFE_REG_LIST_CFG,
898	MSM_ISP_SMMU_ATTACH,
899	MSM_ISP_UPDATE_STATS_STREAM,
900	MSM_ISP_AXI_HALT,
901	MSM_ISP_AXI_RESET,
902	MSM_ISP_AXI_RESTART,
903	MSM_ISP_FETCH_ENG_START,
904	MSM_ISP_DEQUEUE_BUF,
905	MSM_ISP_SET_DUAL_HW_MASTER_SLAVE,
906	MSM_ISP_MAP_BUF_START_FE,
907	MSM_ISP_UNMAP_BUF,
908	MSM_ISP_AHB_CLK_CFG,
909	MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC,
910	MSM_ISP_FETCH_ENG_MULTI_PASS_START,
911	MSM_ISP_MAP_BUF_START_MULTI_PASS_FE,
912	MSM_ISP_REQUEST_BUF_VER2,
913	MSM_ISP_DUAL_HW_LPM_MODE,
914};
915
916#define VIDIOC_MSM_VFE_REG_CFG \
917	_IOWR('V', MSM_VFE_REG_CFG, \
918		struct msm_vfe_cfg_cmd2)
919
920#define VIDIOC_MSM_ISP_REQUEST_BUF \
921	_IOWR('V', MSM_ISP_REQUEST_BUF, \
922		struct msm_isp_buf_request)
923
924#define VIDIOC_MSM_ISP_ENQUEUE_BUF \
925	_IOWR('V', MSM_ISP_ENQUEUE_BUF, \
926		struct msm_isp_qbuf_info)
927
928#define VIDIOC_MSM_ISP_RELEASE_BUF \
929	_IOWR('V', MSM_ISP_RELEASE_BUF, \
930		struct msm_isp_buf_request)
931
932#define VIDIOC_MSM_ISP_REQUEST_STREAM \
933	_IOWR('V', MSM_ISP_REQUEST_STREAM, \
934		struct msm_vfe_axi_stream_request_cmd)
935
936#define VIDIOC_MSM_ISP_CFG_STREAM \
937	_IOWR('V', MSM_ISP_CFG_STREAM, \
938		struct msm_vfe_axi_stream_cfg_cmd)
939
940#define VIDIOC_MSM_ISP_RELEASE_STREAM \
941	_IOWR('V', MSM_ISP_RELEASE_STREAM, \
942		struct msm_vfe_axi_stream_release_cmd)
943
944#define VIDIOC_MSM_ISP_INPUT_CFG \
945	_IOWR('V', MSM_ISP_INPUT_CFG, \
946		struct msm_vfe_input_cfg)
947
948#define VIDIOC_MSM_ISP_SET_SRC_STATE \
949	_IOWR('V', MSM_ISP_SET_SRC_STATE, \
950		struct msm_vfe_axi_src_state)
951
952#define VIDIOC_MSM_ISP_REQUEST_STATS_STREAM \
953	_IOWR('V', MSM_ISP_REQUEST_STATS_STREAM, \
954		struct msm_vfe_stats_stream_request_cmd)
955
956#define VIDIOC_MSM_ISP_CFG_STATS_STREAM \
957	_IOWR('V', MSM_ISP_CFG_STATS_STREAM, \
958		struct msm_vfe_stats_stream_cfg_cmd)
959
960#define VIDIOC_MSM_ISP_RELEASE_STATS_STREAM \
961	_IOWR('V', MSM_ISP_RELEASE_STATS_STREAM, \
962		struct msm_vfe_stats_stream_release_cmd)
963
964#define VIDIOC_MSM_ISP_REG_UPDATE_CMD \
965	_IOWR('V', MSM_ISP_REG_UPDATE_CMD, \
966		enum msm_vfe_input_src)
967
968#define VIDIOC_MSM_ISP_UPDATE_STREAM \
969	_IOWR('V', MSM_ISP_UPDATE_STREAM, \
970		struct msm_vfe_axi_stream_update_cmd)
971
972#define VIDIOC_MSM_VFE_REG_LIST_CFG \
973	_IOWR('V', MSM_VFE_REG_LIST_CFG, \
974		struct msm_vfe_cfg_cmd_list)
975
976#define VIDIOC_MSM_ISP_SMMU_ATTACH \
977	_IOWR('V', MSM_ISP_SMMU_ATTACH, \
978		struct msm_vfe_smmu_attach_cmd)
979
980#define VIDIOC_MSM_ISP_UPDATE_STATS_STREAM \
981	_IOWR('V', MSM_ISP_UPDATE_STATS_STREAM, \
982		struct msm_vfe_axi_stream_update_cmd)
983
984#define VIDIOC_MSM_ISP_AXI_HALT \
985	_IOWR('V', MSM_ISP_AXI_HALT, \
986		struct msm_vfe_axi_halt_cmd)
987
988#define VIDIOC_MSM_ISP_AXI_RESET \
989	_IOWR('V', MSM_ISP_AXI_RESET, \
990		struct msm_vfe_axi_reset_cmd)
991
992#define VIDIOC_MSM_ISP_AXI_RESTART \
993	_IOWR('V', MSM_ISP_AXI_RESTART, \
994		struct msm_vfe_axi_restart_cmd)
995
996#define VIDIOC_MSM_ISP_FETCH_ENG_START \
997	_IOWR('V', MSM_ISP_FETCH_ENG_START, \
998		struct msm_vfe_fetch_eng_start)
999
1000#define VIDIOC_MSM_ISP_DEQUEUE_BUF \
1001	_IOWR('V', MSM_ISP_DEQUEUE_BUF, \
1002		struct msm_isp_qbuf_info)
1003
1004#define VIDIOC_MSM_ISP_SET_DUAL_HW_MASTER_SLAVE \
1005	_IOWR('V', MSM_ISP_SET_DUAL_HW_MASTER_SLAVE, \
1006		struct msm_isp_set_dual_hw_ms_cmd)
1007
1008#define VIDIOC_MSM_ISP_MAP_BUF_START_FE \
1009	_IOWR('V', MSM_ISP_MAP_BUF_START_FE, \
1010		struct msm_vfe_fetch_eng_start)
1011
1012#define VIDIOC_MSM_ISP_UNMAP_BUF \
1013	_IOWR('V', MSM_ISP_UNMAP_BUF, \
1014		struct msm_isp_unmap_buf_req)
1015
1016#define VIDIOC_MSM_ISP_AHB_CLK_CFG \
1017	_IOWR('V', MSM_ISP_AHB_CLK_CFG, struct msm_isp_ahb_clk_cfg)
1018
1019#define VIDIOC_MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC \
1020	_IOWR('V', MSM_ISP_DUAL_HW_MASTER_SLAVE_SYNC, \
1021	struct msm_isp_dual_hw_master_slave_sync)
1022
1023#define VIDIOC_MSM_ISP_FETCH_ENG_MULTI_PASS_START \
1024	_IOWR('V', MSM_ISP_FETCH_ENG_MULTI_PASS_START, \
1025		struct msm_vfe_fetch_eng_multi_pass_start)
1026
1027#define VIDIOC_MSM_ISP_MAP_BUF_START_MULTI_PASS_FE \
1028	_IOWR('V', MSM_ISP_MAP_BUF_START_MULTI_PASS_FE, \
1029		struct msm_vfe_fetch_eng_multi_pass_start)
1030
1031#define VIDIOC_MSM_ISP_REQUEST_BUF_VER2 \
1032	_IOWR('V', MSM_ISP_REQUEST_BUF_VER2, struct msm_isp_buf_request_ver2)
1033
1034#define VIDIOC_MSM_ISP_DUAL_HW_LPM_MODE \
1035	_IOWR('V', MSM_ISP_DUAL_HW_LPM_MODE, \
1036	struct msm_vfe_dual_lpm_mode)
1037
1038#endif /* __MSMB_ISP__ */
1039