1//===- RegisterClassInfo.h - Dynamic Register Class Info --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the RegisterClassInfo class which provides dynamic
11// information about target register classes. Callee saved and reserved
12// registers depends on calling conventions and other dynamic information, so
13// some things cannot be determined statically.
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H
18#define LLVM_CODEGEN_REGISTERCLASSINFO_H
19
20#include "llvm/ADT/ArrayRef.h"
21#include "llvm/ADT/BitVector.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/Target/TargetRegisterInfo.h"
25#include <cassert>
26#include <cstdint>
27#include <memory>
28
29namespace llvm {
30
31class RegisterClassInfo {
32  struct RCInfo {
33    unsigned Tag = 0;
34    unsigned NumRegs = 0;
35    bool ProperSubClass = false;
36    uint8_t MinCost = 0;
37    uint16_t LastCostChange = 0;
38    std::unique_ptr<MCPhysReg[]> Order;
39
40    RCInfo() = default;
41
42    operator ArrayRef<MCPhysReg>() const {
43      return makeArrayRef(Order.get(), NumRegs);
44    }
45  };
46
47  // Brief cached information for each register class.
48  std::unique_ptr<RCInfo[]> RegClass;
49
50  // Tag changes whenever cached information needs to be recomputed. An RCInfo
51  // entry is valid when its tag matches.
52  unsigned Tag = 0;
53
54  const MachineFunction *MF = nullptr;
55  const TargetRegisterInfo *TRI = nullptr;
56
57  // Callee saved registers of last MF. Assumed to be valid until the next
58  // runOnFunction() call.
59  // Used only to determine if an update was made to CalleeSavedAliases.
60  const MCPhysReg *CalleeSavedRegs = nullptr;
61
62  // Map register alias to the callee saved Register.
63  SmallVector<MCPhysReg, 4> CalleeSavedAliases;
64
65  // Reserved registers in the current MF.
66  BitVector Reserved;
67
68  std::unique_ptr<unsigned[]> PSetLimits;
69
70  // Compute all information about RC.
71  void compute(const TargetRegisterClass *RC) const;
72
73  // Return an up-to-date RCInfo for RC.
74  const RCInfo &get(const TargetRegisterClass *RC) const {
75    const RCInfo &RCI = RegClass[RC->getID()];
76    if (Tag != RCI.Tag)
77      compute(RC);
78    return RCI;
79  }
80
81public:
82  RegisterClassInfo();
83
84  /// runOnFunction - Prepare to answer questions about MF. This must be called
85  /// before any other methods are used.
86  void runOnMachineFunction(const MachineFunction &MF);
87
88  /// getNumAllocatableRegs - Returns the number of actually allocatable
89  /// registers in RC in the current function.
90  unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
91    return get(RC).NumRegs;
92  }
93
94  /// getOrder - Returns the preferred allocation order for RC. The order
95  /// contains no reserved registers, and registers that alias callee saved
96  /// registers come last.
97  ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
98    return get(RC);
99  }
100
101  /// isProperSubClass - Returns true if RC has a legal super-class with more
102  /// allocatable registers.
103  ///
104  /// Register classes like GR32_NOSP are not proper sub-classes because %esp
105  /// is not allocatable.  Similarly, tGPR is not a proper sub-class in Thumb
106  /// mode because the GPR super-class is not legal.
107  bool isProperSubClass(const TargetRegisterClass *RC) const {
108    return get(RC).ProperSubClass;
109  }
110
111  /// getLastCalleeSavedAlias - Returns the last callee saved register that
112  /// overlaps PhysReg, or 0 if Reg doesn't overlap a CalleeSavedAliases.
113  unsigned getLastCalleeSavedAlias(unsigned PhysReg) const {
114    assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
115    if (PhysReg < CalleeSavedAliases.size())
116      return CalleeSavedAliases[PhysReg];
117    return 0;
118  }
119
120  /// Get the minimum register cost in RC's allocation order.
121  /// This is the smallest value returned by TRI->getCostPerUse(Reg) for all
122  /// the registers in getOrder(RC).
123  unsigned getMinCost(const TargetRegisterClass *RC) {
124    return get(RC).MinCost;
125  }
126
127  /// Get the position of the last cost change in getOrder(RC).
128  ///
129  /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
130  /// same cost according to TRI->getCostPerUse().
131  unsigned getLastCostChange(const TargetRegisterClass *RC) {
132    return get(RC).LastCostChange;
133  }
134
135  /// Get the register unit limit for the given pressure set index.
136  ///
137  /// RegisterClassInfo adjusts this limit for reserved registers.
138  unsigned getRegPressureSetLimit(unsigned Idx) const {
139    if (!PSetLimits[Idx])
140      PSetLimits[Idx] = computePSetLimit(Idx);
141    return PSetLimits[Idx];
142  }
143
144protected:
145  unsigned computePSetLimit(unsigned Idx) const;
146};
147
148} // end namespace llvm
149
150#endif // LLVM_CODEGEN_REGISTERCLASSINFO_H
151