1/*===---- prfchwintrin.h - PREFETCHW intrinsic -----------------------------=== 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a copy 4 * of this software and associated documentation files (the "Software"), to deal 5 * in the Software without restriction, including without limitation the rights 6 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 7 * copies of the Software, and to permit persons to whom the Software is 8 * furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 16 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 18 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 19 * THE SOFTWARE. 20 * 21 *===-----------------------------------------------------------------------=== 22 */ 23 24#if !defined(__X86INTRIN_H) && !defined(_MM3DNOW_H_INCLUDED) 25#error "Never use <prfchwintrin.h> directly; include <x86intrin.h> or <mm3dnow.h> instead." 26#endif 27 28#ifndef __PRFCHWINTRIN_H 29#define __PRFCHWINTRIN_H 30 31#if defined(__PRFCHW__) || defined(__3dNOW__) 32/// \brief Loads a memory sequence containing the specified memory address into 33/// all data cache levels. The cache-coherency state is set to exclusive. 34/// Data can be read from and written to the cache line without additional 35/// delay. 36/// 37/// \headerfile <x86intrin.h> 38/// 39/// This intrinsic corresponds to the \c PREFETCHT0 instruction. 40/// 41/// \param __P 42/// A pointer specifying the memory address to be prefetched. 43static __inline__ void __attribute__((__always_inline__, __nodebug__)) 44_m_prefetch(void *__P) 45{ 46 __builtin_prefetch (__P, 0, 3 /* _MM_HINT_T0 */); 47} 48 49/// \brief Loads a memory sequence containing the specified memory address into 50/// the L1 data cache and sets the cache-coherency to modified. This 51/// provides a hint to the processor that the cache line will be modified. 52/// It is intended for use when the cache line will be written to shortly 53/// after the prefetch is performed. Note that the effect of this intrinsic 54/// is dependent on the processor implementation. 55/// 56/// \headerfile <x86intrin.h> 57/// 58/// This intrinsic corresponds to the \c PREFETCHW instruction. 59/// 60/// \param __P 61/// A pointer specifying the memory address to be prefetched. 62static __inline__ void __attribute__((__always_inline__, __nodebug__)) 63_m_prefetchw(void *__P) 64{ 65 __builtin_prefetch (__P, 1, 3 /* _MM_HINT_T0 */); 66} 67#endif 68 69#endif /* __PRFCHWINTRIN_H */ 70