1//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAGISel class, which is used as the common 11// base class for SelectionDAG-based instruction selectors. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H 16#define LLVM_CODEGEN_SELECTIONDAGISEL_H 17 18#include "llvm/CodeGen/MachineFunctionPass.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "llvm/IR/BasicBlock.h" 21#include "llvm/Pass.h" 22#include "llvm/Target/TargetSubtargetInfo.h" 23#include <memory> 24 25namespace llvm { 26 class FastISel; 27 class SelectionDAGBuilder; 28 class SDValue; 29 class MachineRegisterInfo; 30 class MachineBasicBlock; 31 class MachineFunction; 32 class MachineInstr; 33 class OptimizationRemarkEmitter; 34 class TargetLowering; 35 class TargetLibraryInfo; 36 class FunctionLoweringInfo; 37 class ScheduleHazardRecognizer; 38 class GCFunctionInfo; 39 class ScheduleDAGSDNodes; 40 class LoadInst; 41 42/// SelectionDAGISel - This is the common base class used for SelectionDAG-based 43/// pattern-matching instruction selectors. 44class SelectionDAGISel : public MachineFunctionPass { 45public: 46 TargetMachine &TM; 47 const TargetLibraryInfo *LibInfo; 48 FunctionLoweringInfo *FuncInfo; 49 MachineFunction *MF; 50 MachineRegisterInfo *RegInfo; 51 SelectionDAG *CurDAG; 52 SelectionDAGBuilder *SDB; 53 AliasAnalysis *AA; 54 GCFunctionInfo *GFI; 55 CodeGenOpt::Level OptLevel; 56 const TargetInstrInfo *TII; 57 const TargetLowering *TLI; 58 bool FastISelFailed; 59 SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs; 60 61 /// Current optimization remark emitter. 62 /// Used to report things like combines and FastISel failures. 63 std::unique_ptr<OptimizationRemarkEmitter> ORE; 64 65 static char ID; 66 67 explicit SelectionDAGISel(TargetMachine &tm, 68 CodeGenOpt::Level OL = CodeGenOpt::Default); 69 ~SelectionDAGISel() override; 70 71 const TargetLowering *getTargetLowering() const { return TLI; } 72 73 void getAnalysisUsage(AnalysisUsage &AU) const override; 74 75 bool runOnMachineFunction(MachineFunction &MF) override; 76 77 virtual void EmitFunctionEntryCode() {} 78 79 /// PreprocessISelDAG - This hook allows targets to hack on the graph before 80 /// instruction selection starts. 81 virtual void PreprocessISelDAG() {} 82 83 /// PostprocessISelDAG() - This hook allows the target to hack on the graph 84 /// right after selection. 85 virtual void PostprocessISelDAG() {} 86 87 /// Main hook for targets to transform nodes into machine nodes. 88 virtual void Select(SDNode *N) = 0; 89 90 /// SelectInlineAsmMemoryOperand - Select the specified address as a target 91 /// addressing mode, according to the specified constraint. If this does 92 /// not match or is not implemented, return true. The resultant operands 93 /// (which will appear in the machine instruction) should be added to the 94 /// OutOps vector. 95 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 96 unsigned ConstraintID, 97 std::vector<SDValue> &OutOps) { 98 return true; 99 } 100 101 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 102 /// operand node N of U during instruction selection that starts at Root. 103 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 104 105 /// IsLegalToFold - Returns true if the specific operand node N of 106 /// U can be folded during instruction selection that starts at Root. 107 /// FIXME: This is a static member function because the MSP430/X86 108 /// targets, which uses it during isel. This could become a proper member. 109 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 110 CodeGenOpt::Level OptLevel, 111 bool IgnoreChains = false); 112 113 // Opcodes used by the DAG state machine: 114 enum BuiltinOpcodes { 115 OPC_Scope, 116 OPC_RecordNode, 117 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3, 118 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7, 119 OPC_RecordMemRef, 120 OPC_CaptureGlueInput, 121 OPC_MoveChild, 122 OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3, 123 OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7, 124 OPC_MoveParent, 125 OPC_CheckSame, 126 OPC_CheckChild0Same, OPC_CheckChild1Same, 127 OPC_CheckChild2Same, OPC_CheckChild3Same, 128 OPC_CheckPatternPredicate, 129 OPC_CheckPredicate, 130 OPC_CheckOpcode, 131 OPC_SwitchOpcode, 132 OPC_CheckType, 133 OPC_SwitchType, 134 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type, 135 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type, 136 OPC_CheckChild6Type, OPC_CheckChild7Type, 137 OPC_CheckInteger, 138 OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer, 139 OPC_CheckChild3Integer, OPC_CheckChild4Integer, 140 OPC_CheckCondCode, 141 OPC_CheckValueType, 142 OPC_CheckComplexPat, 143 OPC_CheckAndImm, OPC_CheckOrImm, 144 OPC_CheckFoldableChainNode, 145 146 OPC_EmitInteger, 147 OPC_EmitRegister, 148 OPC_EmitRegister2, 149 OPC_EmitConvertToTarget, 150 OPC_EmitMergeInputChains, 151 OPC_EmitMergeInputChains1_0, 152 OPC_EmitMergeInputChains1_1, 153 OPC_EmitMergeInputChains1_2, 154 OPC_EmitCopyToReg, 155 OPC_EmitNodeXForm, 156 OPC_EmitNode, 157 // Space-optimized forms that implicitly encode number of result VTs. 158 OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2, 159 OPC_MorphNodeTo, 160 // Space-optimized forms that implicitly encode number of result VTs. 161 OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2, 162 OPC_CompleteMatch, 163 // Contains offset in table for pattern being selected 164 OPC_Coverage 165 }; 166 167 enum { 168 OPFL_None = 0, // Node has no chain or glue input and isn't variadic. 169 OPFL_Chain = 1, // Node has a chain input. 170 OPFL_GlueInput = 2, // Node has a glue input. 171 OPFL_GlueOutput = 4, // Node has a glue output. 172 OPFL_MemRefs = 8, // Node gets accumulated MemRefs. 173 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs. 174 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs. 175 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs. 176 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs. 177 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs. 178 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs. 179 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs. 180 181 OPFL_VariadicInfo = OPFL_Variadic6 182 }; 183 184 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the 185 /// number of fixed arity values that should be skipped when copying from the 186 /// root. 187 static inline int getNumFixedFromVariadicInfo(unsigned Flags) { 188 return ((Flags&OPFL_VariadicInfo) >> 4)-1; 189 } 190 191 192protected: 193 /// DAGSize - Size of DAG being instruction selected. 194 /// 195 unsigned DAGSize; 196 197 /// ReplaceUses - replace all uses of the old node F with the use 198 /// of the new node T. 199 void ReplaceUses(SDValue F, SDValue T) { 200 CurDAG->ReplaceAllUsesOfValueWith(F, T); 201 } 202 203 /// ReplaceUses - replace all uses of the old nodes F with the use 204 /// of the new nodes T. 205 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) { 206 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num); 207 } 208 209 /// ReplaceUses - replace all uses of the old node F with the use 210 /// of the new node T. 211 void ReplaceUses(SDNode *F, SDNode *T) { 212 CurDAG->ReplaceAllUsesWith(F, T); 213 } 214 215 /// Replace all uses of \c F with \c T, then remove \c F from the DAG. 216 void ReplaceNode(SDNode *F, SDNode *T) { 217 CurDAG->ReplaceAllUsesWith(F, T); 218 CurDAG->RemoveDeadNode(F); 219 } 220 221 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 222 /// by tblgen. Others should not call it. 223 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops, 224 const SDLoc &DL); 225 226 /// getPatternForIndex - Patterns selected by tablegen during ISEL 227 virtual StringRef getPatternForIndex(unsigned index) { 228 llvm_unreachable("Tblgen should generate the implementation of this!"); 229 } 230 231 /// getIncludePathForIndex - get the td source location of pattern instantiation 232 virtual StringRef getIncludePathForIndex(unsigned index) { 233 llvm_unreachable("Tblgen should generate the implementation of this!"); 234 } 235public: 236 // Calls to these predicates are generated by tblgen. 237 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 238 int64_t DesiredMaskS) const; 239 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 240 int64_t DesiredMaskS) const; 241 242 243 /// CheckPatternPredicate - This function is generated by tblgen in the 244 /// target. It runs the specified pattern predicate and returns true if it 245 /// succeeds or false if it fails. The number is a private implementation 246 /// detail to the code tblgen produces. 247 virtual bool CheckPatternPredicate(unsigned PredNo) const { 248 llvm_unreachable("Tblgen should generate the implementation of this!"); 249 } 250 251 /// CheckNodePredicate - This function is generated by tblgen in the target. 252 /// It runs node predicate number PredNo and returns true if it succeeds or 253 /// false if it fails. The number is a private implementation 254 /// detail to the code tblgen produces. 255 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const { 256 llvm_unreachable("Tblgen should generate the implementation of this!"); 257 } 258 259 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N, 260 unsigned PatternNo, 261 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) { 262 llvm_unreachable("Tblgen should generate the implementation of this!"); 263 } 264 265 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) { 266 llvm_unreachable("Tblgen should generate this!"); 267 } 268 269 void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 270 unsigned TableSize); 271 272 /// \brief Return true if complex patterns for this target can mutate the 273 /// DAG. 274 virtual bool ComplexPatternFuncMutatesDAG() const { 275 return false; 276 } 277 278private: 279 280 // Calls to these functions are generated by tblgen. 281 void Select_INLINEASM(SDNode *N); 282 void Select_READ_REGISTER(SDNode *N); 283 void Select_WRITE_REGISTER(SDNode *N); 284 void Select_UNDEF(SDNode *N); 285 void CannotYetSelect(SDNode *N); 286 287private: 288 void DoInstructionSelection(); 289 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs, 290 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo); 291 292 SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc); 293 294 /// Prepares the landing pad to take incoming values or do other EH 295 /// personality specific tasks. Returns true if the block should be 296 /// instruction selected, false if no code should be emitted for it. 297 bool PrepareEHLandingPad(); 298 299 /// \brief Perform instruction selection on all basic blocks in the function. 300 void SelectAllBasicBlocks(const Function &Fn); 301 302 /// \brief Perform instruction selection on a single basic block, for 303 /// instructions between \p Begin and \p End. \p HadTailCall will be set 304 /// to true if a call in the block was translated as a tail call. 305 void SelectBasicBlock(BasicBlock::const_iterator Begin, 306 BasicBlock::const_iterator End, 307 bool &HadTailCall); 308 void FinishBasicBlock(); 309 310 void CodeGenAndEmitDAG(); 311 312 /// \brief Generate instructions for lowering the incoming arguments of the 313 /// given function. 314 void LowerArguments(const Function &F); 315 316 void ComputeLiveOutVRegInfo(); 317 318 /// Create the scheduler. If a specific scheduler was specified 319 /// via the SchedulerRegistry, use it, otherwise select the 320 /// one preferred by the target. 321 /// 322 ScheduleDAGSDNodes *CreateScheduler(); 323 324 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel 325 /// state machines that start with a OPC_SwitchOpcode node. 326 std::vector<unsigned> OpcodeOffset; 327 328 void UpdateChains(SDNode *NodeToMatch, SDValue InputChain, 329 SmallVectorImpl<SDNode *> &ChainNodesMatched, 330 bool isMorphNodeTo); 331}; 332 333} 334 335#endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */ 336