Lines Matching refs:ctrl
184 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
466 unsigned int ctrl; /* FUNCTRL0 current value */
708 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
709 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
826 cm->ctrl &= ~val;
828 cm->ctrl |= val;
829 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
830 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
904 cm->ctrl |= chen;
906 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
907 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
914 cm->ctrl &= ~chen;
915 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | reset);
916 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~reset);
921 cm->ctrl |= pause;
922 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
926 cm->ctrl &= ~pause;
927 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1363 cm->ctrl |= CM_CHEN0 << rec->ch;
1364 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl);
1371 cm->ctrl &= ~(CM_CHEN0 << rec->ch);
1373 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl | val);
1374 snd_cmipci_write(cm, CM_REG_FUNCTRL0, cm->ctrl & ~val);
3087 cm->ctrl = CM_CHADC0; /* default FUNCNTRL0 */
3089 cm->ctrl = CM_CHADC1; /* default FUNCNTRL0 */