1/****************************************************************************** 2 3 AudioScience HPI driver 4 Copyright (C) 1997-2010 AudioScience Inc. <support@audioscience.com> 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of version 2 of the GNU General Public License as 8 published by the Free Software Foundation; 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the Free Software 17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 19 Hardware Programming Interface (HPI) for AudioScience 20 ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters. 21 These PCI and PCIe bus adapters are based on a 22 TMS320C6205 PCI bus mastering DSP, 23 and (except ASI50xx) TI TMS320C6xxx floating point DSP 24 25 Exported function: 26 void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) 27 28(C) Copyright AudioScience Inc. 1998-2010 29*******************************************************************************/ 30#define SOURCEFILE_NAME "hpi6205.c" 31 32#include "hpi_internal.h" 33#include "hpimsginit.h" 34#include "hpidebug.h" 35#include "hpi6205.h" 36#include "hpidspcd.h" 37#include "hpicmn.h" 38 39/*****************************************************************************/ 40/* HPI6205 specific error codes */ 41#define HPI6205_ERROR_BASE 1000 /* not actually used anywhere */ 42 43/* operational/messaging errors */ 44#define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015 45#define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016 46 47/* initialization/bootload errors */ 48#define HPI6205_ERROR_6205_NO_IRQ 1002 49#define HPI6205_ERROR_6205_INIT_FAILED 1003 50#define HPI6205_ERROR_6205_REG 1006 51#define HPI6205_ERROR_6205_DSPPAGE 1007 52#define HPI6205_ERROR_C6713_HPIC 1009 53#define HPI6205_ERROR_C6713_HPIA 1010 54#define HPI6205_ERROR_C6713_PLL 1011 55#define HPI6205_ERROR_DSP_INTMEM 1012 56#define HPI6205_ERROR_DSP_EXTMEM 1013 57#define HPI6205_ERROR_DSP_PLD 1014 58#define HPI6205_ERROR_6205_EEPROM 1017 59#define HPI6205_ERROR_DSP_EMIF 1018 60 61/*****************************************************************************/ 62/* for C6205 PCI i/f */ 63/* Host Status Register (HSR) bitfields */ 64#define C6205_HSR_INTSRC 0x01 65#define C6205_HSR_INTAVAL 0x02 66#define C6205_HSR_INTAM 0x04 67#define C6205_HSR_CFGERR 0x08 68#define C6205_HSR_EEREAD 0x10 69/* Host-to-DSP Control Register (HDCR) bitfields */ 70#define C6205_HDCR_WARMRESET 0x01 71#define C6205_HDCR_DSPINT 0x02 72#define C6205_HDCR_PCIBOOT 0x04 73/* DSP Page Register (DSPP) bitfields, */ 74/* defines 4 Mbyte page that BAR0 points to */ 75#define C6205_DSPP_MAP1 0x400 76 77/* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP. 78 * BAR1 maps to non-prefetchable 8 Mbyte memory block 79 * of DSP memory mapped registers (starting at 0x01800000). 80 * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this 81 * needs to be added to the BAR1 base address set in the PCI config reg 82 */ 83#define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L) 84#define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET) 85#define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4) 86#define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8) 87 88/* used to control LED (revA) and reset C6713 (revB) */ 89#define C6205_BAR0_TIMER1_CTL (0x01980000L) 90 91/* For first 6713 in CE1 space, using DA17,16,2 */ 92#define HPICL_ADDR 0x01400000L 93#define HPICH_ADDR 0x01400004L 94#define HPIAL_ADDR 0x01410000L 95#define HPIAH_ADDR 0x01410004L 96#define HPIDIL_ADDR 0x01420000L 97#define HPIDIH_ADDR 0x01420004L 98#define HPIDL_ADDR 0x01430000L 99#define HPIDH_ADDR 0x01430004L 100 101#define C6713_EMIF_GCTL 0x01800000 102#define C6713_EMIF_CE1 0x01800004 103#define C6713_EMIF_CE0 0x01800008 104#define C6713_EMIF_CE2 0x01800010 105#define C6713_EMIF_CE3 0x01800014 106#define C6713_EMIF_SDRAMCTL 0x01800018 107#define C6713_EMIF_SDRAMTIMING 0x0180001C 108#define C6713_EMIF_SDRAMEXT 0x01800020 109 110struct hpi_hw_obj { 111 /* PCI registers */ 112 __iomem u32 *prHSR; 113 __iomem u32 *prHDCR; 114 __iomem u32 *prDSPP; 115 116 u32 dsp_page; 117 118 struct consistent_dma_area h_locked_mem; 119 struct bus_master_interface *p_interface_buffer; 120 121 u16 flag_outstream_just_reset[HPI_MAX_STREAMS]; 122 /* a non-NULL handle means there is an HPI allocated buffer */ 123 struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS]; 124 struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS]; 125 /* non-zero size means a buffer exists, may be external */ 126 u32 instream_host_buffer_size[HPI_MAX_STREAMS]; 127 u32 outstream_host_buffer_size[HPI_MAX_STREAMS]; 128 129 struct consistent_dma_area h_control_cache; 130 struct hpi_control_cache *p_cache; 131}; 132 133/*****************************************************************************/ 134/* local prototypes */ 135 136#define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write) 137 138static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us); 139 140static void send_dsp_command(struct hpi_hw_obj *phw, int cmd); 141 142static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao, 143 u32 *pos_error_code); 144 145static u16 message_response_sequence(struct hpi_adapter_obj *pao, 146 struct hpi_message *phm, struct hpi_response *phr); 147 148static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, 149 struct hpi_response *phr); 150 151#define HPI6205_TIMEOUT 1000000 152 153static void subsys_create_adapter(struct hpi_message *phm, 154 struct hpi_response *phr); 155static void adapter_delete(struct hpi_adapter_obj *pao, 156 struct hpi_message *phm, struct hpi_response *phr); 157 158static u16 create_adapter_obj(struct hpi_adapter_obj *pao, 159 u32 *pos_error_code); 160 161static void delete_adapter_obj(struct hpi_adapter_obj *pao); 162 163static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao, 164 struct hpi_message *phm, struct hpi_response *phr); 165 166static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao, 167 struct hpi_message *phm, struct hpi_response *phr); 168 169static void outstream_host_buffer_free(struct hpi_adapter_obj *pao, 170 struct hpi_message *phm, struct hpi_response *phr); 171static void outstream_write(struct hpi_adapter_obj *pao, 172 struct hpi_message *phm, struct hpi_response *phr); 173 174static void outstream_get_info(struct hpi_adapter_obj *pao, 175 struct hpi_message *phm, struct hpi_response *phr); 176 177static void outstream_start(struct hpi_adapter_obj *pao, 178 struct hpi_message *phm, struct hpi_response *phr); 179 180static void outstream_open(struct hpi_adapter_obj *pao, 181 struct hpi_message *phm, struct hpi_response *phr); 182 183static void outstream_reset(struct hpi_adapter_obj *pao, 184 struct hpi_message *phm, struct hpi_response *phr); 185 186static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao, 187 struct hpi_message *phm, struct hpi_response *phr); 188 189static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao, 190 struct hpi_message *phm, struct hpi_response *phr); 191 192static void instream_host_buffer_free(struct hpi_adapter_obj *pao, 193 struct hpi_message *phm, struct hpi_response *phr); 194 195static void instream_read(struct hpi_adapter_obj *pao, 196 struct hpi_message *phm, struct hpi_response *phr); 197 198static void instream_get_info(struct hpi_adapter_obj *pao, 199 struct hpi_message *phm, struct hpi_response *phr); 200 201static void instream_start(struct hpi_adapter_obj *pao, 202 struct hpi_message *phm, struct hpi_response *phr); 203 204static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index, 205 u32 address); 206 207static void boot_loader_write_mem32(struct hpi_adapter_obj *pao, 208 int dsp_index, u32 address, u32 data); 209 210static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, 211 int dsp_index); 212 213static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index, 214 u32 address, u32 length); 215 216static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, 217 int dsp_index); 218 219static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao, 220 int dsp_index); 221 222static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index); 223 224/*****************************************************************************/ 225 226static void subsys_message(struct hpi_adapter_obj *pao, 227 struct hpi_message *phm, struct hpi_response *phr) 228{ 229 switch (phm->function) { 230 case HPI_SUBSYS_CREATE_ADAPTER: 231 subsys_create_adapter(phm, phr); 232 break; 233 default: 234 phr->error = HPI_ERROR_INVALID_FUNC; 235 break; 236 } 237} 238 239static void control_message(struct hpi_adapter_obj *pao, 240 struct hpi_message *phm, struct hpi_response *phr) 241{ 242 243 struct hpi_hw_obj *phw = pao->priv; 244 u16 pending_cache_error = 0; 245 246 switch (phm->function) { 247 case HPI_CONTROL_GET_STATE: 248 if (pao->has_control_cache) { 249 rmb(); /* make sure we see updates DMAed from DSP */ 250 if (hpi_check_control_cache(phw->p_cache, phm, phr)) { 251 break; 252 } else if (phm->u.c.attribute == HPI_METER_PEAK) { 253 pending_cache_error = 254 HPI_ERROR_CONTROL_CACHING; 255 } 256 } 257 hw_message(pao, phm, phr); 258 if (pending_cache_error && !phr->error) 259 phr->error = pending_cache_error; 260 break; 261 case HPI_CONTROL_GET_INFO: 262 hw_message(pao, phm, phr); 263 break; 264 case HPI_CONTROL_SET_STATE: 265 hw_message(pao, phm, phr); 266 if (pao->has_control_cache) 267 hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm, 268 phr); 269 break; 270 default: 271 phr->error = HPI_ERROR_INVALID_FUNC; 272 break; 273 } 274} 275 276static void adapter_message(struct hpi_adapter_obj *pao, 277 struct hpi_message *phm, struct hpi_response *phr) 278{ 279 switch (phm->function) { 280 case HPI_ADAPTER_DELETE: 281 adapter_delete(pao, phm, phr); 282 break; 283 284 default: 285 hw_message(pao, phm, phr); 286 break; 287 } 288} 289 290static void outstream_message(struct hpi_adapter_obj *pao, 291 struct hpi_message *phm, struct hpi_response *phr) 292{ 293 294 if (phm->obj_index >= HPI_MAX_STREAMS) { 295 phr->error = HPI_ERROR_INVALID_OBJ_INDEX; 296 HPI_DEBUG_LOG(WARNING, 297 "Message referencing invalid stream %d " 298 "on adapter index %d\n", phm->obj_index, 299 phm->adapter_index); 300 return; 301 } 302 303 switch (phm->function) { 304 case HPI_OSTREAM_WRITE: 305 outstream_write(pao, phm, phr); 306 break; 307 case HPI_OSTREAM_GET_INFO: 308 outstream_get_info(pao, phm, phr); 309 break; 310 case HPI_OSTREAM_HOSTBUFFER_ALLOC: 311 outstream_host_buffer_allocate(pao, phm, phr); 312 break; 313 case HPI_OSTREAM_HOSTBUFFER_GET_INFO: 314 outstream_host_buffer_get_info(pao, phm, phr); 315 break; 316 case HPI_OSTREAM_HOSTBUFFER_FREE: 317 outstream_host_buffer_free(pao, phm, phr); 318 break; 319 case HPI_OSTREAM_START: 320 outstream_start(pao, phm, phr); 321 break; 322 case HPI_OSTREAM_OPEN: 323 outstream_open(pao, phm, phr); 324 break; 325 case HPI_OSTREAM_RESET: 326 outstream_reset(pao, phm, phr); 327 break; 328 default: 329 hw_message(pao, phm, phr); 330 break; 331 } 332} 333 334static void instream_message(struct hpi_adapter_obj *pao, 335 struct hpi_message *phm, struct hpi_response *phr) 336{ 337 338 if (phm->obj_index >= HPI_MAX_STREAMS) { 339 phr->error = HPI_ERROR_INVALID_OBJ_INDEX; 340 HPI_DEBUG_LOG(WARNING, 341 "Message referencing invalid stream %d " 342 "on adapter index %d\n", phm->obj_index, 343 phm->adapter_index); 344 return; 345 } 346 347 switch (phm->function) { 348 case HPI_ISTREAM_READ: 349 instream_read(pao, phm, phr); 350 break; 351 case HPI_ISTREAM_GET_INFO: 352 instream_get_info(pao, phm, phr); 353 break; 354 case HPI_ISTREAM_HOSTBUFFER_ALLOC: 355 instream_host_buffer_allocate(pao, phm, phr); 356 break; 357 case HPI_ISTREAM_HOSTBUFFER_GET_INFO: 358 instream_host_buffer_get_info(pao, phm, phr); 359 break; 360 case HPI_ISTREAM_HOSTBUFFER_FREE: 361 instream_host_buffer_free(pao, phm, phr); 362 break; 363 case HPI_ISTREAM_START: 364 instream_start(pao, phm, phr); 365 break; 366 default: 367 hw_message(pao, phm, phr); 368 break; 369 } 370} 371 372/*****************************************************************************/ 373/** Entry point to this HPI backend 374 * All calls to the HPI start here 375 */ 376void _HPI_6205(struct hpi_adapter_obj *pao, struct hpi_message *phm, 377 struct hpi_response *phr) 378{ 379 if (pao && (pao->dsp_crashed >= 10) 380 && (phm->function != HPI_ADAPTER_DEBUG_READ)) { 381 /* allow last resort debug read even after crash */ 382 hpi_init_response(phr, phm->object, phm->function, 383 HPI_ERROR_DSP_HARDWARE); 384 HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n", phm->object, 385 phm->function); 386 return; 387 } 388 389 /* Init default response */ 390 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER) 391 phr->error = HPI_ERROR_PROCESSING_MESSAGE; 392 393 HPI_DEBUG_LOG(VERBOSE, "start of switch\n"); 394 switch (phm->type) { 395 case HPI_TYPE_MESSAGE: 396 switch (phm->object) { 397 case HPI_OBJ_SUBSYSTEM: 398 subsys_message(pao, phm, phr); 399 break; 400 401 case HPI_OBJ_ADAPTER: 402 adapter_message(pao, phm, phr); 403 break; 404 405 case HPI_OBJ_CONTROLEX: 406 case HPI_OBJ_CONTROL: 407 control_message(pao, phm, phr); 408 break; 409 410 case HPI_OBJ_OSTREAM: 411 outstream_message(pao, phm, phr); 412 break; 413 414 case HPI_OBJ_ISTREAM: 415 instream_message(pao, phm, phr); 416 break; 417 418 default: 419 hw_message(pao, phm, phr); 420 break; 421 } 422 break; 423 424 default: 425 phr->error = HPI_ERROR_INVALID_TYPE; 426 break; 427 } 428} 429 430void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) 431{ 432 struct hpi_adapter_obj *pao = NULL; 433 434 if (phm->object != HPI_OBJ_SUBSYSTEM) { 435 /* normal messages must have valid adapter index */ 436 pao = hpi_find_adapter(phm->adapter_index); 437 } else { 438 /* subsys messages don't address an adapter */ 439 _HPI_6205(NULL, phm, phr); 440 return; 441 } 442 443 if (pao) 444 _HPI_6205(pao, phm, phr); 445 else 446 hpi_init_response(phr, phm->object, phm->function, 447 HPI_ERROR_BAD_ADAPTER_NUMBER); 448} 449 450/*****************************************************************************/ 451/* SUBSYSTEM */ 452 453/** Create an adapter object and initialise it based on resource information 454 * passed in in the message 455 * *** NOTE - you cannot use this function AND the FindAdapters function at the 456 * same time, the application must use only one of them to get the adapters *** 457 */ 458static void subsys_create_adapter(struct hpi_message *phm, 459 struct hpi_response *phr) 460{ 461 /* create temp adapter obj, because we don't know what index yet */ 462 struct hpi_adapter_obj ao; 463 u32 os_error_code; 464 u16 err; 465 466 HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n"); 467 468 memset(&ao, 0, sizeof(ao)); 469 470 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL); 471 if (!ao.priv) { 472 HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n"); 473 phr->error = HPI_ERROR_MEMORY_ALLOC; 474 return; 475 } 476 477 ao.pci = *phm->u.s.resource.r.pci; 478 err = create_adapter_obj(&ao, &os_error_code); 479 if (err) { 480 delete_adapter_obj(&ao); 481 if (err >= HPI_ERROR_BACKEND_BASE) { 482 phr->error = HPI_ERROR_DSP_BOOTLOAD; 483 phr->specific_error = err; 484 } else { 485 phr->error = err; 486 } 487 phr->u.s.data = os_error_code; 488 return; 489 } 490 491 phr->u.s.adapter_type = ao.adapter_type; 492 phr->u.s.adapter_index = ao.index; 493 phr->error = 0; 494} 495 496/** delete an adapter - required by WDM driver */ 497static void adapter_delete(struct hpi_adapter_obj *pao, 498 struct hpi_message *phm, struct hpi_response *phr) 499{ 500 struct hpi_hw_obj *phw; 501 502 if (!pao) { 503 phr->error = HPI_ERROR_INVALID_OBJ_INDEX; 504 return; 505 } 506 phw = (struct hpi_hw_obj *)pao->priv; 507 /* reset adapter h/w */ 508 /* Reset C6713 #1 */ 509 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); 510 /* reset C6205 */ 511 iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR); 512 513 delete_adapter_obj(pao); 514 hpi_delete_adapter(pao); 515 phr->error = 0; 516} 517 518/** Create adapter object 519 allocate buffers, bootload DSPs, initialise control cache 520*/ 521static u16 create_adapter_obj(struct hpi_adapter_obj *pao, 522 u32 *pos_error_code) 523{ 524 struct hpi_hw_obj *phw = pao->priv; 525 struct bus_master_interface *interface; 526 u32 phys_addr; 527 int i; 528 u16 err; 529 530 /* init error reporting */ 531 pao->dsp_crashed = 0; 532 533 for (i = 0; i < HPI_MAX_STREAMS; i++) 534 phw->flag_outstream_just_reset[i] = 1; 535 536 /* The C6205 memory area 1 is 8Mbyte window into DSP registers */ 537 phw->prHSR = 538 pao->pci.ap_mem_base[1] + 539 C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]); 540 phw->prHDCR = 541 pao->pci.ap_mem_base[1] + 542 C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]); 543 phw->prDSPP = 544 pao->pci.ap_mem_base[1] + 545 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]); 546 547 pao->has_control_cache = 0; 548 549 if (hpios_locked_mem_alloc(&phw->h_locked_mem, 550 sizeof(struct bus_master_interface), 551 pao->pci.pci_dev)) 552 phw->p_interface_buffer = NULL; 553 else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem, 554 (void *)&phw->p_interface_buffer)) 555 phw->p_interface_buffer = NULL; 556 557 HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n", 558 phw->p_interface_buffer); 559 560 if (phw->p_interface_buffer) { 561 memset((void *)phw->p_interface_buffer, 0, 562 sizeof(struct bus_master_interface)); 563 phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN; 564 } 565 566 err = adapter_boot_load_dsp(pao, pos_error_code); 567 if (err) { 568 HPI_DEBUG_LOG(ERROR, "DSP code load failed\n"); 569 /* no need to clean up as SubSysCreateAdapter */ 570 /* calls DeleteAdapter on error. */ 571 return err; 572 } 573 HPI_DEBUG_LOG(INFO, "load DSP code OK\n"); 574 575 /* allow boot load even if mem alloc wont work */ 576 if (!phw->p_interface_buffer) 577 return HPI_ERROR_MEMORY_ALLOC; 578 579 interface = phw->p_interface_buffer; 580 581 /* make sure the DSP has started ok */ 582 if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) { 583 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n"); 584 return HPI6205_ERROR_6205_INIT_FAILED; 585 } 586 /* Note that *pao, *phw are zeroed after allocation, 587 * so pointers and flags are NULL by default. 588 * Allocate bus mastering control cache buffer and tell the DSP about it 589 */ 590 if (interface->control_cache.number_of_controls) { 591 u8 *p_control_cache_virtual; 592 593 err = hpios_locked_mem_alloc(&phw->h_control_cache, 594 interface->control_cache.size_in_bytes, 595 pao->pci.pci_dev); 596 if (!err) 597 err = hpios_locked_mem_get_virt_addr(&phw-> 598 h_control_cache, 599 (void *)&p_control_cache_virtual); 600 if (!err) { 601 memset(p_control_cache_virtual, 0, 602 interface->control_cache.size_in_bytes); 603 604 phw->p_cache = 605 hpi_alloc_control_cache(interface-> 606 control_cache.number_of_controls, 607 interface->control_cache.size_in_bytes, 608 p_control_cache_virtual); 609 610 if (!phw->p_cache) 611 err = HPI_ERROR_MEMORY_ALLOC; 612 } 613 if (!err) { 614 err = hpios_locked_mem_get_phys_addr(&phw-> 615 h_control_cache, &phys_addr); 616 interface->control_cache.physical_address32 = 617 phys_addr; 618 } 619 620 if (!err) 621 pao->has_control_cache = 1; 622 else { 623 if (hpios_locked_mem_valid(&phw->h_control_cache)) 624 hpios_locked_mem_free(&phw->h_control_cache); 625 pao->has_control_cache = 0; 626 } 627 } 628 send_dsp_command(phw, H620_HIF_IDLE); 629 630 { 631 struct hpi_message hm; 632 struct hpi_response hr; 633 u32 max_streams; 634 635 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n"); 636 memset(&hm, 0, sizeof(hm)); 637 hm.type = HPI_TYPE_MESSAGE; 638 hm.size = sizeof(hm); 639 hm.object = HPI_OBJ_ADAPTER; 640 hm.function = HPI_ADAPTER_GET_INFO; 641 hm.adapter_index = 0; 642 memset(&hr, 0, sizeof(hr)); 643 hr.size = sizeof(hr); 644 645 err = message_response_sequence(pao, &hm, &hr); 646 if (err) { 647 HPI_DEBUG_LOG(ERROR, "message transport error %d\n", 648 err); 649 return err; 650 } 651 if (hr.error) 652 return hr.error; 653 654 pao->adapter_type = hr.u.ax.info.adapter_type; 655 pao->index = hr.u.ax.info.adapter_index; 656 657 max_streams = 658 hr.u.ax.info.num_outstreams + 659 hr.u.ax.info.num_instreams; 660 661 hpios_locked_mem_prepare((max_streams * 6) / 10, max_streams, 662 65536, pao->pci.pci_dev); 663 664 HPI_DEBUG_LOG(VERBOSE, 665 "got adapter info type %x index %d serial %d\n", 666 hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index, 667 hr.u.ax.info.serial_number); 668 } 669 670 pao->open = 0; /* upon creation the adapter is closed */ 671 672 if (phw->p_cache) 673 phw->p_cache->adap_idx = pao->index; 674 675 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n"); 676 677 return hpi_add_adapter(pao); 678} 679 680/** Free memory areas allocated by adapter 681 * this routine is called from AdapterDelete, 682 * and SubSysCreateAdapter if duplicate index 683*/ 684static void delete_adapter_obj(struct hpi_adapter_obj *pao) 685{ 686 struct hpi_hw_obj *phw = pao->priv; 687 int i; 688 689 if (hpios_locked_mem_valid(&phw->h_control_cache)) { 690 hpios_locked_mem_free(&phw->h_control_cache); 691 hpi_free_control_cache(phw->p_cache); 692 } 693 694 if (hpios_locked_mem_valid(&phw->h_locked_mem)) { 695 hpios_locked_mem_free(&phw->h_locked_mem); 696 phw->p_interface_buffer = NULL; 697 } 698 699 for (i = 0; i < HPI_MAX_STREAMS; i++) 700 if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) { 701 hpios_locked_mem_free(&phw->instream_host_buffers[i]); 702 /*?phw->InStreamHostBuffers[i] = NULL; */ 703 phw->instream_host_buffer_size[i] = 0; 704 } 705 706 for (i = 0; i < HPI_MAX_STREAMS; i++) 707 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) { 708 hpios_locked_mem_free(&phw->outstream_host_buffers 709 [i]); 710 phw->outstream_host_buffer_size[i] = 0; 711 } 712 713 hpios_locked_mem_unprepare(pao->pci.pci_dev); 714 715 kfree(phw); 716} 717 718/*****************************************************************************/ 719/* Adapter functions */ 720 721/*****************************************************************************/ 722/* OutStream Host buffer functions */ 723 724/** Allocate or attach buffer for busmastering 725*/ 726static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao, 727 struct hpi_message *phm, struct hpi_response *phr) 728{ 729 u16 err = 0; 730 u32 command = phm->u.d.u.buffer.command; 731 struct hpi_hw_obj *phw = pao->priv; 732 struct bus_master_interface *interface = phw->p_interface_buffer; 733 734 hpi_init_response(phr, phm->object, phm->function, 0); 735 736 if (command == HPI_BUFFER_CMD_EXTERNAL 737 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { 738 /* ALLOC phase, allocate a buffer with power of 2 size, 739 get its bus address for PCI bus mastering 740 */ 741 phm->u.d.u.buffer.buffer_size = 742 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); 743 /* return old size and allocated size, 744 so caller can detect change */ 745 phr->u.d.u.stream_info.data_available = 746 phw->outstream_host_buffer_size[phm->obj_index]; 747 phr->u.d.u.stream_info.buffer_size = 748 phm->u.d.u.buffer.buffer_size; 749 750 if (phw->outstream_host_buffer_size[phm->obj_index] == 751 phm->u.d.u.buffer.buffer_size) { 752 /* Same size, no action required */ 753 return; 754 } 755 756 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> 757 obj_index])) 758 hpios_locked_mem_free(&phw->outstream_host_buffers 759 [phm->obj_index]); 760 761 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers 762 [phm->obj_index], phm->u.d.u.buffer.buffer_size, 763 pao->pci.pci_dev); 764 765 if (err) { 766 phr->error = HPI_ERROR_INVALID_DATASIZE; 767 phw->outstream_host_buffer_size[phm->obj_index] = 0; 768 return; 769 } 770 771 err = hpios_locked_mem_get_phys_addr 772 (&phw->outstream_host_buffers[phm->obj_index], 773 &phm->u.d.u.buffer.pci_address); 774 /* get the phys addr into msg for single call alloc caller 775 * needs to do this for split alloc (or use the same message) 776 * return the phy address for split alloc in the respose too 777 */ 778 phr->u.d.u.stream_info.auxiliary_data_available = 779 phm->u.d.u.buffer.pci_address; 780 781 if (err) { 782 hpios_locked_mem_free(&phw->outstream_host_buffers 783 [phm->obj_index]); 784 phw->outstream_host_buffer_size[phm->obj_index] = 0; 785 phr->error = HPI_ERROR_MEMORY_ALLOC; 786 return; 787 } 788 } 789 790 if (command == HPI_BUFFER_CMD_EXTERNAL 791 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { 792 /* GRANT phase. Set up the BBM status, tell the DSP about 793 the buffer so it can start using BBM. 794 */ 795 struct hpi_hostbuffer_status *status; 796 797 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer. 798 buffer_size - 1)) { 799 HPI_DEBUG_LOG(ERROR, 800 "Buffer size must be 2^N not %d\n", 801 phm->u.d.u.buffer.buffer_size); 802 phr->error = HPI_ERROR_INVALID_DATASIZE; 803 return; 804 } 805 phw->outstream_host_buffer_size[phm->obj_index] = 806 phm->u.d.u.buffer.buffer_size; 807 status = &interface->outstream_host_buffer_status[phm-> 808 obj_index]; 809 status->samples_processed = 0; 810 status->stream_state = HPI_STATE_STOPPED; 811 status->dSP_index = 0; 812 status->host_index = status->dSP_index; 813 status->size_in_bytes = phm->u.d.u.buffer.buffer_size; 814 status->auxiliary_data_available = 0; 815 816 hw_message(pao, phm, phr); 817 818 if (phr->error 819 && hpios_locked_mem_valid(&phw-> 820 outstream_host_buffers[phm->obj_index])) { 821 hpios_locked_mem_free(&phw->outstream_host_buffers 822 [phm->obj_index]); 823 phw->outstream_host_buffer_size[phm->obj_index] = 0; 824 } 825 } 826} 827 828static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao, 829 struct hpi_message *phm, struct hpi_response *phr) 830{ 831 struct hpi_hw_obj *phw = pao->priv; 832 struct bus_master_interface *interface = phw->p_interface_buffer; 833 struct hpi_hostbuffer_status *status; 834 u8 *p_bbm_data; 835 836 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> 837 obj_index])) { 838 if (hpios_locked_mem_get_virt_addr(&phw-> 839 outstream_host_buffers[phm->obj_index], 840 (void *)&p_bbm_data)) { 841 phr->error = HPI_ERROR_INVALID_OPERATION; 842 return; 843 } 844 status = &interface->outstream_host_buffer_status[phm-> 845 obj_index]; 846 hpi_init_response(phr, HPI_OBJ_OSTREAM, 847 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0); 848 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data; 849 phr->u.d.u.hostbuffer_info.p_status = status; 850 } else { 851 hpi_init_response(phr, HPI_OBJ_OSTREAM, 852 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 853 HPI_ERROR_INVALID_OPERATION); 854 } 855} 856 857static void outstream_host_buffer_free(struct hpi_adapter_obj *pao, 858 struct hpi_message *phm, struct hpi_response *phr) 859{ 860 struct hpi_hw_obj *phw = pao->priv; 861 u32 command = phm->u.d.u.buffer.command; 862 863 if (phw->outstream_host_buffer_size[phm->obj_index]) { 864 if (command == HPI_BUFFER_CMD_EXTERNAL 865 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) { 866 phw->outstream_host_buffer_size[phm->obj_index] = 0; 867 hw_message(pao, phm, phr); 868 /* Tell adapter to stop using the host buffer. */ 869 } 870 if (command == HPI_BUFFER_CMD_EXTERNAL 871 || command == HPI_BUFFER_CMD_INTERNAL_FREE) 872 hpios_locked_mem_free(&phw->outstream_host_buffers 873 [phm->obj_index]); 874 } 875 /* Should HPI_ERROR_INVALID_OPERATION be returned 876 if no host buffer is allocated? */ 877 else 878 hpi_init_response(phr, HPI_OBJ_OSTREAM, 879 HPI_OSTREAM_HOSTBUFFER_FREE, 0); 880 881} 882 883static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status) 884{ 885 return status->size_in_bytes - (status->host_index - 886 status->dSP_index); 887} 888 889static void outstream_write(struct hpi_adapter_obj *pao, 890 struct hpi_message *phm, struct hpi_response *phr) 891{ 892 struct hpi_hw_obj *phw = pao->priv; 893 struct bus_master_interface *interface = phw->p_interface_buffer; 894 struct hpi_hostbuffer_status *status; 895 u32 space_available; 896 897 if (!phw->outstream_host_buffer_size[phm->obj_index]) { 898 /* there is no BBM buffer, write via message */ 899 hw_message(pao, phm, phr); 900 return; 901 } 902 903 hpi_init_response(phr, phm->object, phm->function, 0); 904 status = &interface->outstream_host_buffer_status[phm->obj_index]; 905 906 space_available = outstream_get_space_available(status); 907 if (space_available < phm->u.d.u.data.data_size) { 908 phr->error = HPI_ERROR_INVALID_DATASIZE; 909 return; 910 } 911 912 /* HostBuffers is used to indicate host buffer is internally allocated. 913 otherwise, assumed external, data written externally */ 914 if (phm->u.d.u.data.pb_data 915 && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm-> 916 obj_index])) { 917 u8 *p_bbm_data; 918 u32 l_first_write; 919 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data; 920 921 if (hpios_locked_mem_get_virt_addr(&phw-> 922 outstream_host_buffers[phm->obj_index], 923 (void *)&p_bbm_data)) { 924 phr->error = HPI_ERROR_INVALID_OPERATION; 925 return; 926 } 927 928 /* either all data, 929 or enough to fit from current to end of BBM buffer */ 930 l_first_write = 931 min(phm->u.d.u.data.data_size, 932 status->size_in_bytes - 933 (status->host_index & (status->size_in_bytes - 1))); 934 935 memcpy(p_bbm_data + 936 (status->host_index & (status->size_in_bytes - 1)), 937 p_app_data, l_first_write); 938 /* remaining data if any */ 939 memcpy(p_bbm_data, p_app_data + l_first_write, 940 phm->u.d.u.data.data_size - l_first_write); 941 } 942 943 /* 944 * This version relies on the DSP code triggering an OStream buffer 945 * update immediately following a SET_FORMAT call. The host has 946 * already written data into the BBM buffer, but the DSP won't know 947 * about it until dwHostIndex is adjusted. 948 */ 949 if (phw->flag_outstream_just_reset[phm->obj_index]) { 950 /* Format can only change after reset. Must tell DSP. */ 951 u16 function = phm->function; 952 phw->flag_outstream_just_reset[phm->obj_index] = 0; 953 phm->function = HPI_OSTREAM_SET_FORMAT; 954 hw_message(pao, phm, phr); /* send the format to the DSP */ 955 phm->function = function; 956 if (phr->error) 957 return; 958 } 959 960 status->host_index += phm->u.d.u.data.data_size; 961} 962 963static void outstream_get_info(struct hpi_adapter_obj *pao, 964 struct hpi_message *phm, struct hpi_response *phr) 965{ 966 struct hpi_hw_obj *phw = pao->priv; 967 struct bus_master_interface *interface = phw->p_interface_buffer; 968 struct hpi_hostbuffer_status *status; 969 970 if (!phw->outstream_host_buffer_size[phm->obj_index]) { 971 hw_message(pao, phm, phr); 972 return; 973 } 974 975 hpi_init_response(phr, phm->object, phm->function, 0); 976 977 status = &interface->outstream_host_buffer_status[phm->obj_index]; 978 979 phr->u.d.u.stream_info.state = (u16)status->stream_state; 980 phr->u.d.u.stream_info.samples_transferred = 981 status->samples_processed; 982 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes; 983 phr->u.d.u.stream_info.data_available = 984 status->size_in_bytes - outstream_get_space_available(status); 985 phr->u.d.u.stream_info.auxiliary_data_available = 986 status->auxiliary_data_available; 987} 988 989static void outstream_start(struct hpi_adapter_obj *pao, 990 struct hpi_message *phm, struct hpi_response *phr) 991{ 992 hw_message(pao, phm, phr); 993} 994 995static void outstream_reset(struct hpi_adapter_obj *pao, 996 struct hpi_message *phm, struct hpi_response *phr) 997{ 998 struct hpi_hw_obj *phw = pao->priv; 999 phw->flag_outstream_just_reset[phm->obj_index] = 1; 1000 hw_message(pao, phm, phr); 1001} 1002 1003static void outstream_open(struct hpi_adapter_obj *pao, 1004 struct hpi_message *phm, struct hpi_response *phr) 1005{ 1006 outstream_reset(pao, phm, phr); 1007} 1008 1009/*****************************************************************************/ 1010/* InStream Host buffer functions */ 1011 1012static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao, 1013 struct hpi_message *phm, struct hpi_response *phr) 1014{ 1015 u16 err = 0; 1016 u32 command = phm->u.d.u.buffer.command; 1017 struct hpi_hw_obj *phw = pao->priv; 1018 struct bus_master_interface *interface = phw->p_interface_buffer; 1019 1020 hpi_init_response(phr, phm->object, phm->function, 0); 1021 1022 if (command == HPI_BUFFER_CMD_EXTERNAL 1023 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { 1024 1025 phm->u.d.u.buffer.buffer_size = 1026 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); 1027 phr->u.d.u.stream_info.data_available = 1028 phw->instream_host_buffer_size[phm->obj_index]; 1029 phr->u.d.u.stream_info.buffer_size = 1030 phm->u.d.u.buffer.buffer_size; 1031 1032 if (phw->instream_host_buffer_size[phm->obj_index] == 1033 phm->u.d.u.buffer.buffer_size) { 1034 /* Same size, no action required */ 1035 return; 1036 } 1037 1038 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> 1039 obj_index])) 1040 hpios_locked_mem_free(&phw->instream_host_buffers 1041 [phm->obj_index]); 1042 1043 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm-> 1044 obj_index], phm->u.d.u.buffer.buffer_size, 1045 pao->pci.pci_dev); 1046 1047 if (err) { 1048 phr->error = HPI_ERROR_INVALID_DATASIZE; 1049 phw->instream_host_buffer_size[phm->obj_index] = 0; 1050 return; 1051 } 1052 1053 err = hpios_locked_mem_get_phys_addr 1054 (&phw->instream_host_buffers[phm->obj_index], 1055 &phm->u.d.u.buffer.pci_address); 1056 /* get the phys addr into msg for single call alloc. Caller 1057 needs to do this for split alloc so return the phy address */ 1058 phr->u.d.u.stream_info.auxiliary_data_available = 1059 phm->u.d.u.buffer.pci_address; 1060 if (err) { 1061 hpios_locked_mem_free(&phw->instream_host_buffers 1062 [phm->obj_index]); 1063 phw->instream_host_buffer_size[phm->obj_index] = 0; 1064 phr->error = HPI_ERROR_MEMORY_ALLOC; 1065 return; 1066 } 1067 } 1068 1069 if (command == HPI_BUFFER_CMD_EXTERNAL 1070 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { 1071 struct hpi_hostbuffer_status *status; 1072 1073 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer. 1074 buffer_size - 1)) { 1075 HPI_DEBUG_LOG(ERROR, 1076 "Buffer size must be 2^N not %d\n", 1077 phm->u.d.u.buffer.buffer_size); 1078 phr->error = HPI_ERROR_INVALID_DATASIZE; 1079 return; 1080 } 1081 1082 phw->instream_host_buffer_size[phm->obj_index] = 1083 phm->u.d.u.buffer.buffer_size; 1084 status = &interface->instream_host_buffer_status[phm-> 1085 obj_index]; 1086 status->samples_processed = 0; 1087 status->stream_state = HPI_STATE_STOPPED; 1088 status->dSP_index = 0; 1089 status->host_index = status->dSP_index; 1090 status->size_in_bytes = phm->u.d.u.buffer.buffer_size; 1091 status->auxiliary_data_available = 0; 1092 1093 hw_message(pao, phm, phr); 1094 1095 if (phr->error 1096 && hpios_locked_mem_valid(&phw-> 1097 instream_host_buffers[phm->obj_index])) { 1098 hpios_locked_mem_free(&phw->instream_host_buffers 1099 [phm->obj_index]); 1100 phw->instream_host_buffer_size[phm->obj_index] = 0; 1101 } 1102 } 1103} 1104 1105static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao, 1106 struct hpi_message *phm, struct hpi_response *phr) 1107{ 1108 struct hpi_hw_obj *phw = pao->priv; 1109 struct bus_master_interface *interface = phw->p_interface_buffer; 1110 struct hpi_hostbuffer_status *status; 1111 u8 *p_bbm_data; 1112 1113 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> 1114 obj_index])) { 1115 if (hpios_locked_mem_get_virt_addr(&phw-> 1116 instream_host_buffers[phm->obj_index], 1117 (void *)&p_bbm_data)) { 1118 phr->error = HPI_ERROR_INVALID_OPERATION; 1119 return; 1120 } 1121 status = &interface->instream_host_buffer_status[phm-> 1122 obj_index]; 1123 hpi_init_response(phr, HPI_OBJ_ISTREAM, 1124 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0); 1125 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data; 1126 phr->u.d.u.hostbuffer_info.p_status = status; 1127 } else { 1128 hpi_init_response(phr, HPI_OBJ_ISTREAM, 1129 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 1130 HPI_ERROR_INVALID_OPERATION); 1131 } 1132} 1133 1134static void instream_host_buffer_free(struct hpi_adapter_obj *pao, 1135 struct hpi_message *phm, struct hpi_response *phr) 1136{ 1137 struct hpi_hw_obj *phw = pao->priv; 1138 u32 command = phm->u.d.u.buffer.command; 1139 1140 if (phw->instream_host_buffer_size[phm->obj_index]) { 1141 if (command == HPI_BUFFER_CMD_EXTERNAL 1142 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) { 1143 phw->instream_host_buffer_size[phm->obj_index] = 0; 1144 hw_message(pao, phm, phr); 1145 } 1146 1147 if (command == HPI_BUFFER_CMD_EXTERNAL 1148 || command == HPI_BUFFER_CMD_INTERNAL_FREE) 1149 hpios_locked_mem_free(&phw->instream_host_buffers 1150 [phm->obj_index]); 1151 1152 } else { 1153 /* Should HPI_ERROR_INVALID_OPERATION be returned 1154 if no host buffer is allocated? */ 1155 hpi_init_response(phr, HPI_OBJ_ISTREAM, 1156 HPI_ISTREAM_HOSTBUFFER_FREE, 0); 1157 1158 } 1159 1160} 1161 1162static void instream_start(struct hpi_adapter_obj *pao, 1163 struct hpi_message *phm, struct hpi_response *phr) 1164{ 1165 hw_message(pao, phm, phr); 1166} 1167 1168static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status) 1169{ 1170 return status->dSP_index - status->host_index; 1171} 1172 1173static void instream_read(struct hpi_adapter_obj *pao, 1174 struct hpi_message *phm, struct hpi_response *phr) 1175{ 1176 struct hpi_hw_obj *phw = pao->priv; 1177 struct bus_master_interface *interface = phw->p_interface_buffer; 1178 struct hpi_hostbuffer_status *status; 1179 u32 data_available; 1180 u8 *p_bbm_data; 1181 u32 l_first_read; 1182 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data; 1183 1184 if (!phw->instream_host_buffer_size[phm->obj_index]) { 1185 hw_message(pao, phm, phr); 1186 return; 1187 } 1188 hpi_init_response(phr, phm->object, phm->function, 0); 1189 1190 status = &interface->instream_host_buffer_status[phm->obj_index]; 1191 data_available = instream_get_bytes_available(status); 1192 if (data_available < phm->u.d.u.data.data_size) { 1193 phr->error = HPI_ERROR_INVALID_DATASIZE; 1194 return; 1195 } 1196 1197 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm-> 1198 obj_index])) { 1199 if (hpios_locked_mem_get_virt_addr(&phw-> 1200 instream_host_buffers[phm->obj_index], 1201 (void *)&p_bbm_data)) { 1202 phr->error = HPI_ERROR_INVALID_OPERATION; 1203 return; 1204 } 1205 1206 /* either all data, 1207 or enough to fit from current to end of BBM buffer */ 1208 l_first_read = 1209 min(phm->u.d.u.data.data_size, 1210 status->size_in_bytes - 1211 (status->host_index & (status->size_in_bytes - 1))); 1212 1213 memcpy(p_app_data, 1214 p_bbm_data + 1215 (status->host_index & (status->size_in_bytes - 1)), 1216 l_first_read); 1217 /* remaining data if any */ 1218 memcpy(p_app_data + l_first_read, p_bbm_data, 1219 phm->u.d.u.data.data_size - l_first_read); 1220 } 1221 status->host_index += phm->u.d.u.data.data_size; 1222} 1223 1224static void instream_get_info(struct hpi_adapter_obj *pao, 1225 struct hpi_message *phm, struct hpi_response *phr) 1226{ 1227 struct hpi_hw_obj *phw = pao->priv; 1228 struct bus_master_interface *interface = phw->p_interface_buffer; 1229 struct hpi_hostbuffer_status *status; 1230 if (!phw->instream_host_buffer_size[phm->obj_index]) { 1231 hw_message(pao, phm, phr); 1232 return; 1233 } 1234 1235 status = &interface->instream_host_buffer_status[phm->obj_index]; 1236 1237 hpi_init_response(phr, phm->object, phm->function, 0); 1238 1239 phr->u.d.u.stream_info.state = (u16)status->stream_state; 1240 phr->u.d.u.stream_info.samples_transferred = 1241 status->samples_processed; 1242 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes; 1243 phr->u.d.u.stream_info.data_available = 1244 instream_get_bytes_available(status); 1245 phr->u.d.u.stream_info.auxiliary_data_available = 1246 status->auxiliary_data_available; 1247} 1248 1249/*****************************************************************************/ 1250/* LOW-LEVEL */ 1251#define HPI6205_MAX_FILES_TO_LOAD 2 1252 1253static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao, 1254 u32 *pos_error_code) 1255{ 1256 struct hpi_hw_obj *phw = pao->priv; 1257 struct dsp_code dsp_code; 1258 u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD]; 1259 u32 temp; 1260 int dsp = 0, i = 0; 1261 u16 err = 0; 1262 1263 boot_code_id[0] = HPI_ADAPTER_ASI(0x6205); 1264 1265 boot_code_id[1] = pao->pci.pci_dev->subsystem_device; 1266 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(boot_code_id[1]); 1267 1268 /* fix up cases where bootcode id[1] != subsys id */ 1269 switch (boot_code_id[1]) { 1270 case HPI_ADAPTER_FAMILY_ASI(0x5000): 1271 boot_code_id[0] = boot_code_id[1]; 1272 boot_code_id[1] = 0; 1273 break; 1274 case HPI_ADAPTER_FAMILY_ASI(0x5300): 1275 case HPI_ADAPTER_FAMILY_ASI(0x5400): 1276 case HPI_ADAPTER_FAMILY_ASI(0x6300): 1277 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400); 1278 break; 1279 case HPI_ADAPTER_FAMILY_ASI(0x5500): 1280 case HPI_ADAPTER_FAMILY_ASI(0x5600): 1281 case HPI_ADAPTER_FAMILY_ASI(0x6500): 1282 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600); 1283 break; 1284 case HPI_ADAPTER_FAMILY_ASI(0x8800): 1285 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900); 1286 break; 1287 default: 1288 break; 1289 } 1290 1291 /* reset DSP by writing a 1 to the WARMRESET bit */ 1292 temp = C6205_HDCR_WARMRESET; 1293 iowrite32(temp, phw->prHDCR); 1294 hpios_delay_micro_seconds(1000); 1295 1296 /* check that PCI i/f was configured by EEPROM */ 1297 temp = ioread32(phw->prHSR); 1298 if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) != 1299 C6205_HSR_EEREAD) 1300 return HPI6205_ERROR_6205_EEPROM; 1301 temp |= 0x04; 1302 /* disable PINTA interrupt */ 1303 iowrite32(temp, phw->prHSR); 1304 1305 /* check control register reports PCI boot mode */ 1306 temp = ioread32(phw->prHDCR); 1307 if (!(temp & C6205_HDCR_PCIBOOT)) 1308 return HPI6205_ERROR_6205_REG; 1309 1310 /* try writing a few numbers to the DSP page register */ 1311 /* and reading them back. */ 1312 temp = 3; 1313 iowrite32(temp, phw->prDSPP); 1314 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1315 return HPI6205_ERROR_6205_DSPPAGE; 1316 temp = 2; 1317 iowrite32(temp, phw->prDSPP); 1318 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1319 return HPI6205_ERROR_6205_DSPPAGE; 1320 temp = 1; 1321 iowrite32(temp, phw->prDSPP); 1322 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1323 return HPI6205_ERROR_6205_DSPPAGE; 1324 /* reset DSP page to the correct number */ 1325 temp = 0; 1326 iowrite32(temp, phw->prDSPP); 1327 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) 1328 return HPI6205_ERROR_6205_DSPPAGE; 1329 phw->dsp_page = 0; 1330 1331 /* release 6713 from reset before 6205 is bootloaded. 1332 This ensures that the EMIF is inactive, 1333 and the 6713 HPI gets the correct bootmode etc 1334 */ 1335 if (boot_code_id[1] != 0) { 1336 /* DSP 1 is a C6713 */ 1337 /* CLKX0 <- '1' release the C6205 bootmode pulldowns */ 1338 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002202); 1339 hpios_delay_micro_seconds(100); 1340 /* Reset the 6713 #1 - revB */ 1341 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); 1342 1343 /* dummy read every 4 words for 6205 advisory 1.4.4 */ 1344 boot_loader_read_mem32(pao, 0, 0); 1345 1346 hpios_delay_micro_seconds(100); 1347 /* Release C6713 from reset - revB */ 1348 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4); 1349 hpios_delay_micro_seconds(100); 1350 } 1351 1352 for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) { 1353 /* is there a DSP to load? */ 1354 if (boot_code_id[dsp] == 0) 1355 continue; 1356 1357 err = boot_loader_config_emif(pao, dsp); 1358 if (err) 1359 return err; 1360 1361 err = boot_loader_test_internal_memory(pao, dsp); 1362 if (err) 1363 return err; 1364 1365 err = boot_loader_test_external_memory(pao, dsp); 1366 if (err) 1367 return err; 1368 1369 err = boot_loader_test_pld(pao, dsp); 1370 if (err) 1371 return err; 1372 1373 /* write the DSP code down into the DSPs memory */ 1374 dsp_code.ps_dev = pao->pci.pci_dev; 1375 err = hpi_dsp_code_open(boot_code_id[dsp], &dsp_code, 1376 pos_error_code); 1377 if (err) 1378 return err; 1379 1380 while (1) { 1381 u32 length; 1382 u32 address; 1383 u32 type; 1384 u32 *pcode; 1385 1386 err = hpi_dsp_code_read_word(&dsp_code, &length); 1387 if (err) 1388 break; 1389 if (length == 0xFFFFFFFF) 1390 break; /* end of code */ 1391 1392 err = hpi_dsp_code_read_word(&dsp_code, &address); 1393 if (err) 1394 break; 1395 err = hpi_dsp_code_read_word(&dsp_code, &type); 1396 if (err) 1397 break; 1398 err = hpi_dsp_code_read_block(length, &dsp_code, 1399 &pcode); 1400 if (err) 1401 break; 1402 for (i = 0; i < (int)length; i++) { 1403 boot_loader_write_mem32(pao, dsp, address, 1404 *pcode); 1405 /* dummy read every 4 words */ 1406 /* for 6205 advisory 1.4.4 */ 1407 if (i % 4 == 0) 1408 boot_loader_read_mem32(pao, dsp, 1409 address); 1410 pcode++; 1411 address += 4; 1412 } 1413 1414 } 1415 if (err) { 1416 hpi_dsp_code_close(&dsp_code); 1417 return err; 1418 } 1419 1420 /* verify code */ 1421 hpi_dsp_code_rewind(&dsp_code); 1422 while (1) { 1423 u32 length = 0; 1424 u32 address = 0; 1425 u32 type = 0; 1426 u32 *pcode = NULL; 1427 u32 data = 0; 1428 1429 hpi_dsp_code_read_word(&dsp_code, &length); 1430 if (length == 0xFFFFFFFF) 1431 break; /* end of code */ 1432 1433 hpi_dsp_code_read_word(&dsp_code, &address); 1434 hpi_dsp_code_read_word(&dsp_code, &type); 1435 hpi_dsp_code_read_block(length, &dsp_code, &pcode); 1436 1437 for (i = 0; i < (int)length; i++) { 1438 data = boot_loader_read_mem32(pao, dsp, 1439 address); 1440 if (data != *pcode) { 1441 err = 0; 1442 break; 1443 } 1444 pcode++; 1445 address += 4; 1446 } 1447 if (err) 1448 break; 1449 } 1450 hpi_dsp_code_close(&dsp_code); 1451 if (err) 1452 return err; 1453 } 1454 1455 /* After bootloading all DSPs, start DSP0 running 1456 * The DSP0 code will handle starting and synchronizing with its slaves 1457 */ 1458 if (phw->p_interface_buffer) { 1459 /* we need to tell the card the physical PCI address */ 1460 u32 physicalPC_iaddress; 1461 struct bus_master_interface *interface = 1462 phw->p_interface_buffer; 1463 u32 host_mailbox_address_on_dsp; 1464 u32 physicalPC_iaddress_verify = 0; 1465 int time_out = 10; 1466 /* set ack so we know when DSP is ready to go */ 1467 /* (dwDspAck will be changed to HIF_RESET) */ 1468 interface->dsp_ack = H620_HIF_UNKNOWN; 1469 wmb(); /* ensure ack is written before dsp writes back */ 1470 1471 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem, 1472 &physicalPC_iaddress); 1473 1474 /* locate the host mailbox on the DSP. */ 1475 host_mailbox_address_on_dsp = 0x80000000; 1476 while ((physicalPC_iaddress != physicalPC_iaddress_verify) 1477 && time_out--) { 1478 boot_loader_write_mem32(pao, 0, 1479 host_mailbox_address_on_dsp, 1480 physicalPC_iaddress); 1481 physicalPC_iaddress_verify = 1482 boot_loader_read_mem32(pao, 0, 1483 host_mailbox_address_on_dsp); 1484 } 1485 } 1486 HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n"); 1487 /* enable interrupts */ 1488 temp = ioread32(phw->prHSR); 1489 temp &= ~(u32)C6205_HSR_INTAM; 1490 iowrite32(temp, phw->prHSR); 1491 1492 /* start code running... */ 1493 temp = ioread32(phw->prHDCR); 1494 temp |= (u32)C6205_HDCR_DSPINT; 1495 iowrite32(temp, phw->prHDCR); 1496 1497 /* give the DSP 10ms to start up */ 1498 hpios_delay_micro_seconds(10000); 1499 return err; 1500 1501} 1502 1503/*****************************************************************************/ 1504/* Bootloader utility functions */ 1505 1506static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index, 1507 u32 address) 1508{ 1509 struct hpi_hw_obj *phw = pao->priv; 1510 u32 data = 0; 1511 __iomem u32 *p_data; 1512 1513 if (dsp_index == 0) { 1514 /* DSP 0 is always C6205 */ 1515 if ((address >= 0x01800000) & (address < 0x02000000)) { 1516 /* BAR1 register access */ 1517 p_data = pao->pci.ap_mem_base[1] + 1518 (address & 0x007fffff) / 1519 sizeof(*pao->pci.ap_mem_base[1]); 1520 /* HPI_DEBUG_LOG(WARNING, 1521 "BAR1 access %08x\n", dwAddress); */ 1522 } else { 1523 u32 dw4M_page = address >> 22L; 1524 if (dw4M_page != phw->dsp_page) { 1525 phw->dsp_page = dw4M_page; 1526 /* *INDENT OFF* */ 1527 iowrite32(phw->dsp_page, phw->prDSPP); 1528 /* *INDENT-ON* */ 1529 } 1530 address &= 0x3fffff; /* address within 4M page */ 1531 /* BAR0 memory access */ 1532 p_data = pao->pci.ap_mem_base[0] + 1533 address / sizeof(u32); 1534 } 1535 data = ioread32(p_data); 1536 } else if (dsp_index == 1) { 1537 /* DSP 1 is a C6713 */ 1538 u32 lsb; 1539 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address); 1540 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16); 1541 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR); 1542 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR); 1543 data = (data << 16) | (lsb & 0xFFFF); 1544 } 1545 return data; 1546} 1547 1548static void boot_loader_write_mem32(struct hpi_adapter_obj *pao, 1549 int dsp_index, u32 address, u32 data) 1550{ 1551 struct hpi_hw_obj *phw = pao->priv; 1552 __iomem u32 *p_data; 1553 /* u32 dwVerifyData=0; */ 1554 1555 if (dsp_index == 0) { 1556 /* DSP 0 is always C6205 */ 1557 if ((address >= 0x01800000) & (address < 0x02000000)) { 1558 /* BAR1 - DSP register access using */ 1559 /* Non-prefetchable PCI access */ 1560 p_data = pao->pci.ap_mem_base[1] + 1561 (address & 0x007fffff) / 1562 sizeof(*pao->pci.ap_mem_base[1]); 1563 } else { 1564 /* BAR0 access - all of DSP memory using */ 1565 /* pre-fetchable PCI access */ 1566 u32 dw4M_page = address >> 22L; 1567 if (dw4M_page != phw->dsp_page) { 1568 phw->dsp_page = dw4M_page; 1569 /* *INDENT-OFF* */ 1570 iowrite32(phw->dsp_page, phw->prDSPP); 1571 /* *INDENT-ON* */ 1572 } 1573 address &= 0x3fffff; /* address within 4M page */ 1574 p_data = pao->pci.ap_mem_base[0] + 1575 address / sizeof(u32); 1576 } 1577 iowrite32(data, p_data); 1578 } else if (dsp_index == 1) { 1579 /* DSP 1 is a C6713 */ 1580 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address); 1581 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16); 1582 1583 /* dummy read every 4 words for 6205 advisory 1.4.4 */ 1584 boot_loader_read_mem32(pao, 0, 0); 1585 1586 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data); 1587 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16); 1588 1589 /* dummy read every 4 words for 6205 advisory 1.4.4 */ 1590 boot_loader_read_mem32(pao, 0, 0); 1591 } 1592} 1593 1594static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index) 1595{ 1596 if (dsp_index == 0) { 1597 u32 setting; 1598 1599 /* DSP 0 is always C6205 */ 1600 1601 /* Set the EMIF */ 1602 /* memory map of C6205 */ 1603 /* 00000000-0000FFFF 16Kx32 internal program */ 1604 /* 00400000-00BFFFFF CE0 2Mx32 SDRAM running @ 100MHz */ 1605 1606 /* EMIF config */ 1607 /*------------ */ 1608 /* Global EMIF control */ 1609 boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779); 1610#define WS_OFS 28 1611#define WST_OFS 22 1612#define WH_OFS 20 1613#define RS_OFS 16 1614#define RST_OFS 8 1615#define MTYPE_OFS 4 1616#define RH_OFS 0 1617 1618 /* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */ 1619 setting = 0x00000030; 1620 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting); 1621 if (setting != boot_loader_read_mem32(pao, dsp_index, 1622 0x01800008)) 1623 return HPI6205_ERROR_DSP_EMIF; 1624 1625 /* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */ 1626 /* which occupies D15..0. 6713 starts at 27MHz, so need */ 1627 /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */ 1628 /* WST should be 71, but 63 is max possible */ 1629 setting = 1630 (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) | 1631 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) | 1632 (2L << MTYPE_OFS); 1633 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting); 1634 if (setting != boot_loader_read_mem32(pao, dsp_index, 1635 0x01800004)) 1636 return HPI6205_ERROR_DSP_EMIF; 1637 1638 /* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */ 1639 /* which occupies D15..0. 6713 starts at 27MHz, so need */ 1640 /* plenty of wait states */ 1641 setting = 1642 (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) | 1643 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) | 1644 (2L << MTYPE_OFS); 1645 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting); 1646 if (setting != boot_loader_read_mem32(pao, dsp_index, 1647 0x01800010)) 1648 return HPI6205_ERROR_DSP_EMIF; 1649 1650 /* EMIF CE3 setup - 32 bit async. */ 1651 /* This is the PLD on the ASI5000 cards only */ 1652 setting = 1653 (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) | 1654 (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) | 1655 (2L << MTYPE_OFS); 1656 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting); 1657 if (setting != boot_loader_read_mem32(pao, dsp_index, 1658 0x01800014)) 1659 return HPI6205_ERROR_DSP_EMIF; 1660 1661 /* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */ 1662 /* need to use this else DSP code crashes? */ 1663 boot_loader_write_mem32(pao, dsp_index, 0x01800018, 1664 0x07117000); 1665 1666 /* EMIF SDRAM Refresh Timing */ 1667 /* EMIF SDRAM timing (orig = 0x410, emulator = 0x61a) */ 1668 boot_loader_write_mem32(pao, dsp_index, 0x0180001C, 1669 0x00000410); 1670 1671 } else if (dsp_index == 1) { 1672 /* test access to the C6713s HPI registers */ 1673 u32 write_data = 0, read_data = 0, i = 0; 1674 1675 /* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */ 1676 write_data = 1; 1677 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data); 1678 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data); 1679 /* C67 HPI is on lower 16bits of 32bit EMIF */ 1680 read_data = 1681 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR); 1682 if (write_data != read_data) { 1683 HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data, 1684 read_data); 1685 return HPI6205_ERROR_C6713_HPIC; 1686 } 1687 /* HPIA - walking ones test */ 1688 write_data = 1; 1689 for (i = 0; i < 32; i++) { 1690 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, 1691 write_data); 1692 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, 1693 (write_data >> 16)); 1694 read_data = 1695 0xFFFF & boot_loader_read_mem32(pao, 0, 1696 HPIAL_ADDR); 1697 read_data = 1698 read_data | ((0xFFFF & 1699 boot_loader_read_mem32(pao, 0, 1700 HPIAH_ADDR)) 1701 << 16); 1702 if (read_data != write_data) { 1703 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n", 1704 write_data, read_data); 1705 return HPI6205_ERROR_C6713_HPIA; 1706 } 1707 write_data = write_data << 1; 1708 } 1709 1710 /* setup C67x PLL 1711 * ** C6713 datasheet says we cannot program PLL from HPI, 1712 * and indeed if we try to set the PLL multiply from the HPI, 1713 * the PLL does not seem to lock, so we enable the PLL and 1714 * use the default multiply of x 7, which for a 27MHz clock 1715 * gives a DSP speed of 189MHz 1716 */ 1717 /* bypass PLL */ 1718 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000); 1719 hpios_delay_micro_seconds(1000); 1720 /* EMIF = 189/3=63MHz */ 1721 boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002); 1722 /* peri = 189/2 */ 1723 boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001); 1724 /* cpu = 189/1 */ 1725 boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000); 1726 hpios_delay_micro_seconds(1000); 1727 /* ** SGT test to take GPO3 high when we start the PLL */ 1728 /* and low when the delay is completed */ 1729 /* FSX0 <- '1' (GPO3) */ 1730 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A); 1731 /* PLL not bypassed */ 1732 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001); 1733 hpios_delay_micro_seconds(1000); 1734 /* FSX0 <- '0' (GPO3) */ 1735 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02); 1736 1737 /* 6205 EMIF CE1 resetup - 32 bit async. */ 1738 /* Now 6713 #1 is running at 189MHz can reduce waitstates */ 1739 boot_loader_write_mem32(pao, 0, 0x01800004, /* CE1 */ 1740 (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) | 1741 (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) | 1742 (2L << MTYPE_OFS)); 1743 1744 hpios_delay_micro_seconds(1000); 1745 1746 /* check that we can read one of the PLL registers */ 1747 /* PLL should not be bypassed! */ 1748 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF) 1749 != 0x0001) { 1750 return HPI6205_ERROR_C6713_PLL; 1751 } 1752 /* setup C67x EMIF (note this is the only use of 1753 BAR1 via BootLoader_WriteMem32) */ 1754 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL, 1755 0x000034A8); 1756 1757 /* EMIF CE0 setup - 2Mx32 Sync DRAM 1758 31..28 Wr setup 1759 27..22 Wr strobe 1760 21..20 Wr hold 1761 19..16 Rd setup 1762 15..14 - 1763 13..8 Rd strobe 1764 7..4 MTYPE 0011 Sync DRAM 32bits 1765 3 Wr hold MSB 1766 2..0 Rd hold 1767 */ 1768 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0, 1769 0x00000030); 1770 1771 /* EMIF SDRAM Extension 1772 0x00 1773 31-21 0000b 0000b 000b 1774 20 WR2RD = 2cycles-1 = 1b 1775 1776 19-18 WR2DEAC = 3cycle-1 = 10b 1777 17 WR2WR = 2cycle-1 = 1b 1778 16-15 R2WDQM = 4cycle-1 = 11b 1779 14-12 RD2WR = 6cycles-1 = 101b 1780 1781 11-10 RD2DEAC = 4cycle-1 = 11b 1782 9 RD2RD = 2cycle-1 = 1b 1783 8-7 THZP = 3cycle-1 = 10b 1784 6-5 TWR = 2cycle-1 = 01b (tWR = 17ns) 1785 4 TRRD = 2cycle = 0b (tRRD = 14ns) 1786 3-1 TRAS = 5cycle-1 = 100b (Tras=42ns) 1787 1 CAS latency = 3cyc = 1b 1788 (for Micron 2M32-7 operating at 100MHz) 1789 */ 1790 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT, 1791 0x001BDF29); 1792 1793 /* EMIF SDRAM control - set up for a 2Mx32 SDRAM (512x32x4 bank) 1794 31 - 0b - 1795 30 SDBSZ 1b 4 bank 1796 29..28 SDRSZ 00b 11 row address pins 1797 1798 27..26 SDCSZ 01b 8 column address pins 1799 25 RFEN 1b refersh enabled 1800 24 INIT 1b init SDRAM! 1801 1802 23..20 TRCD 0001b (Trcd/Tcyc)-1 = (20/10)-1 = 1 1803 1804 19..16 TRP 0001b (Trp/Tcyc)-1 = (20/10)-1 = 1 1805 1806 15..12 TRC 0110b (Trc/Tcyc)-1 = (70/10)-1 = 6 1807 1808 11..0 - 0000b 0000b 0000b 1809 */ 1810 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL, 1811 0x47116000); 1812 1813 /* SDRAM refresh timing 1814 Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A 1815 */ 1816 boot_loader_write_mem32(pao, dsp_index, 1817 C6713_EMIF_SDRAMTIMING, 0x00000410); 1818 1819 hpios_delay_micro_seconds(1000); 1820 } else if (dsp_index == 2) { 1821 /* DSP 2 is a C6713 */ 1822 } 1823 1824 return 0; 1825} 1826 1827static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index, 1828 u32 start_address, u32 length) 1829{ 1830 u32 i = 0, j = 0; 1831 u32 test_addr = 0; 1832 u32 test_data = 0, data = 0; 1833 1834 length = 1000; 1835 1836 /* for 1st word, test each bit in the 32bit word, */ 1837 /* dwLength specifies number of 32bit words to test */ 1838 /*for(i=0; i<dwLength; i++) */ 1839 i = 0; 1840 { 1841 test_addr = start_address + i * 4; 1842 test_data = 0x00000001; 1843 for (j = 0; j < 32; j++) { 1844 boot_loader_write_mem32(pao, dsp_index, test_addr, 1845 test_data); 1846 data = boot_loader_read_mem32(pao, dsp_index, 1847 test_addr); 1848 if (data != test_data) { 1849 HPI_DEBUG_LOG(VERBOSE, 1850 "Memtest error details " 1851 "%08x %08x %08x %i\n", test_addr, 1852 test_data, data, dsp_index); 1853 return 1; /* error */ 1854 } 1855 test_data = test_data << 1; 1856 } /* for(j) */ 1857 } /* for(i) */ 1858 1859 /* for the next 100 locations test each location, leaving it as zero */ 1860 /* write a zero to the next word in memory before we read */ 1861 /* the previous write to make sure every memory location is unique */ 1862 for (i = 0; i < 100; i++) { 1863 test_addr = start_address + i * 4; 1864 test_data = 0xA5A55A5A; 1865 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data); 1866 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0); 1867 data = boot_loader_read_mem32(pao, dsp_index, test_addr); 1868 if (data != test_data) { 1869 HPI_DEBUG_LOG(VERBOSE, 1870 "Memtest error details " 1871 "%08x %08x %08x %i\n", test_addr, test_data, 1872 data, dsp_index); 1873 return 1; /* error */ 1874 } 1875 /* leave location as zero */ 1876 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0); 1877 } 1878 1879 /* zero out entire memory block */ 1880 for (i = 0; i < length; i++) { 1881 test_addr = start_address + i * 4; 1882 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0); 1883 } 1884 return 0; 1885} 1886 1887static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, 1888 int dsp_index) 1889{ 1890 int err = 0; 1891 if (dsp_index == 0) { 1892 /* DSP 0 is a C6205 */ 1893 /* 64K prog mem */ 1894 err = boot_loader_test_memory(pao, dsp_index, 0x00000000, 1895 0x10000); 1896 if (!err) 1897 /* 64K data mem */ 1898 err = boot_loader_test_memory(pao, dsp_index, 1899 0x80000000, 0x10000); 1900 } else if (dsp_index == 1) { 1901 /* DSP 1 is a C6713 */ 1902 /* 192K internal mem */ 1903 err = boot_loader_test_memory(pao, dsp_index, 0x00000000, 1904 0x30000); 1905 if (!err) 1906 /* 64K internal mem / L2 cache */ 1907 err = boot_loader_test_memory(pao, dsp_index, 1908 0x00030000, 0x10000); 1909 } 1910 1911 if (err) 1912 return HPI6205_ERROR_DSP_INTMEM; 1913 else 1914 return 0; 1915} 1916 1917static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao, 1918 int dsp_index) 1919{ 1920 u32 dRAM_start_address = 0; 1921 u32 dRAM_size = 0; 1922 1923 if (dsp_index == 0) { 1924 /* only test for SDRAM if an ASI5000 card */ 1925 if (pao->pci.pci_dev->subsystem_device == 0x5000) { 1926 /* DSP 0 is always C6205 */ 1927 dRAM_start_address = 0x00400000; 1928 dRAM_size = 0x200000; 1929 /*dwDRAMinc=1024; */ 1930 } else 1931 return 0; 1932 } else if (dsp_index == 1) { 1933 /* DSP 1 is a C6713 */ 1934 dRAM_start_address = 0x80000000; 1935 dRAM_size = 0x200000; 1936 /*dwDRAMinc=1024; */ 1937 } 1938 1939 if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address, 1940 dRAM_size)) 1941 return HPI6205_ERROR_DSP_EXTMEM; 1942 return 0; 1943} 1944 1945static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index) 1946{ 1947 u32 data = 0; 1948 if (dsp_index == 0) { 1949 /* only test for DSP0 PLD on ASI5000 card */ 1950 if (pao->pci.pci_dev->subsystem_device == 0x5000) { 1951 /* PLD is located at CE3=0x03000000 */ 1952 data = boot_loader_read_mem32(pao, dsp_index, 1953 0x03000008); 1954 if ((data & 0xF) != 0x5) 1955 return HPI6205_ERROR_DSP_PLD; 1956 data = boot_loader_read_mem32(pao, dsp_index, 1957 0x0300000C); 1958 if ((data & 0xF) != 0xA) 1959 return HPI6205_ERROR_DSP_PLD; 1960 } 1961 } else if (dsp_index == 1) { 1962 /* DSP 1 is a C6713 */ 1963 if (pao->pci.pci_dev->subsystem_device == 0x8700) { 1964 /* PLD is located at CE1=0x90000000 */ 1965 data = boot_loader_read_mem32(pao, dsp_index, 1966 0x90000010); 1967 if ((data & 0xFF) != 0xAA) 1968 return HPI6205_ERROR_DSP_PLD; 1969 /* 8713 - LED on */ 1970 boot_loader_write_mem32(pao, dsp_index, 0x90000000, 1971 0x02); 1972 } 1973 } 1974 return 0; 1975} 1976 1977/** Transfer data to or from DSP 1978 nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA 1979*/ 1980static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data, 1981 u32 data_size, int operation) 1982{ 1983 struct hpi_hw_obj *phw = pao->priv; 1984 u32 data_transferred = 0; 1985 u16 err = 0; 1986 u32 temp2; 1987 struct bus_master_interface *interface = phw->p_interface_buffer; 1988 1989 if (!p_data) 1990 return HPI_ERROR_INVALID_DATA_POINTER; 1991 1992 data_size &= ~3L; /* round data_size down to nearest 4 bytes */ 1993 1994 /* make sure state is IDLE */ 1995 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) 1996 return HPI_ERROR_DSP_HARDWARE; 1997 1998 while (data_transferred < data_size) { 1999 u32 this_copy = data_size - data_transferred; 2000 2001 if (this_copy > HPI6205_SIZEOF_DATA) 2002 this_copy = HPI6205_SIZEOF_DATA; 2003 2004 if (operation == H620_HIF_SEND_DATA) 2005 memcpy((void *)&interface->u.b_data[0], 2006 &p_data[data_transferred], this_copy); 2007 2008 interface->transfer_size_in_bytes = this_copy; 2009 2010 /* DSP must change this back to nOperation */ 2011 interface->dsp_ack = H620_HIF_IDLE; 2012 send_dsp_command(phw, operation); 2013 2014 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT); 2015 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n", 2016 HPI6205_TIMEOUT - temp2, this_copy); 2017 2018 if (!temp2) { 2019 /* timed out */ 2020 HPI_DEBUG_LOG(ERROR, 2021 "Timed out waiting for " "state %d got %d\n", 2022 operation, interface->dsp_ack); 2023 2024 break; 2025 } 2026 if (operation == H620_HIF_GET_DATA) 2027 memcpy(&p_data[data_transferred], 2028 (void *)&interface->u.b_data[0], this_copy); 2029 2030 data_transferred += this_copy; 2031 } 2032 if (interface->dsp_ack != operation) 2033 HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n", 2034 interface->dsp_ack, operation); 2035 /* err=HPI_ERROR_DSP_HARDWARE; */ 2036 2037 send_dsp_command(phw, H620_HIF_IDLE); 2038 2039 return err; 2040} 2041 2042/* wait for up to timeout_us microseconds for the DSP 2043 to signal state by DMA into dwDspAck 2044*/ 2045static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us) 2046{ 2047 struct bus_master_interface *interface = phw->p_interface_buffer; 2048 int t = timeout_us / 4; 2049 2050 rmb(); /* ensure interface->dsp_ack is up to date */ 2051 while ((interface->dsp_ack != state) && --t) { 2052 hpios_delay_micro_seconds(4); 2053 rmb(); /* DSP changes dsp_ack by DMA */ 2054 } 2055 2056 /*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */ 2057 return t * 4; 2058} 2059 2060/* set the busmaster interface to cmd, then interrupt the DSP */ 2061static void send_dsp_command(struct hpi_hw_obj *phw, int cmd) 2062{ 2063 struct bus_master_interface *interface = phw->p_interface_buffer; 2064 u32 r; 2065 2066 interface->host_cmd = cmd; 2067 wmb(); /* DSP gets state by DMA, make sure it is written to memory */ 2068 /* before we interrupt the DSP */ 2069 r = ioread32(phw->prHDCR); 2070 r |= (u32)C6205_HDCR_DSPINT; 2071 iowrite32(r, phw->prHDCR); 2072 r &= ~(u32)C6205_HDCR_DSPINT; 2073 iowrite32(r, phw->prHDCR); 2074} 2075 2076static unsigned int message_count; 2077 2078static u16 message_response_sequence(struct hpi_adapter_obj *pao, 2079 struct hpi_message *phm, struct hpi_response *phr) 2080{ 2081 u32 time_out, time_out2; 2082 struct hpi_hw_obj *phw = pao->priv; 2083 struct bus_master_interface *interface = phw->p_interface_buffer; 2084 u16 err = 0; 2085 2086 message_count++; 2087 if (phm->size > sizeof(interface->u)) { 2088 phr->error = HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL; 2089 phr->specific_error = sizeof(interface->u); 2090 phr->size = sizeof(struct hpi_response_header); 2091 HPI_DEBUG_LOG(ERROR, 2092 "message len %d too big for buffer %zd \n", phm->size, 2093 sizeof(interface->u)); 2094 return 0; 2095 } 2096 2097 /* Assume buffer of type struct bus_master_interface 2098 is allocated "noncacheable" */ 2099 2100 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) { 2101 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n"); 2102 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT; 2103 } 2104 2105 memcpy(&interface->u.message_buffer, phm, phm->size); 2106 /* signal we want a response */ 2107 send_dsp_command(phw, H620_HIF_GET_RESP); 2108 2109 time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT); 2110 2111 if (!time_out2) { 2112 HPI_DEBUG_LOG(ERROR, 2113 "(%u) Timed out waiting for " "GET_RESP state [%x]\n", 2114 message_count, interface->dsp_ack); 2115 } else { 2116 HPI_DEBUG_LOG(VERBOSE, 2117 "(%u) transition to GET_RESP after %u\n", 2118 message_count, HPI6205_TIMEOUT - time_out2); 2119 } 2120 /* spin waiting on HIF interrupt flag (end of msg process) */ 2121 time_out = HPI6205_TIMEOUT; 2122 2123 /* read the result */ 2124 if (time_out) { 2125 if (interface->u.response_buffer.size <= phr->size) 2126 memcpy(phr, &interface->u.response_buffer, 2127 interface->u.response_buffer.size); 2128 else { 2129 HPI_DEBUG_LOG(ERROR, 2130 "response len %d too big for buffer %d\n", 2131 interface->u.response_buffer.size, phr->size); 2132 memcpy(phr, &interface->u.response_buffer, 2133 sizeof(struct hpi_response_header)); 2134 phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL; 2135 phr->specific_error = 2136 interface->u.response_buffer.size; 2137 phr->size = sizeof(struct hpi_response_header); 2138 } 2139 } 2140 /* set interface back to idle */ 2141 send_dsp_command(phw, H620_HIF_IDLE); 2142 2143 if (!time_out || !time_out2) { 2144 HPI_DEBUG_LOG(DEBUG, "something timed out!\n"); 2145 return HPI6205_ERROR_MSG_RESP_TIMEOUT; 2146 } 2147 /* special case for adapter close - */ 2148 /* wait for the DSP to indicate it is idle */ 2149 if (phm->function == HPI_ADAPTER_CLOSE) { 2150 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) { 2151 HPI_DEBUG_LOG(DEBUG, 2152 "Timeout waiting for idle " 2153 "(on adapter_close)\n"); 2154 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT; 2155 } 2156 } 2157 err = hpi_validate_response(phm, phr); 2158 return err; 2159} 2160 2161static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm, 2162 struct hpi_response *phr) 2163{ 2164 2165 u16 err = 0; 2166 2167 hpios_dsplock_lock(pao); 2168 2169 err = message_response_sequence(pao, phm, phr); 2170 2171 /* maybe an error response */ 2172 if (err) { 2173 /* something failed in the HPI/DSP interface */ 2174 if (err >= HPI_ERROR_BACKEND_BASE) { 2175 phr->error = HPI_ERROR_DSP_COMMUNICATION; 2176 phr->specific_error = err; 2177 } else { 2178 phr->error = err; 2179 } 2180 2181 pao->dsp_crashed++; 2182 2183 /* just the header of the response is valid */ 2184 phr->size = sizeof(struct hpi_response_header); 2185 goto err; 2186 } else 2187 pao->dsp_crashed = 0; 2188 2189 if (phr->error != 0) /* something failed in the DSP */ 2190 goto err; 2191 2192 switch (phm->function) { 2193 case HPI_OSTREAM_WRITE: 2194 case HPI_ISTREAM_ANC_WRITE: 2195 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data, 2196 phm->u.d.u.data.data_size, H620_HIF_SEND_DATA); 2197 break; 2198 2199 case HPI_ISTREAM_READ: 2200 case HPI_OSTREAM_ANC_READ: 2201 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data, 2202 phm->u.d.u.data.data_size, H620_HIF_GET_DATA); 2203 break; 2204 2205 case HPI_CONTROL_SET_STATE: 2206 if (phm->object == HPI_OBJ_CONTROLEX 2207 && phm->u.cx.attribute == HPI_COBRANET_SET_DATA) 2208 err = hpi6205_transfer_data(pao, 2209 phm->u.cx.u.cobranet_bigdata.pb_data, 2210 phm->u.cx.u.cobranet_bigdata.byte_count, 2211 H620_HIF_SEND_DATA); 2212 break; 2213 2214 case HPI_CONTROL_GET_STATE: 2215 if (phm->object == HPI_OBJ_CONTROLEX 2216 && phm->u.cx.attribute == HPI_COBRANET_GET_DATA) 2217 err = hpi6205_transfer_data(pao, 2218 phm->u.cx.u.cobranet_bigdata.pb_data, 2219 phr->u.cx.u.cobranet_data.byte_count, 2220 H620_HIF_GET_DATA); 2221 break; 2222 } 2223 phr->error = err; 2224 2225err: 2226 hpios_dsplock_unlock(pao); 2227 2228 return; 2229} 2230