Cross Reference: /arch/arm/boot/compressed/head.S

History log of /arch/arm/boot/compressed/head.S
Revision	Date	Author	Comments
c7ce15a8a21acc869fae66a3d119b55d325c9416	01-Dec-2012	Arve Hjønnevåg <arve@android.com>	ARM: decompressor: Flush tlb before swiching domain 0 to client mode If the bootloader used a page table that is incompatible with domain 0 in client mode, and boots with the mmu on, then swithing domain 0 to client mode causes a fault if we don't flush the tlb after updating the page table pointer. v2: Add ISB before loading dacr. Signed-off-by: Arve Hjønnevåg <arve@android.com>
238962ac71910d6c20162ea5230685fead1836a4	04-Nov-2014	Will Deacon <will.deacon@arm.com>	ARM: 8191/1: decompressor: ensure I-side picks up relocated code To speed up decompression, the decompressor sets up a flat, cacheable mapping of memory. However, when there is insufficient space to hold the page tables for this mapping, we don't bother to enable the caches and subsequently skip all the cache maintenance hooks. Skipping the cache maintenance before jumping to the relocated code allows the processor to predict the branch and populate the I-cache with stale data before the relocation loop has completed (since a bootloader may have SCTLR.I set, which permits normal, cacheable instruction fetches regardless of SCTLR.M). This patch moves the cache maintenance check into the maintenance routines themselves, allowing the v6/v7 versions to invalidate the I-cache regardless of the MMU state. Cc: <stable@vger.kernel.org> Reported-by: Marc Carino <marc.ceeeee@gmail.com> Tested-by: Julien Grall <julien.grall@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
9696fcae9251610f5935a3823be40d1365649720	19-Jun-2014	Nicolas Pitre <nicolas.pitre@linaro.org>	ARM: 8079/1: zImage: identify kernel endianness With patch #8067/1 ("zImage: ensure header in LE format for BE8 kernels") applied, it is no longer possible to determine the endianness of a compiled kernel image. This normally shouldn't matter to the boot environment, except for those cases where the selection of a ramdisk or root filesystem with a matching endianness has to be automated. Let's add a flag to the zImage header indicating the actual endianness. Four bytes from offset 0x30 can be interpreted as follows: 04 03 02 01 big endian kernel 01 02 03 04 little endian kernel Anything else should be interpreted as "unknown", in which case it is most likely that patch #8067/1 was not applied either and the zImage magic number at offset 0x24 could be used instead to determine endianness. No zImage before this patch ever produced 0x01020304 nor 0x04030201 at offset 0x30 so there is no confusion possible. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
33656d565da51bd01779600352ec28385ab806c8	02-Jun-2014	Nicolas Pitre <nico@fluxnic.net>	ARM: 8067/1: zImage: ensure header in LE format for BE8 kernels All known BE8-capable systems have LE bootloaders, so we need to ensure that the magic number and image start/end values are in little endian format. [ben.dooks@codethink.co.uk: from nico's original email on this subject] [taras.kondratiuk@linaro.org: removed lds.S->lds rule, added target to extra-y] Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
46f34abc750c66fdb4daa9a8bc9d7f955e95eb9c	15-May-2014	Heiko Stuebner <heiko@sntech.de>	ARM: compressed/head.S: remove s3c24xx special case addruart from the generic debug macro is doing exactly the same using the common lowlevel uart definition, so there is no cause for this special casing for s3c24xx. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
97bcb0fea590d3d704f985bec08f342d28992634	01-Feb-2013	Ben Dooks <ben.dooks@codethink.co.uk>	ARM: set BE8 if LE in head code If we are booting in LE and compiled for BE8, then add code to set the state to bE8. Since the instruction stream is always LE, we do not need to do anything special to the instruction. Also ensure that the secondary processors are started in the same mode. Note, we do add about 20 bytes to the kernel image, but it seems easier to do this than adding another configuration to change. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
457c2403c513c74f60d5757fd11ae927e5554a38	12-Feb-2013	Ben Dooks <ben.dooks@codethink.co.uk>	ARM: asm: Add ARM_BE8() assembly helper Add ARM_BE8() helper to wrap any code conditional on being compile when CONFIG_ARM_ENDIAN_BE8 is selected and convert existing places where this is to use it. Acked-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
52c08a9e399739979027ea1e463f5529476da104	21-Jun-2013	Marc Zyngier <Marc.Zyngier@arm.com>	ARM: 7770/1: remove residual ARMv2 support from decompressor arm26 support in Linux is long gone, yet it left an interresting, fossilized trace in the decompressor. Remove it so people won't get confused about what teqp is actually doing here... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2874865c1271cc8e8b663804e5de4bc0c36273e1	06-Jun-2013	Nicolas Pitre <nicolas.pitre@linaro.org>	ARM: 7751/1: zImage: don't overwrite ourself with a page table When zImage is loaded into RAM at a low address but TEXT_OFFSET is set higher, we risk overwriting ourself with the page table needed to turn on the cache as it is located relative to the relocation address. Let's defer the cache setup after relocation in that case. Signed-off-by: Nicolas Pitre <nico@linaro.org> Reported-by: Stephen Boyd <sboyd@codeurora.org> Tested-by: Stephen Boyd <sboyd@codeurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ced2a3b84965f1be8b6a142d6029faf241f109af	05-Jun-2013	Marc C <marc.ceeeee@gmail.com>	ARM: 7750/1: update legacy CPU ID in decompressor cache support jump table The previous mask values for the legacy ARM CPU IDs were conflicting with the CPU ID assignments for late-generation CPUs (like the Qualcomm MSM/QSD or Broadcom Brahma-15 processors). This change corrects the legacy ARM CPU ID value so that the jump table can fall-through to the appropriate cache maintenance / MMU functions. Signed-off-by: Marc C <marc.ceeeee@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
da94a829305f1c217cfdf6771cb1faca0917e3b9	31-May-2013	Arnd Bergmann <arnd@arndb.de>	ARM: 7743/1: compressed/head.S: work around new binutils warning In August 2012, Matthew Gretton-Dann checked a change into binutils labelled "Error on obsolete & warn on deprecated registers", apparently as part of ARMv8 support. Apparently, this was supposed to emit the message "Warning: This coprocessor register access is deprecated in ARMv8" when using certain mcr/mrc instructions and building for ARMv8. Unfortunately, the message that is actually emitted appears to be '(null)', which is less helpful in comparison. Even more unfortunately, this is biting us on every single kernel build with a new gas, because arch/arm/boot/compressed/head.S and some other files in that directory are built with -march=all since kernel commit 80cec14a8 "[ARM] Add -march=all to assembly file build in arch/arm/boot/compressed" back in v2.6.28. This patch reverts Russell's nice solution and instead marks the head.S file to be built for armv7-a, which fortunately lets us build all instructions in that file without warnings even on the broken binutils. Without this patch, building anything results in: arch/arm/boot/compressed/head.S: Assembler messages: arch/arm/boot/compressed/head.S:565: Warning: (null) arch/arm/boot/compressed/head.S:676: Warning: (null) arch/arm/boot/compressed/head.S:698: Warning: (null) arch/arm/boot/compressed/head.S:722: Warning: (null) arch/arm/boot/compressed/head.S:726: Warning: (null) arch/arm/boot/compressed/head.S:957: Warning: (null) arch/arm/boot/compressed/head.S:996: Warning: (null) arch/arm/boot/compressed/head.S:997: Warning: (null) arch/arm/boot/compressed/head.S:1027: Warning: (null) arch/arm/boot/compressed/head.S:1035: Warning: (null) arch/arm/boot/compressed/head.S:1046: Warning: (null) arch/arm/boot/compressed/head.S:1060: Warning: (null) arch/arm/boot/compressed/head.S:1092: Warning: (null) arch/arm/boot/compressed/head.S:1094: Warning: (null) arch/arm/boot/compressed/head.S:1095: Warning: (null) arch/arm/boot/compressed/head.S:1102: Warning: (null) arch/arm/boot/compressed/head.S:1134: Warning: (null) Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: stable@vger.kernel.org Cc: Matthew Gretton-Dann <matthew.gretton-dann@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
4beba08ba1574f6d427347edaba5b924b2f70826	11-Dec-2012	Shawn Guo <shawn.guo@linaro.org>	ARM: 7600/1: include CONFIG_DEBUG_LL_INCLUDE rather than mach/debug-macro.S Commit 91a9fec (ARM: move debug macros to common location) moves arch/arm/kernel/debug.S and arch/arm/kernel/head.S to CONFIG_DEBUG_LL_INCLUDE, but leaves arch/arm/boot/compressed/head.S still with mach/debug-macro.S. This causes the following build error on platforms that moved to new DEBUG_LL inclusion mechanism, when arch/arm/boot/compressed/head.S is compiled with DEBUG turned on. AS arch/arm/boot/compressed/head.o arch/arm/boot/compressed/head.S:49:30: fatal error: mach/debug-macro.S: No such file or directory compilation terminated. Fix the problem by replacing mach/debug-macro.S inclusion with CONFIG_DEBUG_LL_INCLUDE one. Reported-by: Steev Klimaszewski <steev@genesi-usa.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
5010192d5ae589002c4453d6c6e662e5e9acae59	22-Nov-2012	Dave Martin <dave.martin@linaro.org>	ARM: 7583/1: decompressor: Enable unaligned memory access for v6 and above Modern GCC can generate code which makes use of the CPU's native unaligned memory access capabilities. This is useful for the C decompressor implementations used for unpacking compressed kernels. This patch disables alignment faults and enables the v6 unaligned access model on CPUs which support these features (i.e., v6 and later), allowing full unaligned access support for C code in the decompressor. The decompressor C code must not be built to assume that unaligned access works if support for v5 or older platforms is included in the kernel. For correct code generation, C decompressor code must always use the get_unaligned and put_unaligned accessors when dealing with unaligned pointers, regardless of this patch. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
424e5994e63326a42012f003f1174f3c363c7b62	11-Feb-2012	Dave Martin <dave.martin@linaro.org>	ARM: zImage/virt: hyp mode entry support for the zImage loader The zImage loader needs to turn on the MMU in order to take advantage of caching while decompressing the zImage. Running this in hyp mode would require the LPAE pagetable format to be supported; to avoid this complexity, this patch switches out of hyp mode, and returns back to hyp mode just before booting the kernel. This implementation assumes that the Hyp mode view of memory and the PL1 view of memory are coherent, providing that the MMU and caches are off in both, as required by the boot protocol. The zImage decompression code must drain the write buffer on completion anyway, and entry into Hyp mode should flush any prefetch buffer, avoiding hazards associated with local write buffers and the pipeline. Signed-off-by: Dave Martin <dave.martin@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
e1e5b7e4251c7538ca08c2c5545b0c2fbd8a6635	11-Sep-2012	Matthew Leach <matthew.leach@arm.com>	ARM: 7532/1: decompressor: reset SCTLR.TRE for VMSA ARMv7 cores This patch zeroes the SCTLR.TRE bit prior to setting the mapping as cacheable for ARMv7 cores in the decompressor, ensuring that the memory region attributes are obtained from the C and B bits, not from the page tables. Cc: Nicolas Pitre <nico@fluxnic.net> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Cc: <stable@vger.kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
dbece45894d3ab1baac15a96dc4e1e8e23f64a93	24-Aug-2012	Will Deacon <will.deacon@arm.com>	ARM: 7501/1: decompressor: reset ttbcr for VMSA ARMv7 cores When enabling the MMU for ARMv7 CPUs, the decompressor does not touch the ttbcr register, assuming that it will be zeroed (N == 0, EAE == 0). Given that only EAE is defined as 0 for non-secure copies of the register (and a bootloader such as kexec may leave it set to 1 anyway), we should ensure that we reset the register ourselves before turning on the MMU. This patch zeroes TTBCR.EAE and TTBCR.N prior to enabling the MMU for ARMv7 cores in the decompressor, configuring us exclusively for 32-bit translation tables via TTBR0. Cc: <stable@vger.kernel.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1fdc08abfa26f30fcef0ce1333e9ac6f80350f30	10-May-2012	Russell King <rmk+kernel@arm.linux.org.uk>	ARM: decompressor: avoid speculative prefetch from non-RAM areas We setup identity MMU mappings across the entire 4GB of space, which are permissionless because the domain is set to manager. This unfortunately allows ARMv6 and later CPUs to speculatively prefetch from the entire address space, which can cause undesirable side effects if those regions contain devices. As we setup the mappings with read/write permission, we can switch the domain to client mode, and then use the XN bit for ARMv6 and above to control speculative prefetch to non-RAM areas. Reported-by: R Sricharan <r.sricharan@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
4cdfc2ec72e940abb4322aa1bc14f43a1486fc5d	09-May-2012	Russell King <rmk+kernel@arm.linux.org.uk>	ARM: Remove ARMv3 support from decompressor Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
9c5fd9e85f574d9d0361b2b878f55732290afe5b	11-Apr-2012	Marc Zyngier <Marc.Zyngier@arm.com>	ARM: 7379/1: DT: fix atags_to_fdt() second call site atags_to_fdt() returns 1 when it fails to find a valid FDT signature. The CONFIG_ARM_ATAG_DTB_COMPAT code is supposed to retry with another location, but only does so when the initial call doesn't fail. Fix this by using the correct condition in the assembly code. Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: stable@vger.kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
b130d5c29544fe4cedafd35b112d27a06550d844	03-Feb-2012	Kukjin Kim <kgene.kim@samsung.com>	ARM: S3C24XX: change the ARCH_S3C2410 to ARCH_S3C24XX This patch changes the ARCH name to "ARCH_S3C24XX" for Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, and S3C2450 SoCs so that we can merge the mach-xxx directories and plat-s3c24xx dir. to just one mach-s3c24xx for them. I think this should be sent to upstream via samsung tree because this touches many samsung stuff. Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Richard Purdie <rpurdie@rpsys.net> Cc: Chris Ball <cjb@laptop.org> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Greg Kroah-Hartman <gregkh@suse.de> [for the gadget part:] Acked-by: Felipe Balbi <balbi@ti.com> [for the framebuffer (video) part:] Acked-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de> [For the watchdog-part:] Acked-by: Wim Van Sebroeck <wim@iguana.be> Cc: Sangbeom Kim <sbkim73@samsung.com> Cc: Liam Girdwood <lrg@ti.com> Cc: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
d675d0bc47f28c5414fbbe17fcc801f69c45b960	22-Nov-2011	Will Deacon <will.deacon@arm.com>	ARM: LPAE: add ISBs around MMU enabling code Before we enable the MMU, we must ensure that the TTBR registers contain sane values. After the MMU has been enabled, we jump to the virtual address of the following function, so we also need to ensure that the SCTLR write has taken effect. This patch adds ISB instructions around the SCTLR write to ensure the visibility of the above. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
531a6a941745e1e045dd2a6bd09e1dc01247a5f3	24-Oct-2011	Nicolas Pitre <nicolas.pitre@linaro.org>	ARM: 7139/1: fix compilation with CONFIG_ARM_ATAG_DTB_COMPAT and large TEXT_OFFSET If TEXT_OFFSET is too large (e.g. like on MSM) the resulting immediate argument gets wider than 8 bits. Noticed by David Brown <davidb@codeaurora.org> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
b90b9a38251e9c89c34179eccde57411ceb5f1aa	14-Sep-2011	Nicolas Pitre <nicolas.pitre@linaro.org>	ARM: zImage: allow supplementing appended DTB with traditional ATAG data Some old bootloaders can't be updated to a device tree capable one, yet they provide ATAGs with memory configuration, the ramdisk address, the kernel cmdline string, etc. To allow a device tree enabled kernel to be used with such bootloaders, it is necessary to convert those ATAGs into FDT properties and fold them into the DTB appended to zImage. Currently the following ATAGs are converted: ATAG_CMDLINE ATAG_MEM ATAG_INITRD2 If the corresponding information already exists in the appended DTB, it is replaced, otherwise the required node is created to hold it. The code looks for ATAGs at the location pointed by the value of r2 upon entry into the zImage code. If no ATAGs are found there, an attempt at finding ATAGs at the typical 0x100 offset from start of RAM is made. Otherwise the DTB is left unchanged. Thisstarted from an older patch from John Bonesio <bones@secretlab.ca>, with contributions from David Brown <davidb@codeaurora.org>. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dave Martin <dave.martin@linaro.org> Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
5ffb04f6690d71fab241b3562ebf52b893ac4ff1	12-Jun-2011	Nicolas Pitre <nicolas.pitre@linaro.org>	ARM: zImage: make sure appended DTB doesn't get overwritten by kernel .bss The appended DTB gets relocated with the decompressor code to get out of the way of the decompressed kernel. However the kernel's .bss section may be larger than the relocated code and data, and then the DTB gets overwritten. Let's make sure the relocation takes care of moving zImage far enough so no such conflict with .bss occurs. Thanks to Tony Lindgren <tony@atomide.com> for figuring out this issue. While at it, let's clean up the code a bit so that the wont_overwrite symbol is used while determining if a conflict exists, making the above change more precise as well as eliminating some ARM/THUMB alternates. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dave Martin <dave.martin@linaro.org> Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
e2a6a3aafa9862c4a4b59f2a59b8f923d64a680e	28-May-2011	John Bonesio <bones@secretlab.ca>	ARM: zImage: Allow the appending of a device tree binary This patch provides the ability to boot using a device tree that is appended to the raw binary zImage (e.g. cat zImage <filename>.dtb > zImage_w_dtb). Signed-off-by: John Bonesio <bones@secretlab.ca> [nico: ported to latest zImage changes plus additional cleanups/improvements] Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Dave Martin <dave.martin@linaro.org> Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
540b573875bd26dfe39aa18d22dc195f275fc0df	13-Jul-2011	Dave Martin <dave.martin@linaro.org>	ARM: 6999/1: head, zImage: Always Enter the kernel in ARM state Currently, the documented kernel entry requirements are not explicit about whether the kernel should be entered in ARM or Thumb, leading to an ambiguitity about how to enter Thumb-2 kernels. As a result, the kernel is reliant on the zImage decompressor to enter the kernel proper in the correct instruction set state. This patch changes the boot entry protocol for head.S and Image to be the same as for zImage: in all cases, the kernel is now entered in ARM. Documentation/arm/Booting is updated to reflect this new policy. A different rule will be needed for Cortex-M class CPUs as and when support for those lands in mainline, since these CPUs don't support the ARM instruction set at all: a note is added to the effect that the kernel must be entered in Thumb on such systems. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
946a105e16651c35e9cc670bff23812761f1ad35	14-Jun-2011	Dave Martin <dave.martin@linaro.org>	ARM: 6961/1: zImage: Add build-time check for correctly-sized proc_type entries It is easy to mis-maintain the proc_types table such that the entries become wrongly-sized and misaligned when the kernel is built in Thumb-2. This patch adds an assembly-time check which will turn most common size/alignment mistakes in this table into build failures, to avoid having to debug the boot-time kernel hang which would happen if the resulting kernel were actually booted. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
720c60e1943a06cfd9472ad5a9967dec304e4394	09-Jun-2011	Nicolas Pitre <nicolas.pitre@linaro.org>	ARM: 6954/1: zImage: fix Thumb2 breakage Commit af3e4fd37a "ARM: 6859/1: Add writethrough dcache support for ARM926EJS processor" broke Thumb2 compilation by omitting to maintain the wide encoding for the added branch instructions which made the ARM926EJ-S record smaller than expected, breaking the record walk code. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
af3e4fd37a18f2e5a00175bc96061541d1364a3b	01-Apr-2011	Mark A. Greer <mgreer@mvista.com>	ARM: 6859/1: Add writethrough dcache support for ARM926EJS processor The ARM kernel supports writethrough data cache via the CONFIG_CPU_DCACHE_WRITETHROUGH option. However, that functionality wasn't implemented in the arch/arm/boot/compressed code. It is now necessary due to a new ARM926EJS processor that has an issue with writeback data cache. Signed-off-by: Mark A. Greer <mgreer@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
8d7e4cc2c8ea1d180d32d902eb899f27d3ee53d7	27-Apr-2011	Nicolas Pitre <nicolas.pitre@linaro.org>	ARM: zImage: make sure no GOTOFF relocs are used with .bss symbols To be able to relocate the .bss section at run time independently from the rest of the code, we must make sure that no GOTOFF relocations are used with .bss symbols. This usually means that no global variables can be marked static unless they're also const. To enforce this, suffice to fail the build whenever a private symbol is allocated to .bss and list those symbols for convenience. The user_stack and user_stack_end labels in head.S were converted into non exported symbols to remove false positives. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
34cc1a8fe0d3f89f3602b49f1121a99d2bfc5efc	19-Apr-2011	Nicolas Pitre <nicolas.pitre@linaro.org>	ARM: zImage: no need to get the decompressed size from the filesystem In commit d239b1dc093d the hardcoded 4x estimate for the decompressed kernel size was replaced by the exact Image file size and passed to the linker as a symbol value. Turns out that this is unneeded as the size is already included at the end of the compressed piggy data. For those compressed formats that don't include this data, the build system already takes care of appending it using size_append in scripts/Makefile.lib. So let's use that instead. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
ea9df3b168e641e87dbf889afae16390119e4179	22-Apr-2011	Nicolas Pitre <nicolas.pitre@linaro.org>	ARM: zImage: the page table memory must be considered before relocation For correctness, the initial page table located right before the decompressed kernel should be considered when determining if relocation is required. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com>
adcc25915b98e5752d51d66774ec4a61e50af3c5	27-Apr-2011	Nicolas Pitre <nicolas.pitre@linaro.org>	ARM: zImage: make sure not to relocate on top of the relocation code If the zImage load address is slightly below the relocation address, there is a risk for the copied data to overwrite the copy loop or cache flush code that the relocation process requires. Always bump the relocation address by the size of that code to avoid this issue. Noticed by Tony Lindgren <tony@atomide.com>. While at it, let's start the copy from the restart symbol which makes the above code size computation possible by the assembler directly (same sections), given that we don't need to preserve the code before that point anyway. And therefore we don't need to carry the _start pointer in r5 anymore. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com>
7c2527f0c4bf6bd096f58296597e1373387d69fd	26-Apr-2011	Tony Lindgren <tony@atomide.com>	ARM: zImage: Fix bad SP address after relocating kernel Otherwise cache_clean_flush can overwrite some of the relocated area depending on where the kernel image gets loaded. This fixes booting on n900 after commit 6d7d0ae51574943bf571d269da3243257a2d15db (ARM: 6750/1: improvements to compressed/head.S). Thanks to Aaro Koskinen <aaro.koskinen@nokia.com> for debugging the address of the relocated area that gets corrupted, and to Nicolas Pitre <nicolas.pitre@linaro.org> for the other uncompress related fixes. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
f5178ddd2f09de8b1cfc5e19043892e8b24666cb	03-May-2011	Nicolas Pitre <nico@fluxnic.net>	ARM: PJ4: remove the ARMv6 compatible cache method entries The Marvell PJ4 is ARMv7 capable, so we don't support it in ARMv6 mode anymore. Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Acked-by: Saeed Bishara <saeed.bishara@gmail.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
dfad549d98b60160547d1b8299051b9456c8da85	23-Mar-2011	Stephen Boyd <sboyd@codeaurora.org>	ARM: 6826/1: Merge v6 and v7 DEBUG_LL DCC support The inline assembly differences for v6 vs. v7 are purely optimizations. On a v7 processor, an mrc with the pc sets the condition codes to the 28-31 bits of the register being read. It just so happens that the TX/RX full bits the DCC support code is testing for are high enough in the register to be put into the condition codes. On a v6 processor, this "feature" isn't implemented and thus we have to do the usual read, mask, test operations to check for TX/RX full. Thus, we can drop the v7 implementation and just use the v6 implementation for both. Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
6d7d0ae51574943bf571d269da3243257a2d15db	21-Feb-2011	Nicolas Pitre <nicolas.pitre@linaro.org>	ARM: 6750/1: improvements to compressed/head.S In the case of a conflict between the memory used by the compressed kernel with its decompressor code and the memory used for the decompressed kernel, we currently store the later after the former and relocate it afterwards. This would be more efficient to do this the other way around i.e. relocate the compressed data up front instead, resulting in a smaller copy. That also has the advantage of making the code smaller and more straight forward. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
b11fe38883d1de76f2f847943e085a808f83f189	12-Feb-2011	Nicolas Pitre <nico@fluxnic.net>	ARM: 6663/1: make Thumb2 kernel entry point more similar to the ARM one Some installers would binary patch the kernel zImage to replace the first few nops with custom instructions. This breaks the Thumb2 kernel as the mode switch is right at the beginning. Let's move it towards the end of the nop sequence instead. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
e399b1a4e1d205bdc816cb550d2064f2eb1ddc4c	17-Jan-2011	Russell King <rmk+kernel@arm.linux.org.uk>	ARM: v6k: introduce CPU_V6K option Introduce a CPU_V6K configuration option for platforms to select if they have a V6K CPU core. This allows us to identify whether we need to support ARMv6 CPUs without the V6K SMP extensions at build time. Currently CPU_V6K is just an alias for CPU_V6, and all places which reference CPU_V6 are replaced by (CPU_V6 \|\| CPU_V6K). Select CPU_V6K from platforms which are known to be V6K-only. Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Sourav Poddar <sourav.poddar@ti.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
26e5ca93dda9425f8ff78ccb2f9b193328087e45	29-Nov-2010	Dave Martin <dave.martin@linaro.org>	ARM: 6503/1: Thumb-2: Restore sensible zImage header layout for CONFIG_THUMB2_KERNEL The code which makes up the zImage header intends to leave a 32-byte gap followed by a branch to the real entry point, a magic number, and a word containing the absolute entry point address. This gets messed up with with CONFIG_THUMB2_KERNEL, because the size of the initial padding NOPs changes. Instead, the header can be made fully compatible by restoring it to ARM. In the Thumb-2 case, we can replace the initial NOPs with a sequence which switches to Thumb and jumps to the real entry point. As a consequence, the zImage entry point is now always ARM, so no special magic is needed any more for the uImage rules in the Thumb-2 case. Signed-off-by: Dave Martin <dave.martin@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>