| 182905a21200e252f83da17f48ba36d343aaf642 |
|
23-Apr-2014 |
Doug Anderson <dianders@chromium.org> |
UPSTREAM: arm: kgdb: Handle read-only text / modules
Handle the case where someone has set the text segment of the kernel
as read-only by using the newly introduced "patch" mechanism.
Signed-off-by: Doug Anderson <dianders@chromium.org>
[kees: switched structure size check to BUILD_BUG_ON (sboyd)]
Signed-off-by: Kees Cook <keescook@chromium.org>
Acked-by: Nicolas Pitre <nico@linaro.org>
(cherry picked from commit 23a4e4050ba9c98ab67db0980a9fb20e5096d9ea)
Signed-off-by: Kees Cook <keescook@google.com>
Change-Id: I39fafcb198d37779650e9ddb0461cf28406beeed
|
| d93003e8e4e1fbbc8a06ec561a63f5aa105a4c45 |
|
24-Apr-2014 |
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
ARM: 8042/1: iwmmxt: allow to build iWMMXt on Marvell PJ4B
Some Marvell PJ4B CPUs also implement iWMMXt extensions. With a
proper check for iWMMXt coprocessors now in place, enable it by
default on PJ4B. While at it, also allow to manually select
the corresponding Kconfig option.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 603fb42a66499ab353466c7afa3d38beea20a8a9 |
|
25-Mar-2014 |
Sebastian Capella <sebastian.capella@linaro.org> |
ARM: 8011/1: ARM hibernation / suspend-to-disk
Enable hibernation for ARM architectures and provide ARM
architecture specific calls used during hibernation.
The swsusp hibernation framework depends on the
platform first having functional suspend/resume.
Then, in order to enable hibernation on a given platform, a
platform_hibernation_ops structure may need to be registered with
the system in order to save/restore any SoC-specific / cpu specific
state needing (re)init over a suspend-to-disk/resume-from-disk cycle.
For example:
- "secure" SoCs that have different sets of control registers
and/or different CR reg access patterns.
- SoCs with L2 caches as the activation sequence there is
SoC-dependent; a full off-on cycle for L2 is not done
by the hibernation support code.
- SoCs requiring steps on wakeup _before_ the "generic" parts
done by cpu_suspend / cpu_resume can work correctly.
- SoCs having persistent state which is maintained during suspend
and resume, but will be lost during the power off cycle after
suspend-to-disk.
This is a rebase/rework of Frank Hofmann's v5 hibernation patchset.
Acked-by: Russ Dill <Russ.Dill@ti.com>
Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Signed-off-by: Sebastian Capella <sebastian.capella@linaro.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[fixed duplicate virt_to_pfn() definition --rmk]
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| c7edc9e326d53ca5ef9bed82de0740c6b107d55b |
|
07-Mar-2014 |
David A. Long <dave.long@linaro.org> |
ARM: add uprobes support
Using Rabin Vincent's ARM uprobes patches as a base, enable uprobes
support on ARM.
Caveats:
- Thumb is not supported
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: David A. Long <dave.long@linaro.org>
|
| 87abef63ead5ac9e2c67f0c07c461eda6be16aeb |
|
06-Mar-2014 |
David A. Long <dave.long@linaro.org> |
ARM: move generic thumb instruction parsing code to new files for use by other feature
Move the thumb version of the kprobes instruction parsing code into more generic
files from where it can be used by uprobes and possibly other subsystems. The
symbol names will be made more generic in a subsequent part of this patchset.
Signed-off-by: David A. Long <dave.long@linaro.org>
Acked-by: Jon Medhurst <tixy@linaro.org>
|
| c18377c303787ded44b7decd7dee694db0f205e9 |
|
07-Mar-2014 |
David A. Long <dave.long@linaro.org> |
ARM: Move generic arm instruction parsing code to new files for sharing between features
Move the arm version of the kprobes instruction parsing code into more generic
files from where it can be used by uprobes and possibly other subsystems. The
symbol names will be made more generic in a subsequent part of this patchset.
Signed-off-by: David A. Long <dave.long@linaro.org>
Acked-by: Jon Medhurst <tixy@linaro.org>
|
| 574e2b5111e13827da501771b27d92e6e3f2e3d7 |
|
28-Aug-2013 |
Victor Kamensky <victor.kamensky@linaro.org> |
ARM: signal: sigreturn_codes should be endian neutral to work in BE8
In case of BE8 kernel data is in BE order whereas code stays in LE
order. Move sigreturn_codes to separate .S file and use proper
assembler mnemonics for these code snippets. In this case compiler
will take care of proper instructions byteswaps for BE8 case.
Change assumes that sufficiently Thumb-capable tools are used to
build kernel.
Problem was discovered during ltp testing of BE system: all rt_sig*
tests failed. Tested against the same tests in both BE and LE modes.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
|
| 49863894db3ed7bd41541b1c17733273966cea71 |
|
26-Sep-2013 |
Will Deacon <will.deacon@arm.com> |
ARM: perf: add support for perf registers API
This patch implements the functions required for the perf registers API,
allowing the perf tool to interface kernel register dumps with libunwind
in order to provide userspace backtracing.
Cc: Jean Pihet <jean.pihet@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
|
| 6a7d2c625656df5f8ad6e33aa3d164eefb1df8dc |
|
27-Aug-2013 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
ARM: 7828/1: ARMv7-M: implement restart routine common to all v7-M machines
The newly introduced function is to be used as .restart callback for
ARMv7-M machines. The used register is architecturally defined, so it
should work for all M-class machines.
Acked-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 38ff87f77af0b5a93fc8581cff1d6e5692ab8970 |
|
02-Jun-2013 |
Stephen Boyd <sboyd@codeaurora.org> |
sched_clock: Make ARM's sched_clock generic for all architectures
Nothing about the sched_clock implementation in the ARM port is
specific to the architecture. Generalize the code so that other
architectures can use it by selecting GENERIC_SCHED_CLOCK.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[jstultz: Merge minor collisions with other patches in my tree]
Signed-off-by: John Stultz <john.stultz@linaro.org>
|
| 8006b4d1a7c70f27a87cb753b5ed90483f0cfe26 |
|
24-Apr-2013 |
Jonathan Austin <jonathan.austin@arm.com> |
ARM: nommu: Don't build smp_tlb.c for !CONFIG_MMU
Without an MMU we don't need to do any TLB maintenance. Until the addition
of 93dc68876b60 (ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181
(TLBI/DSB operations)) building the tlb maintenance ops in smp_tlb.c worked,
though none of the contents were used.
Since that commit, however, SMP NOMMU has not been able to build. This patch
restores that ability by making the building of smp_tlb.c dependent on MMU.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
CC: Will Deacon <will.deacon@arm.com>
|
| 05774088391c7430f6a4c1d5d18196ef17bb3ba9 |
|
21-May-2013 |
Stefano Stabellini <stefano.stabellini@eu.citrix.com> |
arm: introduce psci_smp_ops
Rename virt_smp_ops to psci_smp_ops and move them to arch/arm/kernel/psci_smp.c.
Remove mach-virt/platsmp.c, now unused.
Compile psci_smp if CONFIG_ARM_PSCI and CONFIG_SMP.
Add a cpu_die smp_op based on psci_ops.cpu_off.
Initialize PSCI before setting smp_ops in setup_arch.
If PSCI is available on the platform, prefer psci_smp_ops over the
platform smp_ops.
Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Will Deacon <will.deacon@arm.com>
CC: arnd@arndb.de
CC: marc.zyngier@arm.com
CC: linux@arm.linux.org.uk
CC: nico@linaro.org
CC: rob.herring@calxeda.com
|
| 4477ca45fb368880bf77b10ed3b24b03f0cc82da |
|
21-Mar-2013 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
ARM: ARMv7-M: Allow the building of new kernel port
This patch modifies the required Kconfig and Makefile files to allow the
building of kernel for Cortex-M3.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Jonathan Austin <jonathan.austin@arm.com>
Tested-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
|
| 2bdd424f26be1c98b6e3d9acfffb5559c131c888 |
|
12-Dec-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: psci: add support for PSCI invocations from the kernel
This patch adds support for the Power State Coordination Interface
defined by ARM, allowing Linux to request CPU-centric power-management
operations from firmware implementing the PSCI protocol.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
|
| 80c59dafb1a9a86fa996e6e34d06b60567c925ca |
|
09-Feb-2012 |
Dave Martin <dave.martin@linaro.org> |
ARM: virt: allow the kernel to be entered in HYP mode
This patch does two things:
* Ensure that asynchronous aborts are masked at kernel entry.
The bootloader should be masking these anyway, but this reduces
the damage window just in case it doesn't.
* Enter svc mode via exception return to ensure that CPU state is
properly serialised. This does not matter when switching from
an ordinary privileged mode ("PL1" modes in ARMv7-AR rev C
parlance), but it potentially does matter when switching from a
another privileged mode such as hyp mode.
This should allow the kernel to boot safely either from svc mode or
hyp mode, even if no support for use of the ARM Virtualization
Extensions is built into the kernel.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
|
| bd51e2f595580fb64bd8494badef746c4d626b25 |
|
01-Sep-2012 |
Nicolas Pitre <nicolas.pitre@linaro.org> |
ARM: 7506/1: allow for ATAGS to be configured out when DT support is selected
Now that ATAGS support is well contained, we can easily remove it from
the kernel build if so desired. It has to explicitly be disabled, and
only when DT support is selected.
Note: disabling kernel ATAGS support does not prevent the usage of
CONFIG_ARM_ATAG_DTB_COMPAT.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| aa783b6fd60b3844e199b1c2d2f4068f3caa1358 |
|
01-Sep-2012 |
Nicolas Pitre <nicolas.pitre@linaro.org> |
ARM: 7505/1: split out ATAGS parsing
Make ATAGS parsing into a source file of its own, namely atags_parse.c.
Also rename compat.c to atags_compat.c to make it clearer what it is
about. Same for atags.c which is now atags_proc.c. Gather all the atags
function declarations into a common atags.h.
Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 5505b206ca006d0506d1d3b3c494aa86234f66e2 |
|
29-Jul-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: perf: move CPU-specific PMU handling code into separate file
This patch moves the CPU-specific PMU handling code out of perf_event.c
and into perf_event_cpu.c.
Signed-off-by: Will Deacon <will.deacon@arm.com>
|
| f0d1bc47953743aef9d2ed5326bc5973a3db08ab |
|
28-Jul-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: pmu: remove unused reservation mechanism
The PMU reservation mechanism was originally intended to allow OProfile
and perf-events to co-ordinate over access to the CPU PMU. Since then,
OProfile for ARM has moved to using perf as its backend, so the
reservation code is no longer used.
This patch removes the reservation code for the CPU PMU on ARM.
Signed-off-by: Will Deacon <will.deacon@arm.com>
|
| fa8bbb13ab49e77c00fa09e5504ec25b7176fb4b |
|
13-Mar-2012 |
Bryan Wu <bryan.wu@canonical.com> |
ARM: use new LEDS CPU trigger stub to replace old one
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bryan Wu <bryan.wu@canonical.com>
|
| 5290dc292915aaed6ae71ec3db5d4aa3285e7d51 |
|
03-May-2012 |
Thomas Gleixner <tglx@linutronix.de> |
arm: Use generic init_task
Same code. Use the generic version. The special Makefile treatment is
pointless anyway as init_task.o contains only data which is handled by
the linker script. So no point on being treated like head text.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Russell King <linux@arm.linux.org.uk>
Link: http://lkml.kernel.org/r/20120503085034.221811388@linutronix.de
|
| 022c03a2d650c641fa0f94dbc9d9ff77f8057678 |
|
11-Jan-2012 |
Marc Zyngier <marc.zyngier@arm.com> |
ARM: local timers: Add A15 architected timer support
Add support for the A15 generic timer and clocksource.
As the timer generates interrupts on a different PPI depending
on the execution mode (normal or secure), it is possible to
register two different PPIs.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
|
| 09f05d8529ff4aa92311c1a55ce35ac98cb59b8c |
|
18-Feb-2012 |
Rabin Vincent <rabin@rab.in> |
ARM: 7334/1: add jump label support
Add the arch-specific code to support jump labels for ARM and Thumb-2.
This code will only be activated on compilers that are capable of
building it. It has been tested with GCC 4.6 patched with the patch
from GCC bug 48637.
Cc: Jason Baron <jbaron@redhat.com>
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| b21d55e98ac2bbcbbeec9a8cb091f717fd95b072 |
|
18-Feb-2012 |
Rabin Vincent <rabin@rab.in> |
ARM: 7332/1: extract out code patch function from kprobes
Extract out the code patching code from kprobes so that it can be used
from the jump label code. Additionally, the separated code:
- Uses the IS_ENABLED() macros instead of the #ifdefs for THUMB2
support
- Unifies the two separate functions in kprobes, providing one function
that uses stop_machine() internally, and one that can be called from
stop_machine() directly
- Patches the text on all CPUs only on processors requiring software
broadcasting of cache operations
Acked-by: Jon Medhurst <tixy@yxit.co.uk>
Tested-by: Jon Medhurst <tixy@yxit.co.uk>
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| d82227cf8f0b42ff42c21ed47025fdf54cb1698d |
|
18-Feb-2012 |
Rabin Vincent <rabin@rab.in> |
ARM: 7331/1: extract out insn generation code from ftrace
Extract out the instruction generation code so that it can be used
for jump labels too.
Signed-off-by: Rabin Vincent <rabin@rab.in>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 6e747b4b83c2290b465aabd1ac006332430e2b2e |
|
01-Mar-2012 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: riscpc: move ecard.c to arch/arm/mach-rpc
RiscPC is the only platform using the Acorn expansion card support, so
move it into its mach-* directory.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| e1689795a784a7c41ac4cf9032794986b095a133 |
|
20-Mar-2012 |
Robert Lee <rob.lee@linaro.org> |
cpuidle: Add common time keeping and irq enabling
Make necessary changes to implement time keeping and irq enabling
in the core cpuidle code. This will allow the removal of these
functionalities from various platform cpuidle implementations whose
timekeeping and irq enabling follows the form in this common code.
Signed-off-by: Robert Lee <rob.lee@linaro.org>
Tested-by: Jean Pihet <j-pihet@ti.com>
Tested-by: Amit Daniel <amit.kachhap@linaro.org>
Tested-by: Robert Lee <rob.lee@linaro.org>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Deepthi Dharwar <deepthi@linux.vnet.ibm.com>
Acked-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Len Brown <len.brown@intel.com>
|
| c444dc0765d4ab87e920c1aeb1a5a622c9b661f9 |
|
10-Jan-2012 |
Ryan Mallon <rmallon@gmail.com> |
ep93xx: Move crunch code to mach-ep93xx directory
The crunch code in arch/arm/kernel is specific to the EP93xx. Move it
to the mach-ep93xx directory. This removes the need for the
EP93XX_SYSCON defines to be exported to arch/arm/kernel.
Signed-off-by: Ryan Mallon <rmallon@gmail.com>
Cc: Russell King <linux@arm.linux.org.uk>
Reviewed-by: Mika Westerberg <mika.westerberg@iki.fi>
Acked-by: Hartley Sweeten <hsweeten@visionengravers.com>
|
| 6905a65879b51d326396e63dfea40861a30bc17f |
|
18-Jan-2012 |
Marc Zyngier <marc.zyngier@arm.com> |
ARM: Make the sched_clock framework mandatory
All sched_clock() providers have been converted to the sched_clock
framework, which also provides a jiffy based implementation for
the platforms that do not provide a counter.
It is now possible to make the sched_clock framework mandatory,
effectively preventing new platforms to add new sched_clock()
functions, which would be detrimental to the single zImage work.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
|
| 0c9030deaf59d444f9e757ee73d6d81bfe2d3376 |
|
12-Dec-2011 |
Leif Lindholm <leif.lindholm@arm.com> |
ARM: 7206/1: Add generic ARM instruction set condition code checks.
This patch breaks the ARM condition checking code out of nwfpe/fpopcode.{ch}
into a standalone file for opcode operations. It also modifies the code
somewhat for coding style adherence, and adds some temporary variables for
increased readability.
Signed-off-by: Leif Lindholm <leif.lindholm@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| c9018aab8eee24b993c12c7aff7fc99d3d73f298 |
|
08-Aug-2011 |
Vincent Guittot <vincent.guittot@linaro.org> |
ARM: 7011/1: Add ARM cpu topology definition
The affinity between ARM processors is defined in the MPIDR register.
We can identify which processors are in the same cluster,
and which ones have performance interdependency. We can define the
cpu topology of ARM platform, that is then used by sched_mc and sched_smt.
The default state of sched_mc and sched_smt config is disable.
When enabled, the behavior of the scheduler can be modified with
sched_mc_power_savings and sched_smt_power_savings sysfs interfaces.
Changes since v4 :
* Remove unnecessary parentheses and blank lines
Changes since v3 :
* Update the format of printk message
* Remove blank line
Changes since v2 :
* Update the commit message and some comments
Changes since v1 :
* Update the commit message
* Add read_cpuid_mpidr in arch/arm/include/asm/cputype.h
* Modify header of arch/arm/kernel/topology.c
* Modify tests and manipulation of MPIDR's bitfields
* Modify the place and dependancy of the config
* Modify Noop functions
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 15e0d9e37c7fe9711b60f47221c394d45553ad8c |
|
01-Oct-2011 |
Arnd Bergmann <arnd@arndb.de> |
ARM: pm: let platforms select cpu_suspend support
Support for the cpu_suspend functions is only built-in
when CONFIG_PM_SLEEP is enabled, but omap3/4, exynos4
and pxa always call cpu_suspend when CONFIG_PM is enabled.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
| e8ce0eb5e2254b85415e4b58e73f24a5d13846a1 |
|
26-Aug-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: pm: preallocate a page table for suspend/resume
Preallocate a page table and setup an identity mapping for the MMU
enable code. This means we don't have to "borrow" a page table to
do this, avoiding complexities with L2 cache coherency.
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| c0cc6df16394da020242a54d577848f9edd9dc50 |
|
27-Aug-2011 |
Jon Medhurst <tixy@yxit.co.uk> |
ARM: kprobes: Add ARM instruction simulation test cases
Signed-off-by: Jon Medhurst <tixy@yxit.co.uk>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
| c7054aad538c18bc4c311e74a24cb2e205f02e04 |
|
27-Aug-2011 |
Jon Medhurst <tixy@yxit.co.uk> |
ARM: kprobes: Add Thumb instruction simulation test cases
Signed-off-by: Jon Medhurst <tixy@yxit.co.uk>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
| 9eed1797720ae633cf17b03dd804d8744f1d3b5c |
|
28-Aug-2011 |
Jon Medhurst <tixy@yxit.co.uk> |
ARM: kprobes: Add basic API tests
These test that the different kinds of probes can be successfully placed
into ARM and Thumb code and that the handlers are called correctly when
this code is executed.
Signed-off-by: Jon Medhurst <tixy@yxit.co.uk>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
| 2437170710c4a3dee137a65623960aa7ac82a32e |
|
19-Apr-2011 |
Jon Medhurst <tixy@yxit.co.uk> |
ARM: kprobes: Add Thumb instruction decoding stubs
Extend arch_prepare_kprobe to support probing of Thumb code. For
the actual decoding of Thumb instructions, stub functions are
added which currently just reject the probe.
Signed-off-by: Jon Medhurst <tixy@yxit.co.uk>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
| 0ab4c02ddae2e1d32d686a7773608f6c44fb2a83 |
|
06-Jul-2011 |
Jon Medhurst <tixy@yxit.co.uk> |
ARM: kprobes: Add kprobes-common.c
This file will contain the instruction decoding and emulation code
which is common to both ARM and Thumb instruction sets.
For now, we will just move over condition_checks from kprobes-arm.c
This table is also renamed to kprobe_condition_checks to avoid polluting
the public namespace with a too generic name.
Signed-off-by: Jon Medhurst <tixy@yxit.co.uk>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
| 691b2ff294a4787f3e54f5bb541570ac74bcb6f4 |
|
06-Jul-2011 |
Jon Medhurst <tixy@yxit.co.uk> |
ARM: kprobes: Rename kprobes-decode.c to kprobes-arm.c
This file contains decoding and emulation functions for the ARM
instruction set. As we will later be adding a file for Thumb and a
file with common decoding functions, this renaming makes things clearer.
Signed-off-by: Jon Medhurst <tixy@yxit.co.uk>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
|
| dc2eb928a1bcf6a48f40c1f2ff21b66bdbf91a3c |
|
23-May-2011 |
Dave Martin <dave.martin@linaro.org> |
ARM: 6938/1: fiq: Refactor {get,set}_fiq_regs() for Thumb-2
* To remove the risk of inconvenient register allocation decisions
by the compiler, these functions are separated out as pure
assembler.
* The apcs frame manipulation code is not applicable for Thumb-2
(and also not easily compatible). Since it's not essential to
have a full frame on these leaf assembler functions, the frame
manipulation is removed, in the interests of simplicity.
* Split up ldm/stm instructions to be compatible with Thumb-2,
as well as avoiding instruction forms deprecated on >= ARMv7.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 9eb8f6743b076b67f00776cda4330c802e157b41 |
|
28-Apr-2011 |
Grant Likely <grant.likely@secretlab.ca> |
arm/dt: Allow CONFIG_OF on ARM
Add some basic empty infrastructure for DT support on ARM.
v5: - Fix off-by-one error in size calculation of initrd
- Stop mucking with cmd_line, and load command line from dt into
boot_command_line instead which matches the behaviour of ATAGS booting
v3: - moved cmd_line export and initrd setup to this patch to make the
series bisectable.
- switched to alloc_bootmem_align() for allocation when
unflattening the device tree. memblock_alloc() was not the
right interface.
Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
|
| 29ea23ff905d07d8559bac69cca46f4bbf20038c |
|
02-Apr-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: Make consolidated PM sleep code depend on PM_SLEEP
CONFIG_PM is now set whenever we support either runtime PM in addition
to suspend and hibernate. This causes build errors when runtime PM is
enabled on a platform, but the CPU does not have the appropriate support
for suspend.
So, switch this code to use CONFIG_PM_SLEEP rather than CONFIG_PM to
allow runtime PM to be enabled without causing build errors.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| f6b0fa02e8b0708d17d631afce456524eadf87ff |
|
06-Feb-2011 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: pm: add generic CPU suspend/resume support
This adds core support for saving and restoring CPU coprocessor
registers for suspend/resume support. This contains support for suspend
with ARM920, ARM926, SA11x0, PXA25x, PXA27x, PXA3xx, V6 and V7 CPUs.
Tested on Assabet and Tegra 2.
Tested-by: Colin Cross <ccross@android.com>
Tested-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 112f38a4a31668eb6a7d91d128296a26afdf7c4b |
|
15-Dec-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: sched_clock: provide common infrastructure for sched_clock()
Provide common sched_clock() infrastructure for platforms to use to
create a 64-bit ns based sched_clock() implementation from a counter
running at a non-variable clock rate.
This implementation is based upon maintaining an epoch for the counter
and an epoch for the nanosecond time. When we desire a sched_clock()
time, we calculate the number of counter ticks since the last epoch
update, convert this to nanoseconds and add to the epoch nanoseconds.
We regularly refresh these epochs within the counter wrap interval.
We perform a similar calculation as above, and store the new epochs.
We read and write the epochs in such a way that sched_clock() can easily
(and locklessly) detect when an update is in progress, and repeat the
loading of these constants when they're known not to be stable. The
one caveat is that sched_clock() is not called in the middle of an
update. We achieve that by disabling IRQs.
Finally, if the clock rate is known at compile time, the counter to ns
conversion factors can be specified, allowing sched_clock() to be tightly
optimized. We ensure that these factors are correct by providing an
initialization function which performs a run-time check.
Acked-by: Peter Zijlstra <peterz@infradead.org>
Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Tested-by: Mikael Pettersson <mikpe@it.uu.se>
Tested-by: Eric Miao <eric.y.miao@gmail.com>
Tested-by: Olof Johansson <olof@lixom.net>
Tested-by: Jamie Iles <jamie@jamieiles.com>
Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 03b505eae6a276b8c38b6222694afb6cea10b1cc |
|
20-Dec-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: SMP: split out software TLB maintainence broadcasting
smp.c is becoming too large, so split out the TLB maintainence
broadcasting into a separate smp_tlb.c file.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| ef6c84454f8567d4968c210d7d194fb711ed3739 |
|
24-Nov-2010 |
Haojian Zhuang <haojian.zhuang@marvell.com> |
ARM: pxa: add iwmmx support for PJ4
iwmmxt is used in XScale, XScale3, Mohawk and PJ4 core. But the instructions
of accessing CP0 and CP1 is changed in PJ4. Append more files to support
iwmmxt in PJ4 core.
Signed-off-by: Zhou Zhu <zzhu3@marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
|
| 283a1b92e25fe3a62c766a042f96dad2eefa7d17 |
|
08-Nov-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: always build swp_emulate as ARMv7
swp_emulate is only used on ARMv7+, and includes ARMv7+ assembly
instructions. Allow the assembler to accept ARMv7 instructions,
but leave the compiler's code generation options alone.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 376cfa8730c08c0394d0aa1d4a80fd8c9971f323 |
|
09-Oct-2010 |
Tim Bird <tim.bird@am.sony.com> |
ARM: ftrace: function graph tracer support
Cc: Tim Bird <tim.bird@am.sony.com>
[rabin@rab.in: rebase on top of latest code,
keep code in ftrace.c instead of separate file,
check for ftrace_graph_entry also]
Signed-off-by: Rabin Vincent <rabin@rab.in>
|
| 64d2dc384e41e2b7acead6804593ddaaf8aad8e1 |
|
16-Sep-2010 |
Leif Lindholm <leif.lindholm@arm.com> |
ARM: 6396/1: Add SWP/SWPB emulation for ARMv7 processors
The SWP instruction was deprecated in the ARMv6 architecture,
superseded by the LDREX/STREX family of instructions for
load-linked/store-conditional operations. The ARMv7 multiprocessing
extensions mandate that SWP/SWPB instructions are treated as undefined
from reset, with the ability to enable them through the System Control
Register SW bit.
This patch adds the alternative solution to emulate the SWP and SWPB
instructions using LDREX/STREX sequences, and log statistics to
/proc/cpu/swp_emulation. To correctly deal with copy-on-write, it also
modifies cpu_v7_set_pte_ext to change the mappings to priviliged RO when
user RO.
Signed-off-by: Leif Lindholm <leif.lindholm@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 19852e59002fbba1c2c6ba0f154095a37ad2ac03 |
|
03-Sep-2010 |
Will Deacon <will.deacon@arm.com> |
ARM: 6358/1: hw-breakpoint: add HAVE_HW_BREAKPOINT to Kconfig
If we're targetting a v6 or v7 core and have at least software perf events
available, then automatically add support for hardware breakpoints.
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: S. Karthikeyan <informkarthik@gmail.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 67742c8168ed66fdd6cb5dc90e06c43cdc5bba07 |
|
10-May-2010 |
Mika Westerberg <mika.westerberg@iki.fi> |
ARM: 6120/1: kdump: implement copy_oldmem_page()
This function is used by vmcore code to read a page from the old
kernel memory.
Signed-off-by: Mika Westerberg <ext-mika.1.westerberg@nokia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 73a65b3f8587fa1c83768515ecc0bf6fa44ccdd1 |
|
19-Jan-2010 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
ARM: deprecate support for old way to pass kernel parameters
This was deprecated in 2001 and announced to live on for 5 years.
For now provide a kernel parameter for those who still need it.
Acked-by: Eric Miao <eric.miao@canonical.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
|
| 373b32abf9b33616ad94283461bb2ab49e8371d5 |
|
10-Jan-2010 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: move LED support code out of arch/arm/kernel/time.c
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 1b8873a0c6ec511870c106c80b94658f857c47f2 |
|
02-Feb-2010 |
Jamie Iles <jamie.iles@picochip.com> |
ARM: 5902/4: arm/perfevents: implement perf event support for ARMv6
This patch implements support for ARMv6 performance counters in the
Linux performance events subsystem. ARMv6 architectures that have the
performance counters should enable HW_PERF_EVENTS to get hardware
performance events support in addition to the software events.
Note: only ARM Ltd ARM cores are supported.
This implementation also provides an ARM PMU abstraction layer to allow
ARMv7 and others to be supported in the future by adding new a
'struct arm_pmu'.
Cc: Jean Pihet <jpihet@mvista.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jamie Iles <jamie.iles@picochip.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 0f4f0672ac950c96cffaf84a666d35e817d7c3ca |
|
02-Feb-2010 |
Jamie Iles <jamie.iles@picochip.com> |
ARM: 5899/2: arm: provide a mechanism to reserve performance counters
To add support for perf events and to allow the hardware counters to be
shared with oprofile, we need a way to reserve access to the pmu
(performance monitor unit). Platforms with PMU interrupts should
register the interrupts in arch/arm/kernel/pmu.c
Signed-off-by: Jamie Iles <jamie.iles@picochip.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 93fd03a8c6728b58879f8af20ffd55d9c32a778b |
|
09-Dec-2009 |
Catalin Marinas <catalin.marinas@arm.com> |
ARM: Add an earlyprintk debug console
This patch allows an earlyprintk console if CONFIG_DEBUG_LL is enabled,
using the printch asm function.
The patch is based on the original work by Sascha Hauer.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Pavel Machek <pavel@ucw.cz>
|
| c5d6c7708c3e58015b2e4e13e6cea02c8567a94e |
|
01-Dec-2009 |
Alexander Shishkin <virtuoso@slind.org> |
ARM: 5841/1: a driver for on-chip ETM and ETB
This driver implements support for on-chip Embedded Tracing Macrocell and
Embedded Trace Buffer. It allows to trigger tracing of kernel execution flow
and exporting trace output to userspace via character device and a sysrq
combo.
Trace output can then be decoded by a fairly simple open source tool [1]
which is already sufficient to get the idea of what the kernel is doing.
[1]: http://github.com/virtuoso/etm2human
Signed-off-by: Alexander Shishkin <virtuoso@slind.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 51b563fc93c8cb5bff1d67a0a71c374e4a4ea049 |
|
20-Sep-2009 |
Sam Ravnborg <sam@ravnborg.org> |
arm, cris, mips, sparc, powerpc, um, xtensa: fix build with bash 4.0
Albin Tonnerre <albin.tonnerre@free-electrons.com> reported:
Bash 4 filters out variables which contain a dot in them.
This happends to be the case of CPPFLAGS_vmlinux.lds.
This is rather unfortunate, as it now causes
build failures when using SHELL=/bin/bash to compile,
or when bash happens to be used by make (eg when it's /bin/sh)
Remove the common definition of CPPFLAGS_vmlinux.lds by
pushing relevant stuff to either Makefile.build or the
arch specific kernel/Makefile where we build the linker script.
This is also nice cleanup as we move the information out where
it is used.
Notes for the different architectures touched:
arm - we use an already exported symbol
cris - we use a config symbol aleady available
[Not build tested]
mips - the jiffies complexity has moved to vmlinux.lds.S where we need it.
Added a few variables to CPPFLAGS - they are only used by
the linker script.
[Not build tested]
powerpc - removed assignment that is not needed
[not build tested]
sparc - simplified it using $(BITS)
um - introduced a few new exported variables to deal with this
xtensa - added options to CPP invocation
[not build tested]
Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Mikael Starvik <starvik@axis.com>
Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Jeff Dike <jdike@addtoit.com>
Cc: Chris Zankel <chris@zankel.net>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
|
| bc581770cfdd8c17ea17d324dc05e2f9c599e7ca |
|
15-Sep-2009 |
Linus Walleij <linus.walleij@stericsson.com> |
ARM: 5580/2: ARM TCM (Tightly-Coupled Memory) support v3
This adds the TCM interface to Linux, when active, it will
detect and report TCM memories and sizes early in boot if
present, introduce generic TCM memory handling, provide a
generic TCM memory pool and select TCM memory for the U300
platform.
See the Documentation/arm/tcm.txt for documentation.
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 4bf1fa5a34aa2dd0d2cc58f0fc213a2e22d007a4 |
|
21-Jul-2009 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
[ARM] 5613/1: implement CALLER_ADDRESSx
From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
As __builtin_return_address(n) doesn't work for ARM with n > 0, the
kernel needs its own implementation.
This fixes many warnings saying:
warning: unsupported argument to '__builtin_return_address'
The new methods and walk_stackframe must not be instrumented because
CALLER_ADDRESSx is used in the various tracers and tracing the tracer is
a bad idea.
What's currently missing is an implementation using unwind tables. This
is not fatal though, it's just that the tracers don't get enough
information to be really useful.
Note that if both ARM_UNWIND and FRAME_POINTER are enabled,
walk_stackframe uses unwind information. So in this case the same
implementation is used as when FRAME_POINTER is disabled.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| f32f4ce25745209f16a5a6cef7442144b596c68a |
|
16-May-2009 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] smp: allow re-use of realview localtimer TWD support
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| a8cbcd92bd4bf893085eddf7f58e63ea98503d94 |
|
16-May-2009 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] smp: separate SCU support code from realview
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 40305a583a3e080a8d1aa126fa810480ec8cbabd |
|
26-Feb-2009 |
Eric Miao <eric.miao@marvell.com> |
[ARM] pxa: add iWMMXt support for pxa168
Signed-off-by: Eric Miao <eric.miao@marvell.com>
|
| adf8b37bafc1495393201a2ae4235846371870d0 |
|
12-Feb-2009 |
Catalin Marinas <catalin.marinas@arm.com> |
[ARM] 5386/2: unwind: Add Makefile and Kconfig entries for ARM stack unwinding
This patch also makes the frame pointer default to y only if
!ARM_UNWIND. LOCKDEP no longer selects FRAME_POINTER if ARM_UNWIND is
enabled.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 8ec53663d2698076468b3e1edc4e1b418bd54de3 |
|
07-Sep-2008 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Improve non-executable support
Add support for detecting non-executable stack binaries, and adjust
permissions to prevent execution from data and stack areas. Also,
ensure that READ_IMPLIES_EXEC is enabled for older CPUs where that
is true, and for any executable-stack binary.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 5cbad0ebf45c5417104b383dc0e34f64fa7f2473 |
|
20-Feb-2008 |
Jason Wessel <jason.wessel@windriver.com> |
kgdb: support for ARCH=arm
This patch adds the ARCH=arm specific a kgdb backend, originally
written by Deepak Saxena <dsaxena@plexity.net> and George Davis
<gdavis@mvista.com>. Geoff Levand <geoffrey.levand@am.sony.com>,
Nicolas Pitre, Manish Lachwani, and Jason Wessel have contributed
various fixups here as well.
The KGDB patch makes one change to the core ARM architecture such that
the traps are initialized early for use with the debugger or other
subsystems.
[ mingo@elte.hu: small cleanups. ]
[ ben-linux@fluff.org: fixed early_trap_init ]
Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
Acked-by: Deepak Saxena <dsaxena@plexity.net>
|
| 014c257cce65e9d1cd2d28ec1c89a37c536b151d |
|
31-May-2008 |
Abhishek Sagar <sagar.abhishek@gmail.com> |
ftrace: core support for ARM
Core ftrace support for the ARM architecture, which includes support
for dynamic function tracing.
Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
|
| d7f864be8323e5394040e2877594645b0e7da85d |
|
18-Apr-2008 |
Catalin Marinas <catalin.marinas@arm.com> |
ARMv7: Add support for the ThumbEE state saving/restoring
This patch adds the detection and handling of the ThumbEE extension on
ARMv7 CPUs.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|
| 64ac24e738823161693bf791f87adc802cf529ff |
|
08-Mar-2008 |
Matthew Wilcox <matthew@wil.cx> |
Generic semaphore implementation
Semaphores are no longer performance-critical, so a generic C
implementation is better for maintainability, debuggability and
extensibility. Thanks to Peter Zijlstra for fixing the lockdep
warning. Thanks to Harvey Harrison for pointing out that the
unlikely() was unnecessary.
Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
Acked-by: Ingo Molnar <mingo@elte.hu>
|
| 4cd9d6f774c7e0578bbc4409d4490d8f2097d40a |
|
02-Jan-2008 |
Richard Purdie <rpurdie@rpsys.net> |
[ARM] 4736/1: Export atags to userspace and allow kexec to use customised atags
Currently, the atags used by kexec are fixed to the ones originally used
to boot the kernel. This is less than ideal as changing the commandline,
initrd and other options would be a useful feature.
This patch exports the atags used for the current kernel to userspace
through an "atags" file in procfs. The presence of the file is
controlled by its own Kconfig option and cleans up several ifdef blocks
into a separate file. The tags for the new kernel are assumed to be at
a fixed location before the kernel image itself. The location of the
tags used to boot the original kernel is unimportant and no longer
saved.
Based on a patch from Uli Luckas <u.luckas@road.de>
Signed-off-by: Richard Purdie <rpurdie@rpsys.net>
Acked-by: Uli Luckas <u.luckas@road.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 24ba613c9d6cad315f484e658288db152f1dc447 |
|
12-Jun-2007 |
Abhishek Sagar <sagar.abhishek@gmail.com> |
ARM kprobes: core code
This is a full implementation of Kprobes including Jprobes and
Kretprobes support.
This ARM implementation does not follow the usual kprobes double-
exception model. The traditional model is where the initial kprobes
breakpoint calls kprobe_handler(), which returns from exception to
execute the instruction in its original context, then immediately
re-enters after a second breakpoint (or single-stepping exception)
into post_kprobe_handler(), each time the probe is hit.. The ARM
implementation only executes one kprobes exception per hit, so no
post_kprobe_handler() phase. All side-effects from the kprobe'd
instruction are resolved before returning from the initial exception.
As a result, all instructions are _always_ effectively boosted
regardless of the type of instruction, and even regardless of whether
or not there is a post-handler for the probe.
Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: Quentin Barnes <qbarnes@gmail.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
|
| 35aa1df4328340f38edc46f00837f08d33d49f63 |
|
12-Jun-2007 |
Quentin Barnes <qbarnes@gmail.com> |
ARM kprobes: instruction single-stepping support
This is the code implementing instruction single-stepping for kprobes
on ARM.
To get around the limitation of no Next-PC and no hardware single-
stepping, all kprobe'd instructions are split into three camps:
simulation, emulation, and rejected. "Simulated" instructions are
those instructions which behavior is reproduced by straight C code.
"Emulated" instructions are ones that are copied, slightly altered
and executed directly in the instruction slot to reproduce their
behavior. "Rejected" instructions are ones that could be simulated,
but work hasn't been put into simulating them. These instructions
should be very rare, if not unencountered, in the kernel. If ever
needed, code could be added to simulate them.
One might wonder why this and the ptrace singlestep facility are not
sharing some code. Both approaches are fundamentally different because
the ptrace code regains control after the stepped instruction by installing
a breakpoint after the instruction itself, and possibly at the location
where the instruction might be branching to, instead of simulating or
emulating the target instruction.
The ptrace approach isn't suitable for kprobes because the breakpoints
would have to be moved back, and the icache flushed, everytime the
probe is hit to let normal code execution resume, which would have a
significant performance impact. It is also racy on SMP since another
CPU could, with the right timing, sail through the probe point without
being caught. Because ptrace single-stepping always result in a
different process to be scheduled, the concern for performance is much
less significant.
On the other hand, the kprobes approach isn't (currently) suitable for
ptrace because it has no provision for proper user space memory
protection and translation, and even if that was implemented, the gain
wouldn't be worth the added complexity in the ptrace path compared to
the current approach.
So, until kprobes does support user space, both kprobes and ptrace are
best kept independent and separate.
Signed-off-by: Quentin Barnes <qbarnes@gmail.com>
Signed-off-by: Abhishek Sagar <sagar.abhishek@gmail.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
|
| f16fb1ecc5a1cb2f7cc595179d1fe55e711e599f |
|
28-Apr-2007 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Add stacktrace support and make oprofile use it
Add support for stacktrace. Use the new stacktrace code with
oprofile instead of it's version; there's no point having
multiple versions of stacktracing in the kernel.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| c587e4a6a4d808fd2a1c4e7fb2d5a3a31e300d23 |
|
06-Feb-2007 |
Richard Purdie <rpurdie@rpsys.net> |
[ARM] 4137/1: Add kexec support
Add kexec support to ARM.
Improvements like commandline handling could be made but this patch gives
basic functional support. It uses the next available syscall number, 347.
Once the syscall number is known, userspace support will be
finalised/submitted to kexec-tools, various patches already exist.
Originally based on a patch by Maxim Syrchin but updated and forward
ported by various people.
Signed-off-by: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 75e7153abd220f1c4a731a9613fb705485b56aa8 |
|
09-Feb-2007 |
Ralf Baechle <ralf@linux-mips.org> |
[APM] ARM: Convert to use shared APM emulation.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| afe4b25e7d9260d85fccb2d13c9933a987bdfc8a |
|
03-Dec-2006 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] 3881/4: xscale: clean up cp0/cp1 handling
XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)
Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch. Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.
CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.
This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.' This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.
These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 863dab453b869136453944bda63e20b6ed39c5ef |
|
28-Aug-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Add Integrator support for glibc outb() and friends
Add the necessary call to register_isa_ports() so that glibc knows
where these are found on Integrator platforms.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| ae95bfbb2b67eba5d67a0478a8715682a87e2616 |
|
01-Jul-2006 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
Patch from Lennert Buytenhek
This patch makes the iWMMXt context switch hook use the generic
thread notifier infrastructure that was recently merged in commit
d6551e884cf66de072b81f8b6d23259462c40baf.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| c17fad11f3105ca4d5bbb2686725aad208f5ead4 |
|
28-Jun-2006 |
Lennert Buytenhek <buytenh@wantstofly.org> |
[ARM] 3370/2: ep93xx: add crunch support
Patch from Lennert Buytenhek
Add the necessary kernel bits for crunch task switching.
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 3b920cef3470b7199acd2dc26e09fb9291131976 |
|
24-Apr-2006 |
Hyok S. Choi <hyok.choi@samsung.com> |
[ARM] nommu: trivial fixups for head-nommu.S and the Makefile
This patch fix compilation problem of start-up codes.
(head-nommu.S, arch/arm/kernel/Makefile)
Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 687ad0191488a067b3b3cc94f670cc21f93811e1 |
|
14-Jan-2006 |
Nicolas Pitre <nico@cam.org> |
[ARM] 3109/1: old ABI compat: syscall wrappers for ABI impedance matching
Patch from Nicolas Pitre
The difference between EABI and the legacy ABI may affect either
structure member alignment and/or argument register selection.
The patch has the details.
Included are wrappers for the following syscalls:
sys_stat64
sys_lstat64
sys_fstat64
sys_fcntl64
sys_epoll_ctl
sys_epoll_wait
sys_ipc
sys_semop
sys_semtimedop
sys_pread64
sys_pwrite64
sys_truncate64
sys_ftruncate64
sys_readahead
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 065909b91581cf2438d901a7811a82af3476bdab |
|
04-Jan-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Refine selection of ISA_DMA_API and generic dma.c code
ISA_DMA_API tells the rest of the kernel if the ISA DMA API is
available. Select this symbol only on machine types which make
use of the ISA DMA API.
Make building of arch/arm/kernel/dma.c depend on this symbol -
if a machine does not support the ISA DMA API, it's pointless
building this file.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 9d4f13e531b4722fe40cc8e28c02a495bdd49267 |
|
03-Jan-2006 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[ARM] Make kernel link address depend on PAGE_OFFSET
We are coding the kernel link address into the makefiles, which is
invisibly dependent on PAGE_OFFSET. If PAGE_OFFSET is changed, the
makefiles also need to be changed.
Make adjustments such that the makefiles encode just the offset from
PAGE_OFFSET for the kernel link address, and use PAGE_OFFSET in the
linker scripts directly.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 37d07b72ef58f2d5ec7701ab75084fbeee0e503e |
|
29-Oct-2005 |
Nicolas Pitre <nico@cam.org> |
[ARM] 3061/1: cleanup the XIP link address mess
Patch from Nicolas Pitre
Since vmlinux.lds.S is preprocessed, we can use the defines already
present in asm/memory.h (allowed by patch #3060) for the XIP kernel link
address instead of relying on a duplicated Makefile hardcoded value, and
also get rid of its dependency on awk to handle it at the same time.
While at it let's clean XIP stuff even further and make things clearer
in head.S with a nice code reduction.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| 34c8eacab670e578a2aaafdf1061efd214b2f639 |
|
20-Jun-2005 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[PATCH] ARM: Remove obsolete arch/arm/kernel/arch.c
This is not used anymore - RiscPC now contains the necessary
supporting code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
| bce495d865829d7a1d8102a834d3e3af32616567 |
|
26-Apr-2005 |
Russell King <rmk@dyn-67.arm.linux.org.uk> |
[PATCH] ARM: make entry*.S includes more logical
Move common includes to entry-header, and file specific includes
to the relevant file.
Signed-off-by: Russell King <rmk@arm.linux.org.uk>
|
| 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 |
|
17-Apr-2005 |
Linus Torvalds <torvalds@ppc970.osdl.org> |
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
|