| a0524acc94c91c72c2968a76eddc6f3afe82f9f2 |
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11-Jul-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: tegra: Sort includes alphabetically
If these aren't sorted alphabetically, then the logical choice is to
append new ones, however that creates a lot of potential for conflicts
because every change will then add new includes in the same location.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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| b4f173752a56187bd55752b0474429202f2ab1d3 |
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06-May-2013 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: disable LP2 cpuidle state if PCIe is enabled
Tegra20 HW appears to have a bug such that PCIe device interrupts,
whether they are legacy IRQs or MSI, are lost when LP2 is enabled. To
work around this, simply disable LP2 if any PCIe devices with interrupts
are present. Detect this via the IRQ domain map operation. This is
slightly over-conservative; if a device with an interrupt is present but
the driver does not actually use them, LP2 will still be disabled.
However, this is a reasonable trade-off which enables a simpler
workaround.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
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| 8f6a0b6528820f9efec36e5843181cc178fa9de8 |
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04-Jun-2013 |
Joseph Lo <josephl@nvidia.com> |
ARM: tegra: don't pass CPU ID to tegra_{set,clear}_cpu_in_lp2
tegra_{set,clear}_cpu_in_lp2 can easily determine which CPU ID they are
running on; there is no need to pass the CPU ID into those functions.
So, remove their CPU ID function parameter.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| bf91add4a0feb7a8624a1f6b3fd4d6dbe9dce1bc |
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04-Jun-2013 |
Joseph Lo <josephl@nvidia.com> |
ARM: tegra: hook tegra_tear_down_cpu function in the PM suspend init function
The tegra_tear_down_cpu was used to cut off the CPU rail for various Tegra
SoCs. Hooking it in the PM suspend init function and making the CPUidle
driver more generic.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| c5106c9dea9a6022ab84c6cb1d4a0b19fc5af0e2 |
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23-Apr-2013 |
Daniel Lezcano <daniel.lezcano@linaro.org> |
ARM: tegra: cpuidle: use init/exit common routine for tegra2
Remove the duplicated code and use the cpuidle common code for initialization.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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| 554c06ba3ee29cf453fca17e9e61120b75aa476d |
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23-Apr-2013 |
Daniel Lezcano <daniel.lezcano@linaro.org> |
cpuidle: remove en_core_tk_irqen flag
The en_core_tk_irqen flag is set in all the cpuidle driver which
means it is not necessary to specify this flag.
Remove the flag and the code related to it.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: Kevin Hilman <khilman@linaro.org> # for mach-omap2/*
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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| 0697598db56179dbaa9376f29703f6b94751a73f |
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03-Apr-2013 |
Daniel Lezcano <daniel.lezcano@linaro.org> |
ARM: tegra: cpuidle: remove useless initialization
dev->state_count is initialized automatically by
cpuidle_register_device().
When drv->state_count is equal to dev->state_count, no need to init
this field, so removing it.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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| 14ad7a119b85b0ba77868882194ab5b16203b2c9 |
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03-Apr-2013 |
Daniel Lezcano <daniel.lezcano@linaro.org> |
ARM: tegra2: cpuidle: change driver initialization
Initialize the idle states directly in the driver structure.
That prevents extra structure declaration and memcpy at init time.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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| 4d82d0587b4a964ea3a7c73aa044b433000527dd |
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02-Apr-2013 |
Joseph Lo <josephl@nvidia.com> |
ARM: tegra: cpuidle: remove redundant parameters for powered-down mode
After the patch series for system suspending support, tegra_idle_lp2_last()
no longer uses its parameters cpu_on_time or cpu_off_time, so remove them.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| 1d328606c66b9bb1c0552f585943d596f37ae3b9 |
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16-Jan-2013 |
Joseph Lo <josephl@nvidia.com> |
ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
The "powered-down" cpuidle mode of Tegra20 needs the CPU0 be the last one
core to go into this mode before other core. The coupled cpuidle framework
can help to sync the MPCore to coupled state then go into "powered-down"
idle mode together. The driver can just assume the MPCore come into
"powered-down" mode at the same time. No need to take care if the CPU_0
goes into this mode along and only can put it into safe idle mode (WFI).
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI for waiting CPU0 in the same state.
When the CPU0 requests powered-down state, it attempts to put the secondary
CPU into reset to prevent it from waking up. Then power down both CPUs
together and power off the cpu rail.
Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".
Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Colin Cross <ccross@android.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| 5c1350bdfcebf47b3b6f83d62e5860259858a54a |
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15-Jan-2013 |
Joseph Lo <josephl@nvidia.com> |
ARM: tegra20: cpuidle: add powered-down state for secondary CPU
The powered-down state of Tegra20 requires power gating both CPU cores.
When the secondary CPU requests to enter powered-down state, it saves
its own contexts and then enters WFI. The Tegra20 had a limition to
power down both CPU cores. The secondary CPU must waits for CPU0 in
powered-down state too. If the secondary CPU be woken up before CPU0
entering powered-down state, then it needs to restore its CPU states
and waits for next chance.
Be aware of that, you may see the legacy power state "LP2" in the code
which is exactly the same meaning of "CPU power down".
Based on the work by:
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| 0b25e25bef0e03c0465c3eb1119b32cb906db689 |
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31-Oct-2012 |
Joseph Lo <josephl@nvidia.com> |
ARM: tegra: cpuidle: separate cpuidle driver for different chips
The different Tegra chips may have different CPU idle states and data.
Individual CPU idle driver make it more easy to maintain.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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