| c090e111633cd82e4e0f72c7e964460676ad1250 |
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11-Jul-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: tegra: Always lock the CPU reset vector
Currently the reset vector is not locked on Tegra20 because the hardware
doesn't support it. However in order not to depend on the chip ID, which
becomes available only later in the boot process, we set the bit anyway.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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| 783c8f4c84451bc444e314a71b447239c6ef6fd9 |
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12-Jun-2014 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
soc/tegra: Add efuse driver for Tegra
Implement fuse driver for Tegra20, Tegra30, Tegra114 and Tegra124. This
replaces functionality previously provided in arch/arm/mach-tegra, which
is removed in this patch.
While at it, move the only user of the global tegra_revision variable
over to tegra_sku_info.revision and export tegra_fuse_readl() to allow
drivers to read calibration fuses.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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| 304664eab93f9e95a8d28fbd9702ede88bb10cc5 |
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11-Jul-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: tegra: Use a function to get the chip ID
Instead of using a simple variable access to get at the Tegra chip ID,
use a function so that we can run additional code. This can be used to
determine where the chip ID is being accessed without being available.
That in turn will be handy for resolving boot sequence dependencies in
order to convert more code to regular initcalls rather than a sequence
fixed by Tegra SoC setup code.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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| a0524acc94c91c72c2968a76eddc6f3afe82f9f2 |
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11-Jul-2014 |
Thierry Reding <treding@nvidia.com> |
ARM: tegra: Sort includes alphabetically
If these aren't sorted alphabetically, then the logical choice is to
append new ones, however that creates a lot of potential for conflicts
because every change will then add new includes in the same location.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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| 265c89c994611e75943563e9b741cb8ae04a43af |
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24-Nov-2013 |
Alexandre Courbot <acourbot@nvidia.com> |
ARM: tegra: set CPU reset handler using firmware
Use a firmware operation to set the CPU reset handler and only resort to
doing it ourselves if there is none defined.
This supports the booting of secondary CPUs on devices using a TrustZone
secure monitor.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| ad14ecee4d868a54556e40cdc3df7fe78e3ab9d0 |
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24-Nov-2013 |
Alexandre Courbot <acourbot@nvidia.com> |
ARM: tegra: split setting of CPU reset handler
Not all Tegra devices can set the CPU reset handler in the same way.
In particular, devices using a TrustZone secure monitor cannot set it
up directly and need to ask the firmware to do it.
This patch separates the act of setting the reset handler from its
preparation, so the former can be implemented in a different way.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| fddb770dbe468876ea6562e21f817813baa15082 |
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21-Aug-2013 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: move resume vector define to irammap.h
irammap.h's purpose is to define the layout/usage of IRAM. As such,
TEGRA_IRAM_CODE_AREA should have been added there rather than iomap.h.
Move the define, and rename it something more descriptive.
Cc: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| 5b795d051c61862cebf4f1d55edab6e9b3383b44 |
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12-Aug-2013 |
Joseph Lo <josephl@nvidia.com> |
ARM: tegra: add common resume handling code for LP1 resuming
Add support to the Tegra CPU reset vector to detect whether the CPU is
resuming from LP1 suspend state. If it is, branch to the LP1-specific
resume code.
When Tegra enters the LP1 suspend state, the SDRAM controller is placed
into a self-refresh state. For this reason, we must place the LP1 resume
code into IRAM, so that it is accessible before SDRAM access has been
re-enabled.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| 9e32366fe51fea464adb21c244f372d55207e13c |
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04-Jan-2013 |
Joseph Lo <josephl@nvidia.com> |
ARM: tegra: make device can run on UP
The reset handler code is used for either UP or SMP. To make Tegra device
can compile for UP. It needs to be moved to another file that is not SMP
only. This is because the reset handler also be needed by CPU idle
"powered-down" mode. So we also need to put the reset handler init function
in non-SMP only and init them always.
And currently the implementation of the reset handler to know which CPU is
OK to bring up was identital with "cpu_present_mask". But the
"cpu_present_mask" did not initialize yet when the reset handler init
function was moved to init early function. We use the "cpu_possible_mask"
to replace "cpu_present_mask". Then it can work on both UP and SMP case.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
[swarren: dropped the move of v7_invalidate_l1() from one file to another,
to avoid conflicts with Pavel's cleanup of this function, adjust Makefile
so each line only contains 1 file.]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| d3f293656c07a1147c11e8c8774d7955a903cee0 |
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31-Oct-2012 |
Joseph Lo <josephl@nvidia.com> |
ARM: tegra: cpuidle: add CPU resume function
The CPU suspending on Tegra means CPU power gating. We add a resume
function for taking care the CPUs that resume from power gating status.
This function was been hooked to the reset handler. We take care
everything here before go into kernel.
Be aware of that, you may see the legacy power status "LP2" in the code
which is exactly the same meaning of "CPU power down".
Based on the work by:
Scott Williams <scwilliams@nvidia.com>
Colin Cross <ccross@android.com>
Gary King <gking@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| bb1de8877c960b3b3e1c8337730df970b262fd44 |
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04-Oct-2012 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: move irammap.h to mach-tegra
Nothing outside mach-tegra uses this file, so there's no need for it to
be in <mach/>.
Since uncompress.h and debug-macro.S remain in include/mach, they need
to include "../../irammap.h" becaue of this change. Both these usages
will be removed shortly, when Tegra's DEBUG_LL implementation is updated
not to pass information through IRAM.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| 2be39c079d692a07b55c8795051d40c0c94a3633 |
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04-Oct-2012 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: move iomap.h to mach-tegra
Nothing outside mach-tegra uses this file, so there's no need for it to
be in <mach/>.
Since uncompress.h and debug-macro.S remain in include/mach, they need
to include "../../iomap.h" becaue of this change. uncompress.h will soon
be deleted in later multi-platform/single-zImage patches. debug-macro.S
will need to continue to include this header using an explicit relative
path, to avoid duplicating the physical->virtual address mapping that
iomap.h dictates.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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| 6355f25ed965421725d92cf719fc63008690ca1c |
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18-Jun-2012 |
Stephen Warren <swarren@nvidia.com> |
ARM: tegra: make tegra_cpu_reset_handler_enable() __init
This solves a section mismatch warning. I hadn't noticed this before,
because my compiler was inlining tegra_cpu_reset_handler_enable() inside
tegra_cpu_reset_handler_init(), which is already __init, but I switched
compilers and it stopped doing that.
Cc: <stable@kernel.org> # v3.4
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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| b36ab9754efbd7429d214b3b03dc9843882571bd |
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10-Feb-2012 |
Peter De Schrijver <pdeschrijver@nvidia.com> |
ARM: tegra: rework Tegra secondary CPU core bringup
Prepare the Tegra secondary CPU core bringup code for other Tegra variants.
The reset handler is also generalized to allow for future introduction of
powersaving modes which turn off the CPU cores.
Based on work by:
Scott Williams <scwilliams@nvidia.com>
Chris Johnson <cwj@nvidia.com>
Colin Cross <ccross@android.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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