| beeab2a441619417a1cdbd06d922ea669eb92931 |
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22-Jan-2015 |
Laura Abbott <lauraa@codeaurora.org> |
UPSTREAM: arm64: use fixmap for text patching
When kernel text is marked as read only, it cannot be modified directly.
Use a fixmap to modify the text instead in a similar manner to
x86 and arm.
Reviewed-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Kees Cook <keescook@chromium.org>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 2f896d5866107e2926dcdec34a7d40bc56dd2951)
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Bug: 24475017
Change-Id: I6587989d6eae6d7e366f84cbd3f9cb3acb6bb154
Signed-off-by: Kees Cook <keescook@google.com>
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| cbefb97b6d7961359f2af89d77b8d5ab77f45528 |
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18-Nov-2014 |
Punit Agrawal <punit.agrawal@arm.com> |
arm64: Emulate CP15 Barrier instructions
The CP15 barrier instructions (CP15ISB, CP15DSB and CP15DMB) are
deprecated in the ARMv7 architecture, superseded by ISB, DSB and DMB
instructions respectively. Some implementations may provide the
ability to disable the CP15 barriers by disabling the CP15BEN bit in
SCTLR_EL1. If not enabled, the encodings for these instructions become
undefined.
To support legacy software using these instructions, this patch
register hooks to -
* emulate CP15 barriers and warn the user about their use
* toggle CP15BEN in SCTLR_EL1
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Change-Id: I16e70c2505489a4d88c898759256df20d2f4c21d
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| f2e97ae6b98e61fa4f1539a47661baef41992b04 |
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18-Nov-2014 |
Punit Agrawal <punit.agrawal@arm.com> |
arm64: Port SWP/SWPB emulation support from arm
The SWP instruction was deprecated in the ARMv6 architecture. The
ARMv7 multiprocessing extensions mandate that SWP/SWPB instructions
are treated as undefined from reset, with the ability to enable them
through the System Control Register SW bit. With ARMv8, the option to
enable these instructions through System Control Register was dropped
as well.
To support legacy applications using these instructions, port the
emulation of the SWP and SWPB instructions from the arm port to arm64.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Change-Id: I5ef56cac623d58a210e67c705aa5f5f63e784c0a
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| fe5bff06524b1b40d269bd00fcbf696713b2d04e |
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18-Nov-2014 |
Punit Agrawal <punit.agrawal@arm.com> |
arm64: Add support for hooks to handle undefined instructions
Add support to register hooks for undefined instructions. The handlers
will be called when the undefined instruction and the processor state
(as contained in pstate) match criteria used at registration.
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Change-Id: Id63a0ddec8b6af448d9512b259e6e7edaee7abff
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| 899d5933b2dd2720f2b20b01eaa07871aa6ad096 |
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11-Nov-2014 |
William Cohen <wcohen@redhat.com> |
Correct the race condition in aarch64_insn_patch_text_sync()
When experimenting with patches to provide kprobes support for aarch64
smp machines would hang when inserting breakpoints into kernel code.
The hangs were caused by a race condition in the code called by
aarch64_insn_patch_text_sync(). The first processor in the
aarch64_insn_patch_text_cb() function would patch the code while other
processors were still entering the function and incrementing the
cpu_count field. This resulted in some processors never observing the
exit condition and exiting the function. Thus, processors in the
system hung.
The first processor to enter the patching function performs the
patching and signals that the patching is complete with an increment
of the cpu_count field. When all the processors have incremented the
cpu_count field the cpu_count will be num_cpus_online()+1 and they
will return to normal execution.
Fixes: ae16480785de arm64: introduce interfaces to hotpatch kernel and module code
Signed-off-by: William Cohen <wcohen@redhat.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| a9ae04c9faeff1ad617e4f4492af3143d8c5ad9b |
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16-Sep-2014 |
Mark Brown <broonie@kernel.org> |
arm64: insn: Add return statements after BUG_ON()
Following a recent series of enhancements to the insn code the ARMv8
allnoconfig build has been generating a large number of warnings in the
form of:
arch/arm64/kernel/insn.c:689:8: warning: 'insn' may be used uninitialized in this function [-Wmaybe-uninitialized]
This is because BUG() and related macros can be compiled out so we get
execution paths which normally result in a panic compiling out to noops
instead.
I wasn't able to immediately identify a sensible return value to use in
these cases so just return AARCH64_BREAK_FAULT - this is all "should
never happen" code so hopefully it never has a practical impact.
Signed-off-by: Mark Brown <broonie@kernel.org>
[catalin.marinas@arm.com: AARCH64_BREAK_FAULT definition contributed by Daniel Borkmann]
[catalin.marinas@arm.com: replace return 0 with AARCH64_BREAK_FAULT]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| 5e6e15a2c4b529fd3cbf367b734842c4d8f6b0fa |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_logical_shifted_reg()
Introduce function to generate logical (shifted register)
instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 27f95ba59b34509dc8afa2f89ad51c044df9d7c7 |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_data3()
Introduce function to generate data-processing (3 source) instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 6481063989283f7cbeb0b6c38506ba4dd319f93a |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_data2()
Introduce function to generate data-processing (2 source) instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 546dd36b44613c770655531ee3ada6a9e9907d71 |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_data1()
Introduce function to generate data-processing (1 source) instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 5fdc639a7a5b187f75b7408ee7ae9f9c06771218 |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_add_sub_shifted_reg()
Introduce function to generate add/subtract (shifted register)
instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 6098f2d5c7a349d388499503bb129d0088870dd6 |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_movewide()
Introduce function to generate move wide (immediate) instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 4a89d2c98e1efadd135015668c499ae1bbd2131f |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_bitfield()
Introduce function to generate bitfield instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 9951a157fa678db0ec92e5fc4c6320c038ffb67e |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_add_sub_imm()
Introduce function to generate add/subtract (immediate) instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 1bba567d0f3050e33b4dd1404fdcbceaf5a73034 |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_load_store_pair()
Introduce function to generate load/store pair instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 17cac179888166a4e8e252d00ad511e999859293 |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_load_store_reg()
Introduce function to generate load/store (register offset)
instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 345e0d35ecdd7aff31881462a6f7786fda3241d9 |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_cond_branch_imm()
Introduce function to generate conditional branch (immediate)
instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| c0cafbae20d2878883ec3c06d6ea30ff38a6bf92 |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_branch_reg()
Introduce function to generate unconditional branch (register)
instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 617d2fbc45233bed182accd3507d0df4d213492c |
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27-Aug-2014 |
Zi Shen Lim <zlim.lnx@gmail.com> |
arm64: introduce aarch64_insn_gen_comp_branch_imm()
Introduce function to generate compare & branch (immediate)
instructions.
Signed-off-by: Zi Shen Lim <zlim.lnx@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
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| 5c5bf25d4f7a950382f94fc120a5818197b48fe9 |
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07-Jan-2014 |
Jiang Liu <liuj97@gmail.com> |
arm64: introduce aarch64_insn_gen_{nop|branch_imm}() helper functions
Introduce aarch64_insn_gen_{nop|branch_imm}() helper functions, which
will be used to implement jump label on ARM64.
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jiang Liu <liuj97@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| c84fced8d990dd86c523233d38b4685a52a4fc3f |
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07-Jan-2014 |
Jiang Liu <liuj97@gmail.com> |
arm64: move encode_insn_immediate() from module.c to insn.c
Function encode_insn_immediate() will be used by other instruction
manipulate related functions, so move it into insn.c and rename it
as aarch64_insn_encode_immediate().
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jiang Liu <liuj97@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| ae16480785de1da84f21d1698f304a52f9790c49 |
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07-Jan-2014 |
Jiang Liu <liuj97@gmail.com> |
arm64: introduce interfaces to hotpatch kernel and module code
Introduce three interfaces to patch kernel and module code:
aarch64_insn_patch_text_nosync():
patch code without synchronization, it's caller's responsibility
to synchronize all CPUs if needed.
aarch64_insn_patch_text_sync():
patch code and always synchronize with stop_machine()
aarch64_insn_patch_text():
patch code and synchronize with stop_machine() if needed
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jiang Liu <liuj97@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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| b11a64a48ccc7ca0ceb33544206934fbd3cdbb22 |
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07-Jan-2014 |
Jiang Liu <liuj97@gmail.com> |
arm64: introduce basic aarch64 instruction decoding helpers
Introduce basic aarch64 instruction decoding helper
aarch64_get_insn_class() and aarch64_insn_hotpatch_safe().
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jiang Liu <liuj97@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
|