| 7b626d93453903e36cbc0189f4cbf7b195e2c037 |
|
08-Aug-2014 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: GIC: Remove useless parens from GICBIS().
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| f28ff3d1ead40515c14ee841dc8b801c7d64353b |
|
08-Aug-2014 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: GIC: Remove useless parens from GICBIS().
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| c55b2851f901215fbfa46e4ea9cc04761c776815 |
|
17-Jul-2014 |
Jeffrey Deans <jeffrey.deans@imgtec.com> |
MIPS: GIC: Fix GICBIS macro
The GICBIS macro could update the GIC registers incorrectly, depending
on the data value passed in:
* Bits were only OR'd into the register data, so register fields could
not be cleared.
* Bits were OR'd into the register data without masking the data to the
correct field width, corrupting adjacent bits.
Signed-off-by: Jeffrey Deans <jeffrey.deans@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7378/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| 31521a7a64bc5df5202e479ee7ba8133993ab32a |
|
17-Jul-2014 |
Jeffrey Deans <jeffrey.deans@imgtec.com> |
MIPS: GIC: Generalise check for pending interrupts
Move most of the functionality of gic_get_int() into a new function
gic_get_int_mask() which takes a bitmask of interrupts in which the
caller is interested, and returns the subset which are pending for the
current CPU.
This allows CP0 IRQ dispatch routines to check only the GIC interrupts
which are routed to a particular CPU interrupt input.
gic_get_int() is reimplemented using gic_get_int_mask() and is retained
for use by any platforms for which gic_get_int() is sufficient.
Signed-off-by: Jeffrey Deans <jeffrey.deans@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7376/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| b0a88ae50220b60d6e9686fc5f5a200151217037 |
|
17-Jul-2014 |
Jeffrey Deans <jeffrey.deans@imgtec.com> |
MIPS: GIC: Remove GIC_FLAG_IPI
irq-gic.c:gic_get_int() masks out interrupts from the pending set which
aren’t in the pcpu_mask. Only interrupts marked with GIC_FLAG_IPI were
set in pcpu_mask, meaning that peripheral interrupts also had to be
marked as IPIs. Remove the use of GIC_FLAG_IPI and allow the flags
member of struct gic_intr_map to be zero.
Signed-off-by: Jeffrey Deans <jeffrey.deans@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7374/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| c975048165a973dc5b0aef76514045b69062db41 |
|
17-Jul-2014 |
Jeffrey Deans <jeffrey.deans@imgtec.com> |
MIPS: GIC: Move GIC_NUM_INTRS into platform irq.h
The value of GIC_NUM_INTRS is platform-specific. Using a default value
from gic.h will result in incorrect behaviour on some systems, so
require a suitable definition to be present in the platform's irq.h.
Signed-off-by: Jeffrey Deans <jeffrey.deans@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7373/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| 822350bc90c5069e9ab39f8720e2ef06af736124 |
|
17-Jul-2014 |
Jeffrey Deans <jeffrey.deans@imgtec.com> |
MIPS: GIC: move GIC interrupt bitmap declarations
Several bitmaps are declared in arch/mips/include/asm/gic.h, but the
scope of their use is limited to arch/mips/kernel/irq-gic.c. Move the
declarations from the header file to the C file.
Signed-off-by: Jeffrey Deans <jeffrey.deans@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7372/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| 414408d0eedd782a397ba89fd8f732ffbd3acde8 |
|
05-Mar-2014 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: allow GIC clockevent device config from other CPUs
This patch allows the GIC clockevent device for a CPU to be configured
by another CPU. This makes GIC clockevent devices suitable for use as
the tick broadcast device, where formerly the GIC timer local to the
configuring CPU would have been configured incorrectly.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
|
| 6d9727a7a58e11c09d28a67345d9a186fcbbdd8f |
|
15-Jan-2014 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: Add missing includes to gic.h
The gic.h header uses bitmaps and NR_CPUS, and should therefore include
linux/bitmap.h and linux/threads.h. This is in preparation for use of
this header in a subsequent commit from a C file which doesn't already
include those headers.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6357/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| 42a111797e8fa961d6168922e873d6b4be87e904 |
|
21-Jun-2013 |
Tony Wu <tung7970@gmail.com> |
MIPS: Fix typos and cleanup comment
Signed-off-by: Tony Wu <tung7970@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5535/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| 0ab2b7d08ea7226dc72ff0f8c05f470566facf7c |
|
10-Apr-2013 |
Raghu Gandham <Raghu.Gandham@imgtec.com> |
MIPS: Add new GIC clockevent driver.
Add new clockevent driver that uses the counter present on the MIPS
Global Interrupt Controller.
Signed-off-by: Raghu Gandham <Raghu.Gandham@imgtec.com>
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
| 2675fa7c7b46842f82b2766b5abe80e16ce32977 |
|
10-Apr-2013 |
Steven J. Hill <Steven.Hill@imgtec.com> |
MIPS: Formatting clean-ups for clocksources.
Various whitespace and #ifdef removals for GIC and R4K clocksources.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
| dfa762e1c31c30607e4e5259f287dd3e174cbcc3 |
|
10-Apr-2013 |
Steven J. Hill <Steven.Hill@imgtec.com> |
MIPS: Refactor GIC clocksource code.
Reorganize some of the GIC clocksource driver code. Below is a list of
the various changes.
* No longer select CSRC_GIC by default for Malta platform.
* Limit choice for either the GIC or R4K clocksource, not both.
* Change location in Makefile.
* Created new 'gic_read_count' function in common 'irq-gic.c' file.
* Change 'git_hpt_read' function in 'csrc-gic.c' to use new function.
* Surround GIC specific code in Malta platform code with #ifdef's.
* Only initialize the GIC clocksource if it was selected. Original
code called it unconditionally if a GIC was found.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
| 28ea215186d365408756577e9e612ee334e26f8e |
|
10-Apr-2013 |
Steven J. Hill <Steven.Hill@imgtec.com> |
MIPS: Move 'gic_frequency' to common location.
Move the global variable 'gic_frequency' to be defined in the file
'arch/mips/kernel/irq-gic.c' instead of defining it individually
for each platform making use of the GIC. Also change the type to
be an unsigned integer instead of signed.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
| ff86714fda0310ad153a2ba4836067f195e1f0b9 |
|
10-Apr-2013 |
Steven J. Hill <Steven.Hill@imgtec.com> |
MIPS: Move 'gic_present' to common location.
Move the global variable 'gic_present' to be defined in the file
'arch/mips/kernel/irq-gic.c' instead of defining it individually
for each platform making use of the GIC. Also change the type to
be an unsigned integer instead of signed.
Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
|
| 778eeb1b199b85bec79b49ac483b013e270636ea |
|
07-Dec-2012 |
Steven J. Hill <sjhill@mips.com> |
MIPS: Add new GIC clocksource.
Add new clocksource that uses the counter present on the MIPS
Global Interrupt Controller.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Patchwork: http://patchwork.linux-mips.org/patch/4681/
Signed-off-by: John Crispin <blogic@openwrt.org>
|
| 7034228792cc561e79ff8600f02884bd4c80e287 |
|
22-Jan-2013 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| 2299c49d601c20ba502f5cc7b2f72a0048f485db |
|
31-Aug-2012 |
Steven J. Hill <sjhill@mips.com> |
MIPS: Code clean-ups for the GIC.
Fix whitespace, beautify the code and remove debug statements.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
|
| 0b271f5600b5ae56d331a18da830e33f9fb0acdc |
|
31-Aug-2012 |
Steven J. Hill <sjhill@mips.com> |
MIPS: Make GIC code platform independent.
The GIC interrupt code is used by multiple platforms and the
current code was half Malta dependent code. These changes
abstract away the platform specific differences.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
|
| f0b77f2c0eed1e37c96b9a995d5a45e9eb4aaca8 |
|
06-Jul-2012 |
Steven J. Hill <sjhill@mips.com> |
MIPS: Clean-up GIC and vectored interrupts.
This change adds macros for routing of GIC interrupts for EIC and
non-EIC hardware modes. Also added Malta GIC macros having to do
with performance and timer interrupts.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3576/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| 863cb9bad8f992a9c171e90552045eac77808e84 |
|
17-Sep-2010 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: GIC: Remove dependencies from Malta files.
This prevents the GIC code from being reusable sanely.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| 7098f748283b4c056cca9c284c476b03f004ca12 |
|
10-Jul-2009 |
Chris Dearman <chris@mips.com> |
MIPS: GIC: Random fixes and enhancements.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| 7d35cdc07dd26eb6667f66f8e2f43f833a926ecf |
|
05-Jul-2009 |
Alexander Clouter <alex@digriz.org.uk> |
MIPS: Fix compile for !CONFIG_SMP
Commit fc03bc1715ca0ad4ccfe97aab16bcc9e7129c1a4 breaks compiling MIPS
with SMP disabled. This patch fixes that.
Signed-off-by: Alexander Clouter <alex@digriz.org.uk>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| 0365070f05f12f1648b4adf22cfb52ec7a8a371c |
|
18-Jun-2009 |
Tim Anderson <tanderson@mvista.com> |
MIPS: CMP: activate CMP support
Most of the CMP support was added before, this mostly correct compile
problems but adds a platform specific translation for the interrupt number
based on cpu number.
Signed-off-by: Tim Anderson <tanderson@mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| 9306c8def6abc2dbde4ac75eb6c631606b8fc1dd |
|
18-Jun-2009 |
Tim Anderson <tanderson@mvista.com> |
MIPS: CMP: Extend the GIC IPI interrupts beyond 32
This patch extends the GIC interrupt handling beyond the current 32 bit
range as well as extending the number of interrupts based on the number
of CPUs.
Signed-off-by: Tim Anderson <tanderson@mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|
| 384740dc49ea651ba350704d13ff6be9976e37fe |
|
16-Sep-2008 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
|