History log of /arch/mips/lantiq/irq.c
Revision Date Author Comments
b633648c5ad3cfbda0b3daea50d2135d44899259 23-May-2014 Ralf Baechle <ralf@linux-mips.org> MIPS: MT: Remove SMTC support

Nobody is maintaining SMTC anymore and there also seems to be no userbase.
Which is a pity - the SMTC technology primarily developed by Kevin D.
Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT
ASE's power and elegance.

Based on Markos Chandras <Markos.Chandras@imgtec.com> patch
https://patchwork.linux-mips.org/patch/6719/ which while very similar did
no longer apply cleanly when I tried to merge it plus some additional
post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to
merge once upon a time.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
f7777dcc7550531ae551f544bdc391c65d0e1731 18-Sep-2013 Ralf Baechle <ralf@linux-mips.org> MIPS: Panic messages should not end in \n.

Panic() is going to add a \n itself and it's annoying if a panic message rolls
of the screen on a device with no scrollback.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
078a55fc824c1633b3a507e4ad48b4637c1dfc18 18-Jun-2013 Paul Gortmaker <paul.gortmaker@windriver.com> MIPS: Delete __cpuinit/__CPUINIT usage from MIPS code

commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.

The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.

After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.

Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.

Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.

[1] https://lkml.org/lkml/2013/5/20/589

[ralf@linux-mips.org: Folded in Paul's followup fix.]

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
26365625947fb7d6501065272a1fd59460c0f4ed 19-Jan-2013 John Crispin <blogic@openwrt.org> MIPS: lantiq: rework external irq code

This code makes the irqs used by the EIU loadable from the DT. Additionally we
add a helper that allows the pinctrl layer to map external irqs to real irq
numbers.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4818/
7034228792cc561e79ff8600f02884bd4c80e287 22-Jan-2013 Ralf Baechle <ralf@linux-mips.org> MIPS: Whitespace cleanup.

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
79d61a046bf02a3eff9da15e607ac35c172de3a7 29-Jan-2013 John Crispin <blogic@openwrt.org> MIPS: Lantiq: Fix cp0_perfcount_irq mapping

The introduction of the OF support broke the cp0_perfcount_irq mapping. This
resulted in oprofile not working anymore.

Offending commit is :

commit 3645da0276ae9f6938ff29b13904b803ecb68424
Author: John Crispin <blogic@openwrt.org>
Date: Tue Apr 17 10:18:32 2012 +0200

OF: MIPS: lantiq: implement irq_domain support

Signed-off-by: Conor O'Gorman <i@conorogorman.net>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4875/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
70ec9054e7a65c878298666083f7d5b70ccf9032 16-Aug-2012 John Crispin <blogic@openwrt.org> MIPS: lantiq: external irq sources are not loaded properly

Support for the external interrupt unit was broken when the code was converted
to devicetree support.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4231/
9c1628b603ee9d2bb220be0400c5dc6950cf012b 16-Aug-2012 John Crispin <blogic@openwrt.org> MIPS: lantiq: dont register irq_chip for the irq cascade

We dont want to register the irq_chip for the MIPS IRQ cascade.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4230/
c2c9c788b91218bccbb9ac31539ffa577fe502bf 16-Aug-2012 John Crispin <blogic@openwrt.org> MIPS: lantiq: timer irq can be different to 7

The SVIP SoC has its timer IRQ on a different IRQ than 7. Fix up the irq
code to be able to handle this.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4229/
61fa969f27ec58296544bf94d058f3aa704cb8d9 16-Aug-2012 John Crispin <blogic@openwrt.org> MIPS: lantiq: split up IRQ IM ranges

Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
the SVIP we need to support IM ranges that are scattered inside the register range.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4237/
3645da0276ae9f6938ff29b13904b803ecb68424 17-Apr-2012 John Crispin <blogic@openwrt.org> OF: MIPS: lantiq: implement irq_domain support

Add support for irq_domain on lantiq socs. The conversion is straight forward
as the ICU found inside the socs allows the usage of irq_domain_add_linear.

Harware IRQ 0->7 are the generic MIPS IRQs. 8->199 are the Lantiq IRQ Modules.
Our irq_chip callbacks need to substract 8 (MIPS_CPU_IRQ_CASCADE) from d->hwirq
to find out the correct offset into the Interrupt Modules register range.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3802/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
a8d096ef78c4d9a664754e1fad5e82dec2feec68 30-Apr-2012 John Crispin <blogic@openwrt.org> MIPS: lantiq: add ipi handlers to make vsmp work

Add IPI handlers to the interrupt code. This patch makes MIPS_MT_SMP work
on lantiq socs. The code is based on the malta implementation.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3704/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
59c115798430f644b43123250ae4e1d820c3c18d 02-May-2012 John Crispin <blogic@openwrt.org> MIPS: lantiq: enable oprofile support on lantiq targets

This patch sets the performance counters irq on Lantiq SoCs.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3720/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
16f70b561dd897dc324b726ebc94e0c87db26f61 02-May-2012 John Crispin <blogic@openwrt.org> MIPS: lantiq: clear all irqs properly on boot

Due to missing brackets, the irq modules were not properly reset on boot.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3719/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
8b5690f8847490c1e3ea47266819833a13621253 22-Nov-2011 Yong Zhang <yong.zhang0@gmail.com> MIPS: irq: Remove IRQF_DISABLED

Since commit [e58aa3d2: genirq: Run irq handlers with interrupts disabled],
We run all interrupt handlers with interrupts disabled and we even check
and yell when an interrupt handler returns with interrupts enabled (see
commit [b738a50a: genirq: Warn when handler enables interrupts]).

So now this flag is a NOOP and can be removed.

[ralf@linux-mips.org: Fixed up conflicts in
arch/mips/alchemy/common/dbdma.c, arch/mips/cavium-octeon/smp.c and
arch/mips/kernel/perf_event.c.]

Signed-off-by: Yong Zhang <yong.zhang0@gmail.com>
To: linux-kernel@vger.kernel.org
Cc: tglx@linutronix.de
linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2835/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
ab75dc02c151c9d2a2fd446334d740b097a3b9db 17-Nov-2011 Ralf Baechle <ralf@linux-mips.org> MIPS: Fix up inconsistency in panic() string argument.

Panic() invokes printk() to add a \n internally, so panic arguments should
not themselves end in \n. Panic invocations in arch/mips and elsewhere
are inconsistently sometimes terminating in \n, sometimes not.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
77fbdb30f045084f1c65b72bd457d7406343aad7 18-Jul-2011 John Crispin <blogic@openwrt.org> MIPS: Lantiq: Fix external interrupt sources

The irq base offset needs to be ignored when matching irqs to external
interrupt pins. Taking the offset into account resulted in the EIU not
being brought up properly.

Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2616/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
171bb2f19ed6f3627f4f783f658f2f475b2fbd50 30-Mar-2011 John Crispin <blogic@openwrt.org> MIPS: Lantiq: Add initial support for Lantiq SoCs

Add initial support for Mips based SoCs made by Lantiq. This series will add
support for the XWAY family.

The series allows booting a minimal system using a initramfs or NOR. Missing
drivers and support for Amazon and GPON family will be provided in a later
series.

[Ralf: Remove some cargo cult programming and fixed formatting.]

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2252/
Patchwork: https://patchwork.linux-mips.org/patch/2371/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>