| d0c550dc36881fda171ec8ad3dcc67491ad968eb |
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19-Jan-2013 |
John Crispin <blogic@openwrt.org> |
MIPS: lantiq: add GPHY clock gate bits
Explicitly enable the clock gate of the internal GPHYs found on xrx200.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4816/
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| af14a456c58c153c6d761e6c0af48157692b52ad |
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09-Nov-2012 |
John Crispin <blogic@openwrt.org> |
MIPS: lantiq: adds code for booting GPHY
The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to
boot them up.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4522
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| 15753b6586710d788f36cfd5fbb98d0805b390ab |
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09-Nov-2012 |
John Crispin <blogic@openwrt.org> |
MIPS: lantiq: fix bootselect bits on XRX200 SoC
The XRX200 SoC family has a different register layout for reading the boot
selection bits.
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4519
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| a0392222d9a374588803454c4d2211108c64d4e4 |
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13-Apr-2012 |
John Crispin <blogic@openwrt.org> |
OF: MIPS: lantiq: implement OF support
Activate USE_OF, add a sample DTS file and convert the core soc code to OF.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3803/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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| 6697c6933048aabe94f0049070f7ec09cd52baa8 |
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30-Apr-2012 |
John Crispin <blogic@openwrt.org> |
MIPS: lantiq: cleanup reset code
Add 2 new soc specifc handlers and remove superflous pr_notice calls.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3705/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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| ab75dc02c151c9d2a2fd446334d740b097a3b9db |
|
17-Nov-2011 |
Ralf Baechle <ralf@linux-mips.org> |
MIPS: Fix up inconsistency in panic() string argument.
Panic() invokes printk() to add a \n internally, so panic arguments should
not themselves end in \n. Panic invocations in arch/mips and elsewhere
are inconsistently sometimes terminating in \n, sometimes not.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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| 4af92e7a68af7b515d274f9d33b14b8a0804a0f6 |
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10-Nov-2011 |
John Crispin <blogic@openwrt.org> |
MIPS: lantiq: use export.h in favour of module.h
The code located at arch/mips/lantiq/ included module.h to be able to use
the EXPORT_SYMBOL* macros. These can now be directly included using
export.h.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2937/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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| 8ec6d93508f705dacafd5fcd058c69ef405002f9 |
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30-Mar-2011 |
John Crispin <blogic@openwrt.org> |
MIPS: Lantiq: add SoC specific code for XWAY family
Add support for the Lantiq XWAY family of Mips24KEc SoCs.
* Danube (PSB50702)
* Twinpass (PSB4000)
* AR9 (PSB50802)
* Amazon SE (PSB5061)
The Amazon SE is a lightweight SoC and has no PCI as well as a different
clock. We split the code out into seperate files to handle this.
The GPIO pins on the SoCs are multi function and there are several bits
we can use to configure the pins. To be as compatible as possible to
GPIOLIB we add a function
int lq_gpio_request(unsigned int pin, unsigned int alt0,
unsigned int alt1, unsigned int dir, const char *name);
which lets you configure the 2 "alternate function" bits. This way drivers like
PCI can make use of GPIOLIB without a cubersome wrapper.
The PLL code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was
taken from a 2.4.20 source tree and was never really changed by me since then.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2249/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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