| d4e58e5928f8c6c49228451dd03e0714cbab299a |
|
11-Jun-2014 |
Michael Neuling <mikey@neuling.org> |
powerpc/powernv: Enable POWER8 doorbell IPIs
This patch enables POWER8 doorbell IPIs on powernv.
Since doorbells can only IPI within a core, we test to see when we can use
doorbells and if not we fall back to XICS. This also enables hypervisor
doorbells to wakeup us up from nap/sleep via the LPCR PECEDH bit.
Based on tests by Anton, the best case IPI latency between two threads dropped
from 894ns to 512ns.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 8f619b5429d9d852df09b85d9e41459859e04951 |
|
28-Mar-2014 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc/ppc64: Do not turn AIL (reloc-on interrupts) too early
Turn them on at the same time as we allow MSR_IR/DR in the paca
kernel MSR, ie, after the MMU has been setup enough to be able
to handle relocated access to the linear mapping.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 0440705049b041d84268ea57f6e90e2f16618897 |
|
30-Oct-2013 |
Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> |
powerpc/book3s: Add flush_tlb operation in cpu_spec.
This patch introduces flush_tlb operation in cpu_spec structure. This will
help us to invoke appropriate CPU-side flush tlb routine. This patch
adds the foundation to invoke CPU specific flush routine for respective
architectures. Currently this patch introduce flush_tlb for p7 and p8.
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 8fc1f5d7eff9a4ed0cdb7215e7ca4b82b931d6d7 |
|
20-May-2013 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc: Fix TLB cleanup at boot on POWER8
The TLB has 512 congruence classes (2048 entries 4 way set associative)
while P7 had 128
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 1ddf499e1a49e67c02b89e6565d091a0bda29a91 |
|
30-Apr-2013 |
Michael Neuling <mikey@neuling.org> |
powerpc: Turn on the EBB H/FSCR bits
This turns Event Based Branching (EBB) on in the Hypervisor Facility Status and
Control Register (HFSCR) and Facility Status and Control Register (FSCR).
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 53b56ca0195b8a2a098a358088ecfefafb030b40 |
|
25-Apr-2013 |
Anshuman Khandual <khandual@linux.vnet.ibm.com> |
powerpc: Setup BHRB instructions facility in HFSCR for POWER8
Make BHRB instructions available in problem and privileged states.
Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 240686c1368775b5dc80aae863301189b25f9bfa |
|
25-Apr-2013 |
Michael Ellerman <michael@ellerman.id.au> |
powerpc: Initialise PMU related regs on Power8
For both HV and guest kernels, intialise PMU regs to something sane.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 8c2a381734fc9718f127f4aba958e8a7958d4028 |
|
24-Apr-2013 |
Michael Neuling <mikey@neuling.org> |
powerpc/power8: Fix secondary CPUs hanging on boot for HV=0
In __restore_cpu_power8 we determine if we are HV and if not, we return
before setting HV only resources.
Unfortunately we forgot to restore the link register from r11 before
returning.
This will happen on boot and with secondary CPUs not coming online.
This adds the missing link register restore.
Signed-off-by: Michael Neuling <mikey@neuling.org>
CC: <stable@vger.kernel.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 2a3563b023e5f99e1ec48b66b4caeac94584e7c7 |
|
05-Mar-2013 |
Michael Neuling <mikey@neuling.org> |
powerpc: Setup in HFSCR for POWER8
Setup the HFSCR (Hypervisor Facility Status and Control Register) for POWER8
when running HV=1. The HFSCR is the same as the FSCR except it's for
hypervisors. It controls the available of various facilities in OS and
userspace levels. It also indicates the cause of a hypervisor facility
unavailable interrupt (although we are not using this here).
This patch sets the facilities Linux knows about incase the firmware doesn't.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
|
| 54c9b2253d34e8998e4bff9ac2d7a3ba0b861d52 |
|
04-Mar-2013 |
Michael Neuling <mikey@neuling.org> |
powerpc: Set DSCR bit in FSCR setup
We support DSCR (Data Stream Control Register) so we should make sure we set it
in the FSCR (Facility Status & Control Register) incase some firmwares don't
set it. If we don't set this, we'll take a facility unavailable exception when
using the DSCR.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 57d231678ace658b3a73a0d144cfebbd4257bc0e |
|
04-Mar-2013 |
Michael Neuling <mikey@neuling.org> |
powerpc: Fix setting FSCR for HV=0 and on secondary CPUs
Currently we only set the FSCR (Facility Status and Control Register) when HV=1
but this feature is available when HV=0 also. This patch sets FSCR when HV=0.
Also, we currently only set the FSCR on the master CPU. This patch also sets
the FSCR on secondary CPUs.
Signed-off-by: Michael Neuling <mikey@neuling.org>
cc: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 2468dcf641e4f3e1b0153e3e11ca20740b2f4ce8 |
|
07-Feb-2013 |
Ian Munsie <imunsie@au1.ibm.com> |
powerpc: Add support for context switching the TAR register
This patch adds support for enabling and context switching the Target
Address Register in Power8. The TAR is a new special purpose register
that can be used for computed branches with the bctar[l] (branch
conditional to TAR) instruction in the same manner as the count and link
registers.
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| b0302722eec7c086a31de6e3d9789304ef21df7b |
|
02-Nov-2012 |
Michael Neuling <mikey@neuling.org> |
powerpc: Setup relocation on exceptions for bare metal systems
This turns on MMU on execptions via AIL field in the LPCR.
Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| f7c32c24f5788798f17d4e520a5d238335a859cb |
|
05-Nov-2012 |
Michael Neuling <mikey@neuling.org> |
powerpc: Move initial mfspr LPCR out of __init_LPCR
We want to change what's initially set in the LPCR, so start by taking the move
from LPCR out of the function and into the caller.
Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| aec937b1ee6d7b28499d50ea6df1b2fe9edee91b |
|
30-Oct-2012 |
Michael Neuling <mikey@neuling.org> |
powerpc: Add POWER8 setup code
Just a copy of POWER7 for now. Will update with new code later.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| cd5daaf713cf8d728a2be2a3673293fff9465d9a |
|
30-Oct-2012 |
Michael Neuling <mikey@neuling.org> |
powerpc: make POWER7 setup code name generic
We are going to reuse this in POWER8 so make the name generic.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|