| 2b2695a8d85593ec0253f7fdbeea1e18f0f9e5e2 |
|
20-Aug-2014 |
Mihai Caraman <mihai.caraman@freescale.com> |
powerpc/booke: Revert SPE/AltiVec common defines for interrupt numbers
Book3E specification defines shared interrupt numbers for SPE and AltiVec
units. Still SPE is present in e200/e500v2 cores while AltiVec is present in
e6500 core. So we can currently decide at compile-time which unit to support
exclusively. As Alexander Graf suggested, this will improve code readability
especially in KVM.
Use distinct defines to identify SPE/AltiVec interrupt numbers, reverting
c58ce397 and 6b310fc5 patches that added common defines.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
|
| 3477e71d53197d7f1b6a1f7416f3c42ffec5f221 |
|
20-Aug-2014 |
Mihai Caraman <mihai.caraman@freescale.com> |
powerpc/booke: Restrict SPE exception handlers to e200/e500 cores
SPE exception handlers are now defined for 32-bit e500mc cores even though
SPE unit is not present and CONFIG_SPE is undefined.
Restrict SPE exception handlers to e200/e500 cores adding CONFIG_SPE_POSSIBLE
and consequently guard __stup_ivors and __setup_cpu functions.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
|
| 0be7d969b0efef085ed6497d462ba16a875ca737 |
|
24-Dec-2013 |
Kevin Hao <haokexin@gmail.com> |
powerpc/fsl_booke: smp support for booting a relocatable kernel above 64M
When booting above the 64M for a secondary cpu, we also face the
same issue as the boot cpu that the PAGE_OFFSET map two different
physical address for the init tlb and the final map. So we have to use
switch_to_as1/restore_to_as0 between the conversion of these two
maps. When restoring to as0 for a secondary cpu, we only need to
return to the caller. So add a new parameter for function
restore_to_as0 for this purpose.
Use LOAD_REG_ADDR_PIC to get the address of variables which may
be used before we set the final map in cams for the secondary cpu.
Move the setting of cams a bit earlier in order to avoid the
unnecessary using of LOAD_REG_ADDR_PIC.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
| 7d2471f9fa85089beb1cb9436ffc28f9e11e518d |
|
24-Dec-2013 |
Kevin Hao <haokexin@gmail.com> |
powerpc/fsl_booke: make sure PAGE_OFFSET map to memstart_addr for relocatable kernel
This is always true for a non-relocatable kernel. Otherwise the kernel
would get stuck. But for a relocatable kernel, it seems a little
complicated. When booting a relocatable kernel, we just align the
kernel start addr to 64M and map the PAGE_OFFSET from there. The
relocation will base on this virtual address. But if this address
is not the same as the memstart_addr, we will have to change the
map of PAGE_OFFSET to the real memstart_addr and do another relocation
again.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
[scottwood@freescale.com: make offset long and non-negative in simple case]
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
| 78a235efdc42ff363de81fdbc171385e8b86b69b |
|
24-Dec-2013 |
Kevin Hao <haokexin@gmail.com> |
powerpc/fsl_booke: set the tlb entry for the kernel address in AS1
We use the tlb1 entries to map low mem to the kernel space. In the
current code, it assumes that the first tlb entry would cover the
kernel image. But this is not true for some special cases, such as
when we run a relocatable kernel above the 64M or set
CONFIG_KERNEL_START above 64M. So we choose to switch to address
space 1 before setting these tlb entries.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
| dd189692d40948d6445bbaeb8cb9bf9d15f54dc6 |
|
24-Dec-2013 |
Kevin Hao <haokexin@gmail.com> |
powerpc: enable the relocatable support for the fsl booke 32bit kernel
This is based on the codes in the head_44x.S. The difference is that
the init tlb size we used is 64M. With this patch we can only load the
kernel at address between memstart_addr ~ memstart_addr + 64M. We will
fix this restriction in the following patches.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
| 99739611e816716d912ae89a4354237fc39745a6 |
|
24-Dec-2013 |
Kevin Hao <haokexin@gmail.com> |
powerpc/fsl_booke: introduce get_phys_addr function
Move the codes which translate a effective address to physical address
to a separate function. So it can be reused by other code.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
| 7c732cba3d9312882e82d91d5948261dfd5c8fe6 |
|
24-Dec-2013 |
Kevin Hao <haokexin@gmail.com> |
powerpc/fsl_booke: protect the access to MAS7
The e500v1 doesn't implement the MAS7, so we should avoid to access
this register on that implementations. In the current kernel, the
access to MAS7 are protected by either CONFIG_PHYS_64BIT or
MMU_FTR_BIG_PHYS. Since some code are executed before the code
patching, we have to use CONFIG_PHYS_64BIT in these cases.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
| c58ce397a62ec14b7b06c407a4173ed667e20d5f |
|
01-Jul-2013 |
Mihai Caraman <mihai.caraman@freescale.com> |
powerpc/fsl-booke: Use common defines for SPE/FP interrupts numbers
On Book3E some SPE/FP/AltiVec interrupts share the same number. Use
common defines to indentify these numbers.
Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com>
[scottwood@freescale.com: fixed space-before-tab]
Signed-off-by: Scott Wood <scottwood@freescale.com>
|
| 5f20be4478032eeba66abddc79eae3abea45c5c8 |
|
14-Jul-2013 |
Kevin Hao <haokexin@gmail.com> |
powerpc: Remove the empty giveup_fpu() function on 32bit kernel
Instead of implementing an empty giveup_fpu() function for each
32bit processor type, replace them with an unique empty inline
function.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| fc2a6cfe05a33891180a27d55983febe170bc0f8 |
|
30-Apr-2013 |
Bharat Bhushan <r65777@freescale.com> |
powerpc: Fix interrupt range check on debug exception
We do not want to take single step and branch-taken debug exception
in kernel exception code. But the address range check was not covering
all kernel exception handlers address range.
With this patch we defined the interrupt_end label which defines the
end on kernel exception code. So now we check interrupt_base to
interrupt_end range for not handling debug exception in kernel
exception entry.
Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 7e0f4872a33c6da38e727cf42c939cc32294fce6 |
|
09-Jul-2012 |
Varun Sethi <Varun.Sethi@freescale.com> |
powepc/booke: Separate out E.HV check and ivor setup code.
Move the E.HV check and CPU_FTR_EMB_HV flag manipulation to the cpu setup
code. Create a separate routine for E.HV ivors setup.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| d0832a75075b1119635e0f48549e378040cf5e67 |
|
20-Jul-2012 |
Zhao Chenhui <chenhui.zhao@freescale.com> |
powerpc/85xx: add HOTPLUG_CPU support
Add support to disable and re-enable individual cores at runtime on
MPC85xx/QorIQ SMP machines. Currently support e500v1/e500v2 core.
MPC85xx machines use ePAPR spin-table in boot page for CPU kick-off. This
patch uses the boot page from bootloader to boot core at runtime. It
supports 32-bit and 36-bit physical address.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 9778b696a0188ad3b3524b383953ee73b31b7b68 |
|
05-Jul-2012 |
Stuart Yoder <stuart.yoder@freescale.com> |
powerpc: Use CURRENT_THREAD_INFO instead of open coded assembly
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 2dc3d4cc6848572237efc5da9f79a2446474f00d |
|
01-Mar-2012 |
Liu Yu <yu.liu@freescale.com> |
powerpc/e500: make load_up_spe a normal fuction
So that we can call it when improving SPE switch like book3e did for fp
switch.
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Olivia Yin <hong-hua.yin@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 8cd3c23df79411f6b24ddb7d2ed58d26e3b06815 |
|
15-Apr-2012 |
Anton Blanchard <anton@samba.org> |
powerpc: Remove empty giveup_altivec function on book3e CPUs
Use an empty inline instead of an empty function to implement
giveup_altivec on book3e CPUs, similar to flush_altivec_to_thread.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 73196cd364a2d972d73fa08da9d81ca3215bed68 |
|
20-Dec-2011 |
Scott Wood <scottwood@freescale.com> |
KVM: PPC: e500mc support
Add processor support for e500mc, using hardware virtualization support
(GS-mode).
Current issues include:
- No support for external proxy (coreint) interrupt mode in the guest.
Includes work by Ashish Kalra <Ashish.Kalra@freescale.com>,
Varun Sethi <Varun.Sethi@freescale.com>, and
Liu Yu <yu.liu@freescale.com>.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
|
| cfac57847a67c4903f34a77e971521531bbc7c77 |
|
20-Dec-2011 |
Scott Wood <scottwood@freescale.com> |
powerpc/booke: Provide exception macros with interrupt name
DO_KVM will need to identify the particular exception type.
There is an existing set of arbitrary numbers that Linux passes,
but it's an undocumented mess that sort of corresponds to server/classic
exception vectors but not really.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
|
| a546498f3bf9aac311c66f965186373aee2ca0b0 |
|
07-Mar-2012 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc: Call do_page_fault() with interrupts off
We currently turn interrupts back to their previous state before
calling do_page_fault(). This can be annoying when debugging as
a bad fault will potentially have lost some processor state before
getting into the debugger.
We also end up calling some generic code with interrupts enabled
such as notify_page_fault() with interrupts enabled, which could
be unexpected.
This changes our code to behave more like other architectures,
and make the assembly entry code call into do_page_faults() with
interrupts disabled. They are conditionally re-enabled from
within do_page_fault() in the same spot x86 does it.
While there, add the might_sleep() test in the case of a successful
trylock of the mmap semaphore, again like x86.
Also fix a bug in the existing assembly where r12 (_MSR) could get
clobbered by C calls (the DTL accounting in the exception common
macro and DISABLE_INTS) in some cases.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2. Add the r12 clobber fix
|
| 0f890c8d205e47f7cb0d381ffba582a170fd4f72 |
|
14-Dec-2011 |
Suzuki Poulose <suzuki@in.ibm.com> |
powerpc: Rename mapping based RELOCATABLE to DYNAMIC_MEMSTART for BookE
The current implementation of CONFIG_RELOCATABLE in BookE is based
on mapping the page aligned kernel load address to KERNELBASE. This
approach however is not enough for platforms, where the TLB page size
is large (e.g, 256M on 44x). So we are renaming the RELOCATABLE used
currently in BookE to DYNAMIC_MEMSTART to reflect the actual method.
The CONFIG_RELOCATABLE for PPC32(BookE) based on processing of the
dynamic relocations will be introduced in the later in the patch series.
This change would allow the use of the old method of RELOCATABLE for
platforms which can afford to enforce the page alignment (platforms with
smaller TLB size).
Changes since v3:
* Introduced a new config, NONSTATIC_KERNEL, to denote a kernel which is
either a RELOCATABLE or DYNAMIC_MEMSTART(Suggested by: Josh Boyer)
Suggested-by: Scott Wood <scottwood@freescale.com>
Tested-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Suzuki K. Poulose <suzuki@in.ibm.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Josh Boyer <jwboyer@gmail.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: linux ppc dev <linuxppc-dev@lists.ozlabs.org>
Signed-off-by: Josh Boyer <jwboyer@gmail.com>
|
| 7d0d3ad5e3cfbf96aa4a2d6ee26a20c98a29d4a1 |
|
26-Oct-2011 |
Matthew McClintock <msm@freescale.com> |
powerpc/fsl_booke: Fix comment in head_fsl_booke.S
Fix typo in comments introduced by:
commit 6dece0eb69b2a28e18d104bc5d707f1cb673f5e0
Author: Scott Wood <scottwood@freescale.com>
Date: Mon Jul 25 11:29:33 2011 +0000
powerpc/32: Pass device tree address as u64 to machine_init
Signed-off-by: Matthew McClintock <msm@freescale.com>
cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 6dece0eb69b2a28e18d104bc5d707f1cb673f5e0 |
|
25-Jul-2011 |
Scott Wood <scottwood@freescale.com> |
powerpc/32: Pass device tree address as u64 to machine_init
u64 is used rather than phys_addr_t to keep things simple, as
this is called from assembly code.
Update callers to pass a 64-bit address in r3/r4. Other unused
register assignments that were once parameters to machine_init
are dropped.
For FSL BookE, look up the physical address of the device tree from the
effective address passed in r3 by the loader. This is required for
situations where memory does not start at zero (due to AMP or IOMMU-less
virtualization), and thus the IMA doesn't start at zero, and thus the
device tree effective address does not equal the physical address.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 41151e77a4d96ea138cede6d84c955aa4769ce74 |
|
28-Jun-2011 |
Becky Bruce <beckyb@kernel.crashing.org> |
powerpc: Hugetlb for BookE
Enable hugepages on Freescale BookE processors. This allows the kernel to
use huge TLB entries to map pages, which can greatly reduce the number of
TLB misses and the amount of TLB thrashing experienced by applications with
large memory footprints. Care should be taken when using this on FSL
processors, as the number of large TLB entries supported by the core is low
(16-64) on current processors.
The supported set of hugepage sizes include 4m, 16m, 64m, 256m, and 1g.
Page sizes larger than the max zone size are called "gigantic" pages and
must be allocated on the command line (and cannot be deallocated).
This is currently only fully implemented for Freescale 32-bit BookE
processors, but there is some infrastructure in the code for
64-bit BooKE.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| c51584d52e3878aa9b2bb98cdfb87173e7acf560 |
|
15-Jun-2011 |
Scott Wood <scottwood@freescale.com> |
powerpc/e500: SPE register saving: take arbitrary struct offset
Previously, these macros hardcoded THREAD_EVR0 as the base of the save
area, relative to the base register passed. This base offset is now
passed as a separate macro parameter, allowing reuse with other SPE
save areas, such as used by KVM.
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
|
| 685659ee70db0bac47ffd619c726cf600e504fd7 |
|
15-Jun-2011 |
yu liu <yu.liu@freescale.com> |
powerpc/e500: Save SPEFCSR in flush_spe_to_thread()
giveup_spe() saves the SPE state which is protected by MSR[SPE].
However, modifying SPEFSCR does not trap when MSR[SPE]=0.
And since SPEFSCR is already saved/restored in _switch(),
not all the callers want to save SPEFSCR again.
Thus, saving SPEFSCR should not belong to giveup_spe().
This patch moves SPEFSCR saving to flush_spe_to_thread(),
and cleans up the caller that needs to save SPEFSCR accordingly.
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
|
| 1325a684b553d4b5c41ae0482f8991b43f945746 |
|
22-Apr-2011 |
Ashish Kalra <Ashish.Kalra@freescale.com> |
powerpc/85xx: Save scratch registers to thread info instead of using SPRGs.
We expect this is actually faster, and we end up needing more space than we
can get from the SPRGs in some instances. This is also useful when running
as a guest OS - SPRGs4-7 do not have guest versions.
8 slots are allocated in thread_info for this even though we only actually
use 4 of them - this allows space for future code to have more scratch
space (and we know we'll need it for things like hugetlb).
Signed-off-by: Ashish Kalra <Ashish.Kalra@freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 25985edcedea6396277003854657b5f3cb31a628 |
|
31-Mar-2011 |
Lucas De Marchi <lucas.demarchi@profusion.mobi> |
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
|
| 46f5221049bb46b0188aad6b6dfab5dbc778be22 |
|
18-Nov-2010 |
Stephen Rothwell <sfr@canb.auug.org.au> |
powerpc: Remove second definition of STACK_FRAME_OVERHEAD
Since STACK_FRAME_OVERHEAD is defined in asm/ptrace.h and that
is ASSEMBER safe, we can just include that instead of going via
asm-offsets.h.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 2ed38b23597284cc96a97e295cb145a6202dfcd4 |
|
01-Sep-2010 |
Matthew McClintock <msm@freescale.com> |
powerpc/fsl_booke: Add support to boot from core other than 0
First we check to see if we are the first core booting up. This
is accomplished by comparing the boot_cpuid with -1, if it is we
assume this is the first core coming up.
Secondly, we need to update the initial thread info structure
to reflect the actual cpu we are running on otherwise
smp_processor_id() and related functions will return the default
initialization value of the struct or 0.
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| b3df895aebe091b1657a42a8c859bd49fc96646b |
|
04-Apr-2010 |
Sebastian Andrzej Siewior <bigeasy@linutronix.de> |
powerpc/kexec: Add support for FSL-BookE
This adds support kexec on FSL-BookE where the MMU can not be simply
switched off. The code borrows the initial MMU-setup code to create the
identical mapping mapping. The only difference to the original boot code
is the size of the mapping(s) and the executeable address.
The kexec code maps the first 2 GiB of memory in 256 MiB steps. This
should work also on e500v1 boxes.
SMP support is still not available.
(Kumar: Added minor change to build to ifdef CONFIG_PPC_STD_MMU_64 some
code that was PPC64 specific)
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 7c08ce718fd04e373d7473918ae02f1c04d5d504 |
|
04-Apr-2010 |
Sebastian Andrzej Siewior <bigeasy@linutronix.de> |
powerpc/fsl-booke: Move the entry setup code into a seperate file
This patch only moves the initial entry code which setups the mapping
from what ever to KERNELBASE into a seperate file. No code change has
been made here.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 2289d2d1a8574a11e66b00c5a59090c6fc227751 |
|
04-Apr-2010 |
Sebastian Andrzej Siewior <bigeasy@linutronix.de> |
powerpc/fsl-booke: fix the case where we are not in the first page
During boot we change the mapping a few times until we have a "defined"
mapping. During this procedure a small 4KiB mapping is created and after
that one a 64MiB. Currently the offset of the 4KiB page in that we run
is zero because the complete startup up code is in first page which
starts at RPN zero.
If the code is recycled and moved to another location then its execution
will fail because the start address in 64 MiB mapping is computed
wrongly. It does not consider the offset to the page from the begin of
the memory.
This patch fixes this. Usually (system boot) r25 is zero so this does
not change anything unless the code is recycled.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 78e2e68a2b79f394b7cd61e07987a8a89af907f7 |
|
07-May-2010 |
Li Yang <leoli@freescale.com> |
powerpc/fsl-booke: Fix InstructionTLBError execute permission check
In CONFIG_PTE_64BIT the PTE format has unique permission bits for user
and supervisor execute. However on !CONFIG_PTE_64BIT we overload the
supervisor bit to imply user execute with _PAGE_USER set. This allows
us to use the same permission check mask for user or supervisor code on
!CONFIG_PTE_64BIT.
However, on CONFIG_PTE_64BIT we map _PAGE_EXEC to _PAGE_BAP_UX so we
need a different permission mask based on the fault coming from a kernel
address or user space.
Without unique permission masks we see issues like the following with
modules:
Unable to handle kernel paging request for instruction fetch
Faulting instruction address: 0xf938d040
Oops: Kernel access of bad area, sig: 11 [#1]
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| fa6bd996db2fbecd7a9a408c158105c55a51fe41 |
|
07-May-2010 |
Li Yang <leoli@freescale.com> |
powerpc/fsl-booke: Fix InstructionTLBError execute permission check
In CONFIG_PTE_64BIT the PTE format has unique permission bits for user
and supervisor execute. However on !CONFIG_PTE_64BIT we overload the
supervisor bit to imply user execute with _PAGE_USER set. This allows
us to use the same permission check mask for user or supervisor code on
!CONFIG_PTE_64BIT.
However, on CONFIG_PTE_64BIT we map _PAGE_EXEC to _PAGE_BAP_UX so we
need a different permission mask based on the fault coming from a kernel
address or user space.
Without unique permission masks we see issues like the following with
modules:
Unable to handle kernel paging request for instruction fetch
Faulting instruction address: 0xf938d040
Oops: Kernel access of bad area, sig: 11 [#1]
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Jin Qing <b24347@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 09156a7a409cf93d1ca2706bf05d714879a5b7ea |
|
06-Mar-2010 |
Márton Németh <nm127@freemail.hu> |
powerpc: Do not call prink when CONFIG_PRINTK is not defined
When printk() is disabled (CONFIG_PRINTK) at menu item
General setup
-> Configure standard kernel features (for small systems)
-> Enable support for printk
then there should be no printk() calls at all.
Signed-off-by: Márton Németh <nm127@freemail.hu>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| 9d296cfa69b3d4abc9d556986d544f0727988eed |
|
17-Mar-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-booke: Get coherent bit from PTE
We shouldn't be always setting 'M' in the TLB entry since its reasonable
for somethings to be mapped non-coherent. The PTE should have 'M' set
properly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 51adc548cb0b2441ee9d4c428a84b77021f4d3fa |
|
15-Jan-2010 |
Sebastian Andrzej Siewior <bigeasy@linutronix.de> |
powerpc/fsl-booke: replace a hardcoded constant
24 is offset between the opcode past bl and past rfi. This makes it more
obvious.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 8b27f0b61db57f5555fc2d3fc95c3ea9fd1a9d6c |
|
15-Oct-2009 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-booke: Rework TLB CAM code
Re-write the code so its more standalone and fixed some issues:
* Bump'd # of CAM entries to 64 to support e500mc
* Make the code handle MAS7 properly
* Use pr_cont instead of creating a string as we go
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 76acc2c1a7a9a8c2cae7e9cf8d0a8b374a48aa94 |
|
01-Sep-2009 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-booke: Use HW PTE format if CONFIG_PTE_64BIT
Switch to using the Power ISA defined PTE format when we have a 64-bit
PTE. This makes the code handling between fsl-booke and book3e-64
similiar for TLB faults.
Additionally this lets use take advantage of the page size encodings and
full permissions that the HW PTE defines.
Also defined _PMD_PRESENT, _PMD_PRESENT_MASK, and _PMD_BAD since the
32-bit ppc arch code expects them.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| ea3cc330ac0cd521ff07c7cd432a1848c19a7e92 |
|
18-Aug-2009 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc/mm: Cleanup handling of execute permission
This is an attempt at cleaning up a bit the way we handle execute
permission on powerpc. _PAGE_HWEXEC is gone, _PAGE_EXEC is now only
defined by CPUs that can do something with it, and the myriad of
#ifdef's in the I$/D$ coherency code is reduced to 2 cases that
hopefully should cover everything.
The logic on BookE is a little bit different than what it was though
not by much. Since now, _PAGE_EXEC will be set by the generic code
for executable pages, we need to filter out if they are unclean and
recover it. However, I don't expect the code to be more bloated than
it already was in that area due to that change.
I could boast that this brings proper enforcing of per-page execute
permissions to all BookE and 40x but in fact, we've had that now for
some time as a side effect of my previous rework in that area (and
I didn't even know it :-) We would only enable execute permission if
the page was cache clean and we would only cache clean it if we took
and exec fault. Since we now enforce that the later only work if
VM_EXEC is part of the VMA flags, we de-fact already enforce per-page
execute permissions... Unless I missed something
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| ee43eb788b3a06425fffb912677e2e1c8b00dd3b |
|
14-Jul-2009 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc: Use names rather than numbers for SPRGs (v2)
The kernel uses SPRG registers for various purposes, typically in
low level assembly code as scratch registers or to hold per-cpu
global infos such as the PACA or the current thread_info pointer.
We want to be able to easily shuffle the usage of those registers
as some implementations have specific constraints realted to some
of them, for example, some have userspace readable aliases, etc..
and the current choice isn't always the best.
This patch should not change any code generation, and replaces the
usage of SPRN_SPRGn everywhere in the kernel with a named replacement
and adds documentation next to the definition of the names as to
what those are used for on each processor family.
The only parts that still use the original numbers are bits of KVM
or suspend/resume code that just blindly needs to save/restore all
the SPRGs.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| e70398458738fd26f96adc95eea8efe908809f08 |
|
26-Apr-2009 |
Tim Abbott <tabbott@MIT.EDU> |
powerpc: convert to use __HEAD and HEAD_TEXT macros.
This has the consequence of changing the section name use for head
code from ".text.head" to ".head.text". Since this commit changes all
users in the architecture, this change should be harmless.
Signed-off-by: Tim Abbott <tabbott@mit.edu>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
|
| 620165f971753c2c451c880796bac7cd66f3534a |
|
12-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add support for using doorbells for SMP IPI
The e500mc supports the new msgsnd/doorbell mechanisms that were added in
the Power ISA 2.05 architecture. We use the normal level doorbell for
doing SMP IPIs at this point.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
|
| d66c82ea456853a71d88359b0c19a92ac1d393ff |
|
11-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-booke: Add new ISA 2.06 page sizes and MAS defines
The Power ISA 2.06 added power of two page sizes to the embedded MMU
architecture. Its done it such a way to be code compatiable with the
existing HW. Made the minor code changes to support both power of two
and power of four page sizes. Also added some new MAS bits and macros
that are defined as part of the 2.06 ISA. Renamed some things to use
the 'Book-3e' concept to convey the new MMU that is based on the
Freescale Book-E MMU programming model.
Note, its still invalid to try and use a page size that isn't supported
by cpu.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 105c31df6fc5a424b480321763b5598cf3817821 |
|
08-Jan-2009 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-booke: Cleanup init/exception setup to be runtime
We currently have a few variants of fsl-booke processors (e500v1, e500v2,
e500mc, and e200). They all have minor differences that we had previously
been handling via ifdefs.
To move towards having this support the following changes have been made:
* PID1, PID2 only exist on e500v1 & e500v2 and should not be accessed on
e500mc or e200. We use MMUCFG[NPIDS] to determine which case we are
since we only touch PID1/2 in extremely early init code.
* Not all IVORs exist on all the processors so introduce cpu_setup
functions for each variant to setup the proper IVORs that are either
unique or exist but have some variations between the processors
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 5597b25c300eeaf43392f399990d3f3027a9b779 |
|
09-Jan-2009 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/e500mc: Doorbells need to be taken w/exceptions disabled
We use Doorbell interrupts for IPIs and thus we need to make sure we aren't
interrupted in the process of processing the IPI.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Dave Liu <daveliu@freescale.com>
|
| 6fd8be4bf72879b3039654388e985cabf8449af5 |
|
09-Dec-2008 |
Trent Piepho <tpiepho@freescale.com> |
powerpc/fsl-booke: Remove num_tlbcam_entries
This is a global variable defined in fsl_booke_mmu.c with a value that gets
initialized in assembly code in head_fsl_booke.S.
It's never used.
If some code ever does want to know the number of entries in TLB1, then
"numcams = mfspr(SPRN_TLB1CFG) & 0xfff", is a whole lot simpler than a
global initialized during kernel boot from assembly.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 19f5465e823858a2f0b0e9a92e52816ba3ee70bb |
|
09-Dec-2008 |
Trent Piepho <tpiepho@freescale.com> |
powerpc/fsl-booke: Don't hard-code size of struct tlbcam
Some assembly code in head_fsl_booke.S hard-coded the size of struct tlbcam
to 20 when it indexed the TLBCAM table. Anyone changing the size of struct
tlbcam would not know to expect that.
The kernel already has a system to get the size of C structures into
assembly language files, asm-offsets, so let's use it.
The definition of the struct gets moved to a header, so that asm-offsets.c
can include it.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 7c03d653cd257793dc40520c94e229b5fd0578e7 |
|
18-Dec-2008 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
powerpc/mm: Introduce MMU features
We're soon running out of CPU features and I need to add some new
ones for various MMU related bits, so this patch separates the MMU
features from the CPU features. I moved over the 32-bit MMU related
ones, added base features for MMU type families, but didn't move
over any 64-bit only feature yet.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
|
| d5b26db2cfcf09f28f4839c8c3484279cd5ea5b3 |
|
19-Nov-2008 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for SMP initialization
Added 85xx specifc smp_ops structure. We use ePAPR style boot release
and the MPIC for IPIs at this point.
Additionally added routines for secondary cpu entry and initializtion.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 06b90969a7564fad888f67e9f7f4c3a51a16ef1d |
|
01-Dec-2008 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: minor head_fsl_booke.S cleanup
Removed unused branch labels
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| b3898895355f73973eb3aef3489e999d3fb8e2bc |
|
19-Nov-2008 |
Trent Piepho <tpiepho@freescale.com> |
powerpc: Better setup of boot page TLB entry
The initial TLB mapping for the kernel boot didn't set the memory coherent
attribute, MAS2[M], in SMP mode.
If this code supported booting a secondary processor, which it doesn't yet,
but if it did, then when a secondary processor boots, it would probably signal
the primary processor by setting a variable called something like
__secondary_hold_acknowledge. However, due to the lack of the M bit, the
primary processor would not snoop the transaction (even if a transaction were
broadcast). If primary CPU's L1 D-cache had a copy, it would not be flushed
and the CPU would never see the ack. Which would have resulted in the primary
CPU spinning for a long time, perhaps a full second before it gives up, while
it would have waited for the ack from the secondary CPU that it wouldn't have
been able to see because of the stale cache.
The value of MAS2 for the boot page TLB1 entry is a compile time constant,
so there is no need to calculate it in powerpc assembly language.
Also, from the MPC8572 manual section 6.12.5.3, "Bits that represent
offsets within a page are ignored and should be cleared." Existing code
didn't clear them, this code does.
The same when the page of KERNELBASE is found; we don't need to use asm to
mask the lower 12 bits off.
In the code that computes the address to rfi from, don't hard code the
offset to 24 bytes, but have the assembler figure that out for us.
Signed-off-by: Trent Piepho <tpiepho@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 6a800f36acd5bf06b5fe2cb27c4d0524d60c3df5 |
|
28-Oct-2008 |
Liu Yu <yu.liu@freescale.com> |
powerpc: Add SPE/EFP math emulation for E500v1/v2 processors.
This patch add the handlers of SPE/EFP exceptions.
The code is used to emulate float point arithmetic,
when MSR(SPE) is enabled and receive EFP data interrupt or EFP round interrupt.
This patch has no conflict with or dependence on FP math-emu.
The code has been tested by TestFloat.
Now the code doesn't support SPE/EFP instructions emulation
(it won't be called when receive program interrupt),
but it could be easily added.
Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 9bd54d185ab6c73f0cbd97b9f048394a3462193b |
|
10-Oct-2008 |
Milton Miller <miltonm@bga.com> |
powerpc: remove non-dependent load fsl_booke PTE_64BIT
b38fd42ff46a4a31dced8533e8a6e549693500b6 added false dependencys
to order the load of upper and lower halfs of the pte, but only
adjusted whitespace instead of deleting the old load in the iside
handler, letting the hardware see the non-dependent load.
This patch removes the extra load.
Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 4ee7084eb11e00eb02dc8435fd18273a61ffa9bf |
|
24-Sep-2008 |
Becky Bruce <becky.bruce@freescale.com> |
POWERPC: Allow 32-bit hashed pgtable code to support 36-bit physical
This rearranges a bit of code, and adds support for
36-bit physical addressing for configs that use a
hashed page table. The 36b physical support is not
enabled by default on any config - it must be
explicitly enabled via the config system.
This patch *only* expands the page table code to accomodate
large physical addresses on 32-bit systems and enables the
PHYS_64BIT config option for 86xx. It does *not*
allow you to boot a board with more than about 3.5GB of
RAM - for that, SWIOTLB support is also required (and
coming soon).
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| b38fd42ff46a4a31dced8533e8a6e549693500b6 |
|
16-Jul-2008 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl-booke: Fixup 64-bit PTE reading for SMP support
We need to create a false data dependency to ensure the loads of
the pte are done in the right order.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 0332f000cd010e9db0a04181284b9ac91dac5ea7 |
|
11-Jul-2008 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl: Minor TLBSYNC cleanup for FSL Book-E
Use the TLBSYNC macro defined in ppc_asm.h rather than our own ifdefs.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 6cfd8990e27d3a491c1c605d6cbc18a46ae51fef |
|
09-Jul-2008 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: rework FSL Book-E PTE access and TLB miss
This converts the FSL Book-E PTE access and TLB miss handling to match
with the recent changes to 44x that introduce support for non-atomic PTE
operations in pgtable-ppc32.h and removes write back to the PTE from
the TLB miss handlers. In addition, the DSI interrupt code no longer
tries to fixup write permission, this is left to generic code, and
_PAGE_HWWRITE is gone.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| fc4033b2f8b1482022bff3d05505a1b1631bb6de |
|
18-Jun-2008 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: add DOZE/NAP support for e500 core
The e500 core enter DOZE/NAP power-saving modes when the core go to
cpu_idle routine.
The power management default running mode is DOZE, If the user
echo 1 > /proc/sys/kernel/powersave-nap
the system will change to NAP running mode.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 3dfa8773674e16f95f70a0e631e80c69390d04d7 |
|
16-Jun-2008 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/booke: Add support for new e500mc core
The new e500mc core from Freescale is based on the e500v2 but with the
following changes:
* Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
* Floating Point
* No SPE
* Supports lwsync
* Doorbell Exceptions
* Hypervisor
* Cache line size is now 64-bytes (e500v1/v2 have a 32-byte cache line)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| bcf0b0880710409420a4e3b15dbf4b9a63542c0b |
|
30-Apr-2008 |
Kumar Gala <galak@kernel.crashing.org> |
[POWERPC] Move to runtime allocated exception stacks
For the additonal exception levels (critical, debug, machine check) on
40x/book-e we were using "static" allocations of the stack in the
associated head.S.
Move to a runtime allocation to make the code a bit easier to read as
we mimic how we handle IRQ stacks. Its also a bit easier to setup the
stack with a "dummy" thread_info in C code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Paul Mackerras <paulus@samba.org>
|
| 37dd2badcfcec35f5e21a0926968d77a404f03c3 |
|
21-Apr-2008 |
Kumar Gala <galak@kernel.crashing.org> |
[POWERPC] 85xx: Add support for relocatable kernel (and booting at non-zero)
Added support to allow an 85xx kernel to be run from a non-zero physical
address (useful for cooperative asymmetric multiprocessing situations and
kdump). The support can be configured at compile time by setting
CONFIG_PAGE_OFFSET, CONFIG_KERNEL_START, and CONFIG_PHYSICAL_START as
desired.
Alternatively, the kernel build can set CONFIG_RELOCATABLE. Setting this
config option causes the kernel to determine at runtime the physical
addresses of CONFIG_PAGE_OFFSET and CONFIG_KERNEL_START. If
CONFIG_RELOCATABLE is set, then CONFIG_PHYSICAL_START has no meaning.
However, CONFIG_PHYSICAL_START will always be used to set the LOAD program
header physical address field in the resulting ELF image.
Currently we are limited to running at a physical address that is a
multiple of 256M. This is due to how we map TLBs to cover
lowmem. This should be fixed to allow 64M or maybe even 16M alignment
in the future. It is considered an error to try and run a kernel at a
non-aligned physical address.
All the magic for this support is accomplished by proper initialization
of the kernel memory subsystem and use of ARCH_PFN_OFFSET.
The use of ARCH_PFN_OFFSET only affects normal memory and not IO mappings.
ioremap uses map_page and isn't affected by ARCH_PFN_OFFSET.
/dev/mem continues to allow access to any physical address in the system
regardless of how CONFIG_PHYSICAL_START is set.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
|
| eb0cd5fd295f469b4782d8088f3e39019da44707 |
|
09-Apr-2008 |
Kumar Gala <galak@kernel.crashing.org> |
[POWERPC] Rework Book-E debug exception handling
The architecture allows for "Book-E" style debug interrupts to either go
to critial interrupts of their own debug interrupt level. To allow for
a dynamic kernel to support machines of either type we want to be able to
compile in the interrupt handling code for both exception levels.
Towards this goal we renamed the debug handling macros to specify the
interrupt level in their name (DEBUG_CRIT_EXCEPTION/DebugCrit and
DEBUG_DEBUG_EXCEPTION/DebugDebug).
Additionally, on the Freescale Book-e parts we expanded the exception
stacks to cover the maximum case of needing three exception stacks (normal,
machine check and debug).
There is some kernel text space optimization to be gained if a kernel is
configured for a specific Freescale implementation but we aren't handling
that now to allow for the single kernel image support.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 0aef996b37d08757562ecf0bb0c1f6998e634c8b |
|
15-Apr-2008 |
Kumar Gala <galak@kernel.crashing.org> |
[POWERPC] 85xx: Cleanup TLB initialization
* Determine the RPN we are running the kernel at runtime rather
than using compile time constant for initial TLB
* Cleanup adjust_total_lowmem() to respect memstart_addr and
be a bit more clear on variables that are sizes vs addresses.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
|
| e8b63761554aca641bd9020447d487bfd85111bf |
|
22-Nov-2007 |
Dale Farnsworth <dale@farnsworth.org> |
[POWERPC] 85xx: Respect KERNELBASE, PAGE_OFFSET, and PHYSICAL_START on e500
The e500 MMU init code previously assumed KERNELBASE always equaled
PAGE_OFFSET and PHYSICAL_START was 0. This is useful for kdump
support as well as asymetric multicore.
For the initial kdump support the secondary kernel will run at 32M
but need access to all of memory so we bump the initial TLB up to
64M. This also matches with the forth coming ePAPR spec.
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| bee86f14d51a5a9a3b1897e301da1e415df0ba23 |
|
06-Dec-2007 |
Kumar Gala <galak@kernel.crashing.org> |
[POWERPC] Fix swapper_pg_dir size when CONFIG_PTE_64BIT=y on FSL_BOOKE
The size of swapper_pg_dir is 8k instead of 4k when using 64-bit PTEs
(CONFIG_PTE_64BIT).
This was reported by Cedric Hombourger <chombourger@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 8a13c4f972e6c107d8cff54de647544c00e25b41 |
|
11-Oct-2007 |
Kumar Gala <galak@kernel.crashing.org> |
[POWERPC] Use PAGE_OFFSET to tell if an address is user/kernel in SW TLB handlers
Move to using PAGE_OFFSET instead of TASK_SIZE or KERNELBASE value on
6xx/40x/44x/fsl-booke to determine if the faulting address is a kernel or
user space address. This mimics how the macro is_kernel_addr() works.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 3c5df5c26ed17828760945d59653a2e22e3fb63f |
|
27-Sep-2007 |
Kumar Gala <galak@kernel.crashing.org> |
[POWERPC] Cleaned up whitespace in head_fsl_booke.S
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 19a8d97d89442e2bda6245b8a3de2c1fec69a7ad |
|
17-Sep-2007 |
Stephen Rothwell <sfr@canb.auug.org.au> |
[POWERPC] Remove cmd_line from head*.S
It is just a C char array, so declare it thusly.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Paul Mackerras <paulus@samba.org>
|
| 748a768384e05c021ea6be221b80c62a83d7b520 |
|
13-Sep-2007 |
Kumar Gala <galak@kernel.crashing.org> |
[POWERPC] Fix modpost warnings from head*.S on ppc32
We get warnings like the following from the various ppc32 head*.S files:
WARNING: vmlinux.o(.text+0x358): Section mismatch: reference to .init.text:early_init (between 'skpinv' and 'interrupt_base')
WARNING: vmlinux.o(.text+0x380): Section mismatch: reference to .init.text:machine_init (between 'skpinv' and 'interrupt_base')
WARNING: vmlinux.o(.text+0x384): Section mismatch: reference to .init.text:MMU_init (between 'skpinv' and 'interrupt_base')
WARNING: vmlinux.o(.text+0x3aa): Section mismatch: reference to .init.text:start_kernel (between 'skpinv' and 'interrupt_base')
WARNING: vmlinux.o(.text+0x3ae): Section mismatch: reference to .init.text:start_kernel (between 'skpinv' and 'interrupt_base')
Added a .text.head section simliar to what other architectures do since
modpost already excludes this from its warnings.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 02ed82ccc5171bc3c88666568edcb71f3d4a79f6 |
|
13-Feb-2007 |
Becky Bruce <bgill@freescale.com> |
[POWERPC] 85xx: Drop use of SYNC macro in head_fsl_booke.S
Eliminate needless invocation of the SYNC macro (which always evaluates to
nothing on BookE) from head_fsl_booke.S (for both arch/ppc & arch/powerpc).
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 8ce0a7df6e6117d8814e976d4b7ce6a6b2c9cf93 |
|
13-Feb-2007 |
Becky Bruce <bgill@freescale.com> |
[POWERPC] 85xx: Don't write reserved values to MAS1[TSIZE]
Some of the current tlbwe instructions early on in head_fsl_booke.S take
advantage of unarchitected behavior that allows the writing of reserved
values to the TSIZE field. This patch corrects that, as well as an error
where an uninitialized (by linux) value was written into a MAS register and
used for a tlbwe.
Correct this for both arch/ppc and arch/powerpc.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| 6ab3d5624e172c553004ecc862bfeac16d9d68b7 |
|
30-Jun-2006 |
Jörn Engel <joern@wohnheim.fh-wedel.de> |
Remove obsolete #include <linux/config.h>
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
|
| 2ef9481e666b4654159ac9f847e6963809e3c470 |
|
23-Jan-2006 |
Jon Mason <jdmason@us.ibm.com> |
[PATCH] powerpc: trivial: modify comments to refer to new location of files
This patch removes all self references and fixes references to files
in the now defunct arch/ppc64 tree. I think this accomplises
everything wanted, though there might be a few references I missed.
Signed-off-by: Jon Mason <jdmason@us.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
|
| a7cb03375d794d3494561bbad90aeab13ff7e4d0 |
|
08-Feb-2006 |
Becky Bruce <bgill@freescale.com> |
[PATCH] powerpc/ppc: Add missing isyncs in head_fsl_booke.S
The e500 core reference manual indicates that isync is required
after mtmsr(DE bit) and mtspr DBCR0. Add isyncs to make the code
conform to the spec.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
|
| 4c8d3d997ef3c0594350fba716529905b314287e |
|
14-Nov-2005 |
Kumar Gala <galak@gate.crashing.org> |
[PATCH] Update email address for Kumar
Changed jobs and the Freescale address is no longer valid.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
|
| ea703ce20699dd85ad7954e34b71a2c7c47b6132 |
|
12-Oct-2005 |
Kumar Gala <galak@freescale.com> |
[PATCH] powerpc: replace use of _GLOBAL with .globl
The _GLOBAL() macro is for text symbols only. Changed to using
.globl for .data symbols.
Signed-off-by: Kumar K. Gala <kumar.gala@freescale.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
|
| dc1c1ca3dcd94c545c5e01d7c06b46824d43f4d0 |
|
01-Oct-2005 |
Stephen Rothwell <sfr@canb.auug.org.au> |
powerpc: merge idle_power4.S and trapc.s
Use idle_power4.S from ppc64 as we are not going to support
32 bit power4 in the merged tree.
Merge ppc64 traps.c into powerpc traps.c:
use ppc64 versions of exception routine names
(as they don't have StudlyCaps)
make all the versions if die() have the same
prototype
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
|
| 14cf11af6cf608eb8c23e989ddb17a715ddce109 |
|
26-Sep-2005 |
Paul Mackerras <paulus@samba.org> |
powerpc: Merge enough to start building in arch/powerpc.
This creates the directory structure under arch/powerpc and a bunch
of Kconfig files. It does a first-cut merge of arch/powerpc/mm,
arch/powerpc/lib and arch/powerpc/platforms/powermac. This is enough
to build a 32-bit powermac kernel with ARCH=powerpc.
For now we are getting some unmerged files from arch/ppc/kernel and
arch/ppc/syslib, or arch/ppc64/kernel. This makes some minor changes
to files in those directories and files outside arch/powerpc.
The boot directory is still not merged. That's going to be interesting.
Signed-off-by: Paul Mackerras <paulus@samba.org>
|