40d158e61840fbbe23be3f37302a3ca237c15491 |
|
11-May-2013 |
Al Viro <viro@zeniv.linux.org.uk> |
consolidate io_remap_pfn_range definitions Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
|
65d517eb7224d24ee4206416161390f30d69e622 |
|
31-May-2011 |
Paul Mundt <lethal@linux-sh.org> |
sh64: asm/pgtable.h needs asm/mmu.h Needed to satisfy the __in_29bit_mode() check. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
8f82f0c7029d39b499389c8e225cf147fb83abe2 |
|
14-Jan-2011 |
Paul Mundt <lethal@linux-sh.org> |
sh: Fix up breakage from asm-generic/pgtable.h changes. We require a forward declaration for mm_struct: In file included from arch/sh/include/asm/pgtable.h:163, from arch/sh/include/asm/io.h:21, from arch/sh/kernel/machvec.c:20: include/asm-generic/pgtable.h:104: error: 'struct mm_struct' declared inside parameter list include/asm-generic/pgtable.h: In function 'ptep_get_and_clear_full': include/asm-generic/pgtable.h:107: error: passing argument 1 of 'ptep_get_and_clear' from incompatible pointer type include/asm-generic/pgtable.h:70: note: expected 'struct mm_struct *' but argument is of type 'struct mm_struct *' Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
ccedb20c6879ac0237b95b3500d69822f1e5e2ea |
|
03-Nov-2010 |
Paul Mundt <lethal@linux-sh.org> |
sh: Simplify phys_addr_mask()/PTE_PHYS_MASK for 29/32-bit. Given that __in_29bit_mode() is a constant for the non-PMB case, we can simply use the PMB-facing version of phys_addr_mask() and drop the other variants. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
a16382ce1cbcc3ab12274e20f92c09c439629162 |
|
27-Oct-2010 |
Paul Mundt <lethal@linux-sh.org> |
sh64: _PAGE_SPECIAL support. Now that sh64 has grown extended page flag support we finally have a free bit for _PAGE_SPECIAL. Wire it up. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
4b3073e1c53a256275f1079c0fbfbe85883d9275 |
|
18-Dec-2009 |
Russell King <rmk+kernel@arm.linux.org.uk> |
MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself On VIVT ARM, when we have multiple shared mappings of the same file in the same MM, we need to ensure that we have coherency across all copies. We do this via make_coherent() by making the pages uncacheable. This used to work fine, until we allowed highmem with highpte - we now have a page table which is mapped as required, and is not available for modification via update_mmu_cache(). Ralf Beache suggested getting rid of the PTE value passed to update_mmu_cache(): On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables to construct a pointer to the pte again. Passing a pte_t * is much more elegant. Maybe we might even replace the pte argument with the pte_t? Ben Herrenschmidt would also like the pte pointer for PowerPC: Passing the ptep in there is exactly what I want. I want that -instead- of the PTE value, because I have issue on some ppc cases, for I$/D$ coherency, where set_pte_at() may decide to mask out the _PAGE_EXEC. So, pass in the mapped page table pointer into update_mmu_cache(), and remove the PTE value, updating all implementations and call sites to suit. Includes a fix from Stephen Rothwell: sparc: fix fallout from update_mmu_cache API change Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
e44d6c4010a4c84369013932eea4721d16cbc08d |
|
13-Jan-2010 |
Paul Mundt <lethal@linux-sh.org> |
sh: Rename split-level pgtable headers. These were originally named _nopmd and _pmd to follow their asm-generic counterparts, but we rename them to -2level and -3level for general consistency. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
782bb5a532f883540bf403afb19f735a4eefd95b |
|
13-Jan-2010 |
Paul Mundt <lethal@linux-sh.org> |
sh: default to extended TLB support. All SH-X2 and SH-X3 parts support an extended TLB mode, which has been left as experimental since support was originally merged. Now that it's had some time to stabilize and get some exposure to various platforms, we can drop it as an option and default enable it across the board. This is also good future proofing for newer parts that will drop support for the legacy TLB mode completely. This will also force 3-level page tables for all newer parts, which is necessary both for the varying page sizes and larger memories. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
2a5eacca85d39d8b6dffae821d7d260f05584dc7 |
|
31-Dec-2009 |
Matt Fleming <matt@console-pimps.org> |
sh: Move page table allocation out of line We also switched away from quicklists and instead moved to slab caches. After benchmarking both implementations the difference is negligible. The slab caches suit us better though because the size of a pgd table is just 4 entries when we're using a 3-level page table layout and quicklists always deal with pages. Signed-off-by: Matt Fleming <matt@console-pimps.org>
|
5d9b4b19f118abfb75e352841f7bf74580d7e427 |
|
13-Dec-2009 |
Matt Fleming <matt@console-pimps.org> |
sh: Definitions for 3-level page table layout If using 64-bit PTEs and 4K pages then each page table has 512 entries (as opposed to 1024 entries with 32-bit PTEs). Unlike MIPS, SH follows the convention that all structures in the page table (pgd_t, pmd_t, pgprot_t, etc) must be the same size. Therefore, 64-bit PTEs require 64-bit PGD entries, etc. Using 2-levels of page tables and 64-bit PTEs it is only possible to map 1GB of virtual address space. In order to map all 4GB of virtual address space we need to adopt a 3-level page table layout. This actually works out better for CONFIG_SUPERH32 because we only waste 2 PGD entries on the P1 and P2 areas (which are untranslated) instead of 256. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
b73c806341cfc7492ede6a2ce713cb579547d0ab |
|
25-Nov-2009 |
Matt Fleming <matt@console-pimps.org> |
sh: Abstract the number of page table levels Keep the dimensions of the page tables in a separate header file in preparation for allowing a three level page table structure. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
2a8bc923455f320da6c460258c21d2235ab2edc8 |
|
10-Oct-2009 |
Paul Mundt <lethal@linux-sh.org> |
sh: Shut up CONFIG_32BIT=n compiler warnings. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
1f69b6af9171f50135cce8023c84d82fbf42a8f5 |
|
06-Oct-2009 |
Matt Fleming <matt@console-pimps.org> |
sh: Prepare for dynamic PMB support To allow the MMU to be switched between 29bit and 32bit mode at runtime some constants need to swapped for functions that return a runtime value. Signed-off-by: Matt Fleming <matt@console-pimps.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
2739742c24f1a55365e71f0722bfdce8994e9c4e |
|
15-Aug-2009 |
Paul Mundt <lethal@linux-sh.org> |
sh: Provide the kmap_coherent() interface generically. This plugs in kmap_coherent() for the non-SH4 cases to permit the pg-mmu.c bits to be used generically across all CPUs. SH-5 is still in the TODO state, but will move over to fixmap and the generic interface gradually. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
c7914834ef3b8a396b7e82ea34ac07cdcfe6f868 |
|
04-Aug-2009 |
Paul Mundt <lethal@linux-sh.org> |
sh: Tidy up NEFF-based sign extension for SH-5. This consolidates all of the NEFF-based sign extension for SH-5. In the future the other SH code will need to make use of this as well, so make it generic in preparation for more 32/64 consolidation. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
9cef7492696a416663b4edb953a4eade8517ebeb |
|
28-Jul-2009 |
Paul Mundt <lethal@linux-sh.org> |
sh: update_mmu_cache() consolidation. This splits out a separate __update_cache()/__update_tlb() for update_mmu_cache() to wrap in to. This lets us share the common __update_cache() bits while keeping special __update_tlb() handling broken out. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
0dfae7d5a21901b28ec0452d71be64adf5ea323e |
|
27-Jul-2009 |
Paul Mundt <lethal@linux-sh.org> |
sh: Use the now generic SH-4 clear/copy page ops for all MMU platforms. Now that the SH-4 page clear/copy ops are generic, they can be used for all platforms with CONFIG_MMU=y. SH-5 remains the odd one out, but it too will gradually be converted over to using this interface. SH-3 platforms which do not contain aliases will see no impact from this change, while aliasing SH-3 platforms will get the same interface as SH-4. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
dfff0fa65ab15db45acd64b3189787d37ab163cd |
|
27-Jul-2009 |
Paul Mundt <lethal@linux-sh.org> |
sh: wire up clear_user_highpage() for sh4, convert sh7705. This wires up clear_user_highpage() on SH-4 and subsequently converts the SH7705 32kB cache mode over to using it. Now that the SH-4 implementation handles all of the dcache purging directly in the aliasing case, there is no need to do this in the default clear_page() implementation. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
2277ab4a1df50e05bc732fe9488d4e902bb8399a |
|
22-Jul-2009 |
Paul Mundt <lethal@linux-sh.org> |
sh: Migrate from PG_mapped to PG_dcache_dirty. This inverts the delayed dcache flush a bit to be more in line with other platforms. At the same time this also gives us the ability to do some more optimizations and cleanup. Now that the update_mmu_cache() callsite only tests for the bit, the implementation can gradually be split out and made generic, rather than relying on special implementations for each of the peculiar CPU types. SH7705 in 32kB mode and SH-4 still need slightly different handling, but this is something that can remain isolated in the varying page copy/clear routines. On top of that, SH-X3 is dcache coherent, so there is no need to bother with any of these tests in the PTEAEX version of update_mmu_cache(), so we kill that off too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
ee1acbfabd5270b40ce2cfdc202070b7ca91cdff |
|
07-May-2009 |
Paul Mundt <lethal@linux-sh.org> |
sh: Handle shm_align_mask also for HAVE_ARCH_UNMAPPED_AREA_TOPDOWN. Presently shm_align_mask is only looked at for the bottom up case, but we still want this for proper colouring constraints in the topdown case. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
acca4f4d9bd657e8bc7e1665ba5077465138f133 |
|
10-Nov-2008 |
Paul Mundt <lethal@linux-sh.org> |
sh: Handle fixmap TLB eviction more coherently. There was a race in the kmap_coherent() implementation. While we guarded against preemption, there was nothing preventing eviction of the pre-faulted fixmap entry from the UTLB. Under certain workloads this would result in the fixmap entries used for cache colouring being evicted from the UTLB in the midst of a copy_page(). In addition to pre-faulting, we also make sure to preserve the PTEs in the kernel page table and introduce a cached PTE for kmap_coherent() usage. This follows a similar change on MIPS ("[MIPS] Fix aliasing bug in copy_to_user_page / copy_from_user_page"). Reported-by: Hideo Saito <saito@densan.co.jp> Reported-by: CHIKAMA Masaki <masaki.chikama@gmail.com> Tested-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
cb700aa4f13d38726defab3060d3ebeaf67dc189 |
|
12-Sep-2008 |
Paul Mundt <lethal@linux-sh.org> |
sh: ioremap_prot support. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|
f15cbe6f1a4b4d9df59142fc8e4abb973302cf44 |
|
29-Jul-2008 |
Paul Mundt <lethal@linux-sh.org> |
sh: migrate to arch/sh/include/ This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
|