| 126eb08820a2c97c10ea58e73a544c2f075d59a7 |
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16-Sep-2013 |
Chris Metcalf <cmetcalf@tilera.com> |
tile: improve gxio iorpc autogenerated code style
Fix some whitespace style issues in some auto-generated files.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
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| 90d9dd66957a744831146dbb1a9e4f96a9106100 |
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02-Aug-2013 |
Chris Metcalf <cmetcalf@tilera.com> |
tile PCI RC: support more MSI-X interrupt vectors
To support PCIe devices with higher number of MSI-X interrupt vectors,
e.g. 16 for the LSI RAID card, enhance the Gx RC stack to provide more
MSI-X vectors by using the TRIO Scatter Queues, which provide 8 more
vectors in addition to ~10 from the Map Mem regions.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
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| bce5bbbb23f780a792be7e594af7cd4b4aae1cd4 |
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07-Apr-2012 |
Chris Metcalf <cmetcalf@tilera.com> |
arch/tile: provide kernel support for the tilegx TRIO shim
Provide kernel support for the tilegx "Transaction I/O" (TRIO) on-chip
hardware. This hardware implements the PCIe interface for tilegx;
the driver changes to use TRIO for PCIe are in a subsequent commit.
The change is layered on top of the tilegx GXIO IORPC subsystem.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
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